1/* 2 * This code was extracted from: 3 * git://github.com/gonzoua/u-boot-pi.git master 4 * and hence presumably (C) 2012 Oleksandr Tymoshenko 5 * 6 * Tweaks for U-Boot upstreaming 7 * (C) 2012 Stephen Warren 8 * 9 * Portions (e.g. read/write macros, concepts for back-to-back register write 10 * timing workarounds) obviously extracted from the Linux kernel at: 11 * https://github.com/raspberrypi/linux.git rpi-3.6.y 12 * 13 * The Linux kernel code has the following (c) and license, which is hence 14 * propagated to Oleksandr's tree and here: 15 * 16 * Support for SDHCI device on 2835 17 * Based on sdhci-bcm2708.c (c) 2010 Broadcom 18 * 19 * This program is free software; you can redistribute it and/or modify 20 * it under the terms of the GNU General Public License version 2 as 21 * published by the Free Software Foundation. 22 * 23 * This program is distributed in the hope that it will be useful, 24 * but WITHOUT ANY WARRANTY; without even the implied warranty of 25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 26 * GNU General Public License for more details. 27 * 28 * You should have received a copy of the GNU General Public License 29 * along with this program; if not, write to the Free Software 30 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 31 */ 32 33/* Supports: 34 * SDHCI platform device - Arasan SD controller in BCM2708 35 * 36 * Inspired by sdhci-pci.c, by Pierre Ossman 37 */ 38 39#include <common.h> 40#include <dm.h> 41#include <log.h> 42#include <malloc.h> 43#include <memalign.h> 44#include <sdhci.h> 45#include <time.h> 46#include <asm/arch/msg.h> 47#include <asm/arch/mbox.h> 48#include <mach/sdhci.h> 49#include <mach/timer.h> 50 51/* 400KHz is max freq for card ID etc. Use that as min */ 52#define MIN_FREQ 400000 53#define SDHCI_BUFFER 0x20 54 55struct bcm2835_sdhci_plat { 56 struct mmc_config cfg; 57 struct mmc mmc; 58}; 59 60struct bcm2835_sdhci_host { 61 struct sdhci_host host; 62 uint twoticks_delay; 63 ulong last_write; 64}; 65 66static inline struct bcm2835_sdhci_host *to_bcm(struct sdhci_host *host) 67{ 68 return (struct bcm2835_sdhci_host *)host; 69} 70 71static inline void bcm2835_sdhci_raw_writel(struct sdhci_host *host, u32 val, 72 int reg) 73{ 74 struct bcm2835_sdhci_host *bcm_host = to_bcm(host); 75 76 /* 77 * The Arasan has a bugette whereby it may lose the content of 78 * successive writes to registers that are within two SD-card clock 79 * cycles of each other (a clock domain crossing problem). 80 * It seems, however, that the data register does not have this problem. 81 * (Which is just as well - otherwise we'd have to nobble the DMA engine 82 * too) 83 */ 84 if (reg != SDHCI_BUFFER) { 85 while (timer_get_us() - bcm_host->last_write < 86 bcm_host->twoticks_delay) 87 ; 88 } 89 90 writel(val, host->ioaddr + reg); 91 bcm_host->last_write = timer_get_us(); 92} 93 94static inline u32 bcm2835_sdhci_raw_readl(struct sdhci_host *host, int reg) 95{ 96 return readl(host->ioaddr + reg); 97} 98 99static void bcm2835_sdhci_writel(struct sdhci_host *host, u32 val, int reg) 100{ 101 bcm2835_sdhci_raw_writel(host, val, reg); 102} 103 104static void bcm2835_sdhci_writew(struct sdhci_host *host, u16 val, int reg) 105{ 106 static u32 shadow; 107 u32 oldval = (reg == SDHCI_COMMAND) ? shadow : 108 bcm2835_sdhci_raw_readl(host, reg & ~3); 109 u32 word_num = (reg >> 1) & 1; 110 u32 word_shift = word_num * 16; 111 u32 mask = 0xffff << word_shift; 112 u32 newval = (oldval & ~mask) | (val << word_shift); 113 114 if (reg == SDHCI_TRANSFER_MODE) 115 shadow = newval; 116 else 117 bcm2835_sdhci_raw_writel(host, newval, reg & ~3); 118} 119 120static void bcm2835_sdhci_writeb(struct sdhci_host *host, u8 val, int reg) 121{ 122 u32 oldval = bcm2835_sdhci_raw_readl(host, reg & ~3); 123 u32 byte_num = reg & 3; 124 u32 byte_shift = byte_num * 8; 125 u32 mask = 0xff << byte_shift; 126 u32 newval = (oldval & ~mask) | (val << byte_shift); 127 128 bcm2835_sdhci_raw_writel(host, newval, reg & ~3); 129} 130 131static u32 bcm2835_sdhci_readl(struct sdhci_host *host, int reg) 132{ 133 u32 val = bcm2835_sdhci_raw_readl(host, reg); 134 135 return val; 136} 137 138static u16 bcm2835_sdhci_readw(struct sdhci_host *host, int reg) 139{ 140 u32 val = bcm2835_sdhci_raw_readl(host, (reg & ~3)); 141 u32 word_num = (reg >> 1) & 1; 142 u32 word_shift = word_num * 16; 143 u32 word = (val >> word_shift) & 0xffff; 144 145 return word; 146} 147 148static u8 bcm2835_sdhci_readb(struct sdhci_host *host, int reg) 149{ 150 u32 val = bcm2835_sdhci_raw_readl(host, (reg & ~3)); 151 u32 byte_num = reg & 3; 152 u32 byte_shift = byte_num * 8; 153 u32 byte = (val >> byte_shift) & 0xff; 154 155 return byte; 156} 157 158static const struct sdhci_ops bcm2835_ops = { 159 .write_l = bcm2835_sdhci_writel, 160 .write_w = bcm2835_sdhci_writew, 161 .write_b = bcm2835_sdhci_writeb, 162 .read_l = bcm2835_sdhci_readl, 163 .read_w = bcm2835_sdhci_readw, 164 .read_b = bcm2835_sdhci_readb, 165}; 166 167static int bcm2835_sdhci_bind(struct udevice *dev) 168{ 169 struct bcm2835_sdhci_plat *plat = dev_get_plat(dev); 170 171 return sdhci_bind(dev, &plat->mmc, &plat->cfg); 172} 173 174static int bcm2835_sdhci_probe(struct udevice *dev) 175{ 176 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 177 struct bcm2835_sdhci_plat *plat = dev_get_plat(dev); 178 struct bcm2835_sdhci_host *priv = dev_get_priv(dev); 179 struct sdhci_host *host = &priv->host; 180 fdt_addr_t base; 181 int emmc_freq; 182 int ret; 183 int clock_id = (int)dev_get_driver_data(dev); 184 185 base = dev_read_addr(dev); 186 if (base == FDT_ADDR_T_NONE) 187 return -EINVAL; 188 189 ret = bcm2835_get_mmc_clock(clock_id); 190 if (ret < 0) { 191 debug("%s: Failed to set MMC clock (err=%d)\n", __func__, ret); 192 return ret; 193 } 194 emmc_freq = ret; 195 196 /* 197 * See the comments in bcm2835_sdhci_raw_writel(). 198 * 199 * This should probably be dynamically calculated based on the actual 200 * frequency. However, this is the longest we'll have to wait, and 201 * doesn't seem to slow access down too much, so the added complexity 202 * doesn't seem worth it for now. 203 * 204 * 1/MIN_FREQ is (max) time per tick of eMMC clock. 205 * 2/MIN_FREQ is time for two ticks. 206 * Multiply by 1000000 to get uS per two ticks. 207 * +1 for hack rounding. 208 */ 209 priv->twoticks_delay = ((2 * 1000000) / MIN_FREQ) + 1; 210 priv->last_write = 0; 211 212 host->name = dev->name; 213 host->ioaddr = (void *)(uintptr_t)base; 214 host->quirks = SDHCI_QUIRK_BROKEN_VOLTAGE | SDHCI_QUIRK_BROKEN_R1B | 215 SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_NO_HISPD_BIT; 216 host->max_clk = emmc_freq; 217 host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 218 host->ops = &bcm2835_ops; 219 220 host->mmc = &plat->mmc; 221 host->mmc->dev = dev; 222 223 ret = sdhci_setup_cfg(&plat->cfg, host, emmc_freq, MIN_FREQ); 224 if (ret) { 225 debug("%s: Failed to setup SDHCI (err=%d)\n", __func__, ret); 226 return ret; 227 } 228 229 upriv->mmc = &plat->mmc; 230 host->mmc->priv = host; 231 232 return sdhci_probe(dev); 233} 234 235static const struct udevice_id bcm2835_sdhci_match[] = { 236 { 237 .compatible = "brcm,bcm2835-sdhci", 238 .data = BCM2835_MBOX_CLOCK_ID_EMMC 239 }, 240 { 241 .compatible = "brcm,bcm2711-emmc2", 242 .data = BCM2835_MBOX_CLOCK_ID_EMMC2 243 }, 244 { /* sentinel */ } 245}; 246 247U_BOOT_DRIVER(sdhci_cdns) = { 248 .name = "sdhci-bcm2835", 249 .id = UCLASS_MMC, 250 .of_match = bcm2835_sdhci_match, 251 .bind = bcm2835_sdhci_bind, 252 .probe = bcm2835_sdhci_probe, 253 .priv_auto = sizeof(struct bcm2835_sdhci_host), 254 .plat_auto = sizeof(struct bcm2835_sdhci_plat), 255 .ops = &sdhci_ops, 256}; 257