1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * (C) Copyright 2002-2010
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 */
6
7#ifndef	__ASM_GBL_DATA_H
8#define __ASM_GBL_DATA_H
9
10#ifndef __ASSEMBLY__
11
12#include <linux/types.h>
13#include <asm/processor.h>
14#include <asm/mrccache.h>
15
16enum pei_boot_mode_t {
17	PEI_BOOT_NONE = 0,
18	PEI_BOOT_SOFT_RESET,
19	PEI_BOOT_RESUME,
20
21};
22
23struct dimm_info {
24	uint32_t dimm_size;
25	uint16_t ddr_type;
26	uint16_t ddr_frequency;
27	uint8_t rank_per_dimm;
28	uint8_t channel_num;
29	uint8_t dimm_num;
30	uint8_t bank_locator;
31	/* The 5th byte is '\0' for the end of string */
32	uint8_t serial[5];
33	/* The 19th byte is '\0' for the end of string */
34	uint8_t module_part_number[19];
35	uint16_t mod_id;
36	uint8_t mod_type;
37	uint8_t bus_width;
38} __packed;
39
40struct pei_memory_info {
41	uint8_t dimm_cnt;
42	/* Maximum num of dimm is 8 */
43	struct dimm_info dimm[8];
44} __packed;
45
46struct memory_area {
47	uint64_t start;
48	uint64_t size;
49};
50
51struct memory_info {
52	int num_areas;
53	uint64_t total_memory;
54	uint64_t total_32bit_memory;
55	struct memory_area area[CONFIG_NR_DRAM_BANKS];
56};
57
58#define MAX_MTRR_REQUESTS	8
59
60/**
61 * A request for a memory region to be set up in a particular way. These
62 * requests are processed before board_init_r() is called. They are generally
63 * optional and can be ignored with some performance impact.
64 */
65struct mtrr_request {
66	int type;		/* MTRR_TYPE_... */
67	uint64_t start;
68	uint64_t size;
69};
70
71/**
72 * struct mrc_output - holds the MRC data
73 *
74 * @buf: MRC training data to save for the next boot. This is set to point to
75 *	the raw data after SDRAM init is complete. Then mrccache_setup()
76 *	turns it into a proper cache record with a checksum
77 * @len: Length of @buf
78 * @cache: Resulting cache record
79 */
80struct mrc_output {
81	char *buf;
82	uint len;
83	struct mrc_data_container *cache;
84};
85
86/* Architecture-specific global data */
87struct arch_global_data {
88	u64 gdt[X86_GDT_NUM_ENTRIES] __aligned(16);
89	struct global_data *gd_addr;	/* Location of Global Data */
90	uint8_t x86;			/* CPU family */
91	uint8_t x86_vendor;		/* CPU vendor */
92	uint8_t x86_model;
93	uint8_t x86_mask;
94	uint32_t x86_device;
95	uint64_t tsc_base;		/* Initial value returned by rdtsc() */
96	bool tsc_inited;		/* true if tsc is ready for use */
97	unsigned long clock_rate;	/* Clock rate of timer in Hz */
98	void *new_fdt;			/* Relocated FDT */
99	uint32_t bist;			/* Built-in self test value */
100	enum pei_boot_mode_t pei_boot_mode;
101	const struct pch_gpio_map *gpio_map;	/* board GPIO map */
102	struct memory_info meminfo;	/* Memory information */
103	struct pei_memory_info pei_meminfo;	/* PEI memory information */
104#ifdef CONFIG_USE_HOB
105	void *hob_list;			/* FSP HOB list */
106#endif
107	struct mtrr_request mtrr_req[MAX_MTRR_REQUESTS];
108	int mtrr_req_count;
109	int has_mtrr;
110	/* MRC training data */
111	struct mrc_output mrc[MRC_TYPE_COUNT];
112	ulong table;			/* Table pointer from previous loader */
113	int turbo_state;		/* Current turbo state */
114	struct irq_routing_table *pirq_routing_table;
115	int dw_i2c_num_cards;		/* Used by designware i2c driver */
116#ifdef CONFIG_SEABIOS
117	u32 high_table_ptr;
118	u32 high_table_limit;
119#endif
120	int prev_sleep_state;		/* Previous sleep state ACPI_S0/1../5 */
121	ulong backup_mem;		/* Backup memory address for S3 */
122#ifdef CONFIG_FSP_VERSION2
123	struct fsp_header *fsp_s_hdr;	/* Pointer to FSP-S header */
124#endif
125	void *itss_priv;		/* Private ITSS data pointer */
126	ulong coreboot_table;		/* Address of coreboot table */
127	ulong table_start;		/* Start address of x86 tables */
128	ulong table_end;		/* End address of x86 tables */
129	ulong table_start_high;		/* Start address of high x86 tables */
130	ulong table_end_high;		/* End address of high x86 tables */
131	ulong smbios_start;		/* Start address of SMBIOS table */
132};
133
134#endif
135
136#include <asm-generic/global_data.h>
137
138#ifndef __ASSEMBLY__
139# if defined(CONFIG_EFI_APP) || CONFIG_IS_ENABLED(X86_64)
140
141/* TODO(sjg@chromium.org): Consider using a fixed register for gd on x86_64 */
142#define gd global_data_ptr
143
144#define DECLARE_GLOBAL_DATA_PTR   extern struct global_data *global_data_ptr
145# else
146static inline notrace gd_t *get_fs_gd_ptr(void)
147{
148	gd_t *gd_ptr;
149
150#if CONFIG_IS_ENABLED(X86_64)
151	asm volatile("fs mov 0, %0\n" : "=r" (gd_ptr));
152#else
153	asm volatile("fs movl 0, %0\n" : "=r" (gd_ptr));
154#endif
155
156	return gd_ptr;
157}
158
159#define gd	get_fs_gd_ptr()
160
161#define DECLARE_GLOBAL_DATA_PTR
162# endif
163
164#endif
165
166#endif /* __ASM_GBL_DATA_H */
167