1108768Strhodes/* SPDX-License-Identifier: GPL-2.0+ */ 2108768Strhodes/* 3108768Strhodes * (C) Copyright 2011 4108768Strhodes * Marvell Semiconductor <www.marvell.com> 5133338Ssimon * Written-by: Lei Wen <leiwen@marvell.com> 6108768Strhodes */ 7108768Strhodes 8108768Strhodes/* 9108768Strhodes * This file should be included in board config header file. 10108768Strhodes * 11108768Strhodes * It supports common definitions for Kirkwood platform 12158762Sbrueffer */ 13158762Sbrueffer 14158762Sbrueffer#ifndef _KW_CONFIG_H 15158762Sbrueffer#define _KW_CONFIG_H 16158762Sbrueffer 17158762Sbrueffer#if defined (CONFIG_KW88F6281) 18158762Sbrueffer#include <asm/arch/kw88f6281.h> 19158762Sbrueffer#elif defined (CONFIG_KW88F6192) 20158762Sbrueffer#include <asm/arch/kw88f6192.h> 21158762Sbrueffer#else 22158762Sbrueffer#error "SOC Name not defined" 23158762Sbrueffer#endif /* CONFIG_KW88F6281 */ 24158762Sbrueffer 25158762Sbrueffer#include <asm/arch/soc.h> 26108768Strhodes 27108768Strhodes#define CFG_I2C_MVTWSI_BASE0 KW_TWSI_BASE 28108768Strhodes#define MV_UART_CONSOLE_BASE KW_UART0_BASE 29108768Strhodes#define MV_SATA_BASE KW_SATA_BASE 30108768Strhodes#define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET 31108768Strhodes#define MV_SATA_PORT1_OFFSET KW_SATA_PORT1_OFFSET 32108768Strhodes 33108768Strhodes/* 34111447Sru * NAND configuration 35111447Sru */ 36133336Ssimon#ifdef CONFIG_CMD_NAND 37111447Sru#define CFG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */ 38111447Sru#define NAND_ALLOW_ERASE_ALL 1 39111447Sru#endif 40111447Sru 41133336Ssimon/* 42111447Sru * IDE Support on SATA ports 43111447Sru */ 44111447Sru#ifdef CONFIG_IDE 45111447Sru#define __io 46111447Sru/* Data, registers and alternate blocks are at the same offset */ 47111447Sru/* Each 8-bit ATA register is aligned to a 4-bytes address */ 48111447Sru/* CONFIG_IDE requires some #defines for ATA registers */ 49111447Sru/* ATA registers base is at SATA controller base */ 50111447Sru#endif /* CONFIG_IDE */ 51111447Sru 52111447Sru/* Use common timer */ 53111447Sru#ifndef CONFIG_TIMER 54111447Sru#define CFG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14) 55111447Sru#define CFG_SYS_TIMER_RATE CFG_SYS_TCLK 56111447Sru#endif 57111447Sru 58111447Sru#endif /* _KW_CONFIG_H */ 59111447Sru