1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * (C) Copyright 2009
4 * Marvell Semiconductor <www.marvell.com>
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6 */
7
8#ifndef _ASM_CACHE_H
9#define _ASM_CACHE_H
10
11#include <asm/system.h>
12
13#ifndef CONFIG_ARM64
14
15/*
16 * Invalidate L2 Cache using co-proc instruction
17 */
18#if CONFIG_IS_ENABLED(SYS_THUMB_BUILD)
19void invalidate_l2_cache(void);
20#else
21static inline void invalidate_l2_cache(void)
22{
23	unsigned int val=0;
24
25	asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache"
26		: : "r" (val) : "cc");
27	isb();
28}
29#endif
30
31int check_cache_range(unsigned long start, unsigned long stop);
32
33void l2_cache_enable(void);
34void l2_cache_disable(void);
35void set_section_dcache(int section, enum dcache_option option);
36
37void arm_init_before_mmu(void);
38void cpu_cache_initialization(void);
39void dram_bank_mmu_setup(int bank);
40
41#endif
42
43/*
44 * The value of the largest data cache relevant to DMA operations shall be set
45 * for us in CONFIG_SYS_CACHELINE_SIZE.  In some cases this may be a larger
46 * value than found in the L1 cache but this is OK to use in terms of
47 * alignment.
48 */
49#define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
50
51/*
52 * arm_reserve_mmu() - Reserve memory for MMU TLB table
53 *
54 * Default implementation for reserving memory for MMU TLB table. It is used
55 * during generic board init sequence in common/board_f.c. Weakly defined, so
56 * that machines can override it if needed.
57 *
58 * Return: 0 if OK
59 */
60int arm_reserve_mmu(void);
61
62#endif /* _ASM_CACHE_H */
63