1/* 2 * (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#ifndef _SUNXI_CPU_SUN50I_H6_H 8#define _SUNXI_CPU_SUN50I_H6_H 9 10#define SUNXI_SRAMC_BASE 0x03000000 11#define SUNXI_CCM_BASE 0x03001000 12/* SID address space starts at 0x03006000, but e-fuse is at offset 0x200 */ 13#define SUNXI_SIDC_BASE 0x03006000 14#define SUNXI_SID_BASE 0x03006200 15#define SUNXI_TIMER_BASE 0x03009000 16 17#define SUNXI_GIC400_BASE 0x03020000 18 19#ifdef CONFIG_MACH_SUN50I_H6 20#define SUNXI_DRAM_COM_BASE 0x04002000 21#define SUNXI_DRAM_CTL0_BASE 0x04003000 22#define SUNXI_DRAM_PHY0_BASE 0x04005000 23#endif 24#define SUNXI_NFC_BASE 0x04011000 25#define SUNXI_MMC0_BASE 0x04020000 26#define SUNXI_MMC1_BASE 0x04021000 27#define SUNXI_MMC2_BASE 0x04022000 28#ifdef CONFIG_MACH_SUN50I_H616 29#define SUNXI_DRAM_COM_BASE 0x047FA000 30#define SUNXI_DRAM_CTL0_BASE 0x047FB000 31#define SUNXI_DRAM_PHY0_BASE 0x04800000 32#endif 33 34#define SUNXI_TWI0_BASE 0x05002000 35#define SUNXI_TWI1_BASE 0x05002400 36#define SUNXI_TWI2_BASE 0x05002800 37#define SUNXI_TWI3_BASE 0x05002C00 38 39#define SUNXI_HDMI_BASE 0x06000000 40 41#define SUNXI_RTC_BASE 0x07000000 42#define SUNXI_R_CPUCFG_BASE 0x07000400 43#define SUNXI_PRCM_BASE 0x07010000 44#define SUNXI_R_WDOG_BASE 0x07020400 45#define SUNXI_R_TWI_BASE 0x07081400 46 47#ifndef __ASSEMBLY__ 48void sunxi_board_init(void); 49void sunxi_reset(void); 50int sunxi_get_sid(unsigned int *sid); 51#endif 52 53#endif /* _SUNXI_CPU_SUN9I_H */ 54