1/* 2 * Copyright 2014, General Dynamics C4 Systems 3 * 4 * SPDX-License-Identifier: GPL-2.0-only 5 */ 6 7#pragma once 8 9/* This file contains useful macros for assembly code. */ 10 11#ifdef __ASSEMBLER__ 12 13#define PSR_F_BIT 0x00000040 14#define PSR_I_BIT 0x00000080 15#define PSR_A_BIT 0x00000100 16#define PSR_D_BIT 0x00000200 17 18#define PSR_MODE_EL0t 0x00000000 19#define PSR_MODE_EL1t 0x00000004 20#define PSR_MODE_EL1h 0x00000005 21#define PSR_MODE_EL2t 0x00000008 22#define PSR_MODE_EL2h 0x00000009 23#define PSR_MODE_SVC_32 0x00000013 24 25#define TCR_T0SZ(x) ((64 - (x))) 26#define TCR_T1SZ(x) ((64 - (x)) << 16) 27#define TCR_TxSZ(x) (TCR_T0SZ(x) | TCR_T1SZ(x)) 28 29#define TCR_IRGN0_WBWC (1 << 8) 30#define TCR_IRGN_NC ((0 << 8) | (0 << 24)) 31#define TCR_IRGN_WBWA ((1 << 8) | (1 << 24)) 32#define TCR_IRGN_WT ((2 << 8) | (2 << 24)) 33#define TCR_IRGN_WBnWA ((3 << 8) | (3 << 24)) 34#define TCR_IRGN_MASK ((3 << 8) | (3 << 24)) 35 36#define TCR_ORGN0_WBWC (1 << 10) 37#define TCR_ORGN_NC ((0 << 10) | (0 << 26)) 38#define TCR_ORGN_WBWA ((1 << 10) | (1 << 26)) 39#define TCR_ORGN_WT ((2 << 10) | (2 << 26)) 40#define TCR_ORGN_WBnWA ((3 << 10) | (3 << 26)) 41#define TCR_ORGN_MASK ((3 << 10) | (3 << 26)) 42 43#define TCR_SH0_ISH (3 << 12) 44#define TCR_SHARED ((3 << 12) | (3 << 28)) 45 46#define TCR_TG0_4K (0 << 14) 47#define TCR_TG0_64K (1 << 14) 48#define TCR_TG1_4K (2 << 30) 49#define TCR_TG1_64K (3 << 30) 50 51#define TCR_PS_4G (0 << 16) 52#define TCR_PS_64G (1 << 16) 53#define TCR_PS_1T (2 << 16) 54#define TCR_PS_4T (3 << 16) 55#define TCR_PS_16T (4 << 16) 56#define TCR_PS_256T (5 << 16) 57 58/* bits are reserved as 1 */ 59#define TCR_EL2_RES1 ((1 << 23) | (1 << 31)) 60#define TCR_ASID16 (1 << 36) 61 62#define MT_DEVICE_nGnRnE 0 63#define MT_DEVICE_nGnRE 1 64#define MT_DEVICE_GRE 2 65#define MT_NORMAL_NC 3 66#define MT_NORMAL 4 67#define MAIR(_attr, _mt) ((_attr) << ((_mt) * 8)) 68 69.macro enable_mmu sctlr tmp 70 mrs \tmp, \sctlr 71 orr \tmp, \tmp, #(1 << 0) 72 orr \tmp, \tmp, #(1 << 2) 73 orr \tmp, \tmp, #(1 << 12) 74 msr \sctlr, \tmp 75 isb 76.endm 77 78.macro disable_mmu sctlr tmp 79 mrs \tmp, \sctlr 80 bic \tmp, \tmp, #(1 << 0) 81 bic \tmp, \tmp, #(1 << 2) 82 bic \tmp, \tmp, #(1 << 12) 83 msr \sctlr, \tmp 84 isb 85.endm 86 87.macro disable_id_cache sctlr tmp 88 mrs \tmp, \sctlr 89 bic \tmp, \tmp, #(1 << 2) 90 bic \tmp, \tmp, #(1 << 12) 91 msr \sctlr, \tmp 92 isb 93.endm 94 95.macro dcache op 96 dsb sy 97 mrs x0, clidr_el1 98 and x3, x0, #0x7000000 99 lsr x3, x3, #23 100 101 cbz x3, finished_\op 102 mov x10, #0 103 104loop1_\op: 105 add x2, x10, x10, lsr #1 106 lsr x1, x0, x2 107 and x1, x1, #7 108 cmp x1, #2 109 b.lt skip_\op 110 111 msr csselr_el1, x10 112 isb 113 114 mrs x1, ccsidr_el1 115 and x2, x1, #7 116 add x2, x2, #4 117 mov x4, #0x3ff 118 and x4, x4, x1, lsr #3 119 clz w5, w4 120 mov x7, #0x7fff 121 and x7, x7, x1, lsr #13 122 123loop2_\op: 124 mov x9, x4 125 126loop3_\op: 127 lsl x6, x9, x5 128 orr x11, x10, x6 129 lsl x6, x7, x2 130 orr x11, x11, x6 131 dc \op, x11 132 subs x9, x9, #1 133 b.ge loop3_\op 134 subs x7, x7, #1 135 b.ge loop2_\op 136 137skip_\op: 138 add x10, x10, #2 139 cmp x3, x10 140 b.gt loop1_\op 141 142finished_\op: 143 mov x10, #0 144 msr csselr_el1, x10 145 dsb sy 146 isb 147.endm 148 149#else /* !__ASSEMBLER__ */ 150#warning "Including assembly-specific header in C code" 151#endif 152 153