1/* 2 * \file radeon_drv.c 3 * ATI Radeon driver 4 * 5 * \author Gareth Hughes <gareth@valinux.com> 6 */ 7 8/* 9 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 10 * All Rights Reserved. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a 13 * copy of this software and associated documentation files (the "Software"), 14 * to deal in the Software without restriction, including without limitation 15 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 16 * and/or sell copies of the Software, and to permit persons to whom the 17 * Software is furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice (including the next 20 * paragraph) shall be included in all copies or substantial portions of the 21 * Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 29 * OTHER DEALINGS IN THE SOFTWARE. 30 */ 31 32 33#include <linux/compat.h> 34#include <linux/module.h> 35#include <linux/pm_runtime.h> 36#include <linux/vga_switcheroo.h> 37#include <linux/mmu_notifier.h> 38#include <linux/pci.h> 39 40#include <drm/drm_aperture.h> 41#include <drm/drm_drv.h> 42#include <drm/drm_file.h> 43#include <drm/drm_gem.h> 44#include <drm/drm_ioctl.h> 45#include <drm/drm_pciids.h> 46#include <drm/drm_probe_helper.h> 47#include <drm/drm_vblank.h> 48#include <drm/radeon_drm.h> 49 50#include "radeon_drv.h" 51#include "radeon.h" 52#include "radeon_kms.h" 53#include "radeon_ttm.h" 54#include "radeon_device.h" 55#include "radeon_prime.h" 56 57/* 58 * KMS wrapper. 59 * - 2.0.0 - initial interface 60 * - 2.1.0 - add square tiling interface 61 * - 2.2.0 - add r6xx/r7xx const buffer support 62 * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs 63 * - 2.4.0 - add crtc id query 64 * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen 65 * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500) 66 * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs 67 * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query 68 * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query 69 * 2.10.0 - fusion 2D tiling 70 * 2.11.0 - backend map, initial compute support for the CS checker 71 * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS 72 * 2.13.0 - virtual memory support, streamout 73 * 2.14.0 - add evergreen tiling informations 74 * 2.15.0 - add max_pipes query 75 * 2.16.0 - fix evergreen 2D tiled surface calculation 76 * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx 77 * 2.18.0 - r600-eg: allow "invalid" DB formats 78 * 2.19.0 - r600-eg: MSAA textures 79 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query 80 * 2.21.0 - r600-r700: FMASK and CMASK 81 * 2.22.0 - r600 only: RESOLVE_BOX allowed 82 * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880 83 * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures 84 * 2.25.0 - eg+: new info request for num SE and num SH 85 * 2.26.0 - r600-eg: fix htile size computation 86 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA 87 * 2.28.0 - r600-eg: Add MEM_WRITE packet support 88 * 2.29.0 - R500 FP16 color clear registers 89 * 2.30.0 - fix for FMASK texturing 90 * 2.31.0 - Add fastfb support for rs690 91 * 2.32.0 - new info request for rings working 92 * 2.33.0 - Add SI tiling mode array query 93 * 2.34.0 - Add CIK tiling mode array query 94 * 2.35.0 - Add CIK macrotile mode array query 95 * 2.36.0 - Fix CIK DCE tiling setup 96 * 2.37.0 - allow GS ring setup on r6xx/r7xx 97 * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN), 98 * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG 99 * 2.39.0 - Add INFO query for number of active CUs 100 * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting 101 * CS to GPU on >= r600 102 * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support 103 * 2.42.0 - Add VCE/VUI (Video Usability Information) support 104 * 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER 105 * 2.44.0 - SET_APPEND_CNT packet3 support 106 * 2.45.0 - Allow setting shader registers using DMA/COPY packet3 on SI 107 * 2.46.0 - Add PFP_SYNC_ME support on evergreen 108 * 2.47.0 - Add UVD_NO_OP register support 109 * 2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI 110 * 2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct vram_size/visible values 111 * 2.50.0 - Allows unaligned shader loads on CIK. (needed by OpenGL) 112 */ 113#define KMS_DRIVER_MAJOR 2 114#define KMS_DRIVER_MINOR 50 115#define KMS_DRIVER_PATCHLEVEL 0 116 117int radeon_no_wb; 118int radeon_modeset = -1; 119int radeon_dynclks = -1; 120int radeon_r4xx_atom; 121int radeon_agpmode = -1; 122int radeon_vram_limit; 123int radeon_gart_size = -1; /* auto */ 124int radeon_benchmarking; 125int radeon_testing; 126int radeon_connector_table; 127int radeon_tv = 1; 128int radeon_audio = -1; 129int radeon_disp_priority; 130int radeon_hw_i2c; 131int radeon_pcie_gen2 = -1; 132int radeon_msi = -1; 133int radeon_lockup_timeout = 10000; 134int radeon_fastfb; 135int radeon_dpm = -1; 136int radeon_aspm = -1; 137int radeon_runtime_pm = -1; 138int radeon_hard_reset; 139int radeon_vm_size = 8; 140int radeon_vm_block_size = -1; 141int radeon_deep_color; 142int radeon_use_pflipirq = 2; 143int radeon_bapm = -1; 144int radeon_backlight = -1; 145int radeon_auxch = -1; 146int radeon_uvd = 1; 147int radeon_vce = 1; 148 149MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers"); 150module_param_named(no_wb, radeon_no_wb, int, 0444); 151 152MODULE_PARM_DESC(modeset, "Disable/Enable modesetting"); 153module_param_named(modeset, radeon_modeset, int, 0400); 154 155MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks"); 156module_param_named(dynclks, radeon_dynclks, int, 0444); 157 158MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx"); 159module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444); 160 161MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 162module_param_named(vramlimit, radeon_vram_limit, int, 0600); 163 164MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)"); 165module_param_named(agpmode, radeon_agpmode, int, 0444); 166 167MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)"); 168module_param_named(gartsize, radeon_gart_size, int, 0600); 169 170MODULE_PARM_DESC(benchmark, "Run benchmark"); 171module_param_named(benchmark, radeon_benchmarking, int, 0444); 172 173MODULE_PARM_DESC(test, "Run tests"); 174module_param_named(test, radeon_testing, int, 0444); 175 176MODULE_PARM_DESC(connector_table, "Force connector table"); 177module_param_named(connector_table, radeon_connector_table, int, 0444); 178 179MODULE_PARM_DESC(tv, "TV enable (0 = disable)"); 180module_param_named(tv, radeon_tv, int, 0444); 181 182MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 183module_param_named(audio, radeon_audio, int, 0444); 184 185MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 186module_param_named(disp_priority, radeon_disp_priority, int, 0444); 187 188MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 189module_param_named(hw_i2c, radeon_hw_i2c, int, 0444); 190 191MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 192module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444); 193 194MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 195module_param_named(msi, radeon_msi, int, 0444); 196 197MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)"); 198module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444); 199 200MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)"); 201module_param_named(fastfb, radeon_fastfb, int, 0444); 202 203MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 204module_param_named(dpm, radeon_dpm, int, 0444); 205 206MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 207module_param_named(aspm, radeon_aspm, int, 0444); 208 209MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 210module_param_named(runpm, radeon_runtime_pm, int, 0444); 211 212MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))"); 213module_param_named(hard_reset, radeon_hard_reset, int, 0444); 214 215MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)"); 216module_param_named(vm_size, radeon_vm_size, int, 0444); 217 218MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 219module_param_named(vm_block_size, radeon_vm_block_size, int, 0444); 220 221MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 222module_param_named(deep_color, radeon_deep_color, int, 0444); 223 224MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))"); 225module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444); 226 227MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 228module_param_named(bapm, radeon_bapm, int, 0444); 229 230MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)"); 231module_param_named(backlight, radeon_backlight, int, 0444); 232 233MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)"); 234module_param_named(auxch, radeon_auxch, int, 0444); 235 236MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)"); 237module_param_named(uvd, radeon_uvd, int, 0444); 238 239MODULE_PARM_DESC(vce, "vce enable/disable vce support (1 = enable, 0 = disable)"); 240module_param_named(vce, radeon_vce, int, 0444); 241 242int radeon_si_support = 1; 243MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 244module_param_named(si_support, radeon_si_support, int, 0444); 245 246int radeon_cik_support = 1; 247MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 248module_param_named(cik_support, radeon_cik_support, int, 0444); 249 250static const struct pci_device_id pciidlist[] = { 251 radeon_PCI_IDS 252}; 253 254MODULE_DEVICE_TABLE(pci, pciidlist); 255 256static const struct drm_driver kms_driver; 257 258#ifdef __linux__ 259static int radeon_pci_probe(struct pci_dev *pdev, 260 const struct pci_device_id *ent) 261{ 262 unsigned long flags = 0; 263 struct drm_device *dev; 264 int ret; 265 266 if (!ent) 267 return -ENODEV; /* Avoid NULL-ptr deref in drm_get_pci_dev */ 268 269 flags = ent->driver_data; 270 271 if (!radeon_si_support) { 272 switch (flags & RADEON_FAMILY_MASK) { 273 case CHIP_TAHITI: 274 case CHIP_PITCAIRN: 275 case CHIP_VERDE: 276 case CHIP_OLAND: 277 case CHIP_HAINAN: 278 dev_info(&pdev->dev, 279 "SI support disabled by module param\n"); 280 return -ENODEV; 281 } 282 } 283 if (!radeon_cik_support) { 284 switch (flags & RADEON_FAMILY_MASK) { 285 case CHIP_KAVERI: 286 case CHIP_BONAIRE: 287 case CHIP_HAWAII: 288 case CHIP_KABINI: 289 case CHIP_MULLINS: 290 dev_info(&pdev->dev, 291 "CIK support disabled by module param\n"); 292 return -ENODEV; 293 } 294 } 295 296 if (vga_switcheroo_client_probe_defer(pdev)) 297 return -EPROBE_DEFER; 298 299 /* Get rid of things like offb */ 300 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &kms_driver); 301 if (ret) 302 return ret; 303 304 dev = drm_dev_alloc(&kms_driver, &pdev->dev); 305 if (IS_ERR(dev)) 306 return PTR_ERR(dev); 307 308 ret = pci_enable_device(pdev); 309 if (ret) 310 goto err_free; 311 312 pci_set_drvdata(pdev, dev); 313 314 ret = drm_dev_register(dev, ent->driver_data); 315 if (ret) 316 goto err_agp; 317 318 radeon_fbdev_setup(dev->dev_private); 319 320 return 0; 321 322err_agp: 323 pci_disable_device(pdev); 324err_free: 325 drm_dev_put(dev); 326 return ret; 327} 328 329static void 330radeon_pci_remove(struct pci_dev *pdev) 331{ 332 struct drm_device *dev = pci_get_drvdata(pdev); 333 334 drm_put_dev(dev); 335} 336 337static void 338radeon_pci_shutdown(struct pci_dev *pdev) 339{ 340 /* if we are running in a VM, make sure the device 341 * torn down properly on reboot/shutdown 342 */ 343 if (radeon_device_is_virtual()) 344 radeon_pci_remove(pdev); 345 346#if defined(CONFIG_PPC64) || defined(CONFIG_MACH_LOONGSON64) 347 /* 348 * Some adapters need to be suspended before a 349 * shutdown occurs in order to prevent an error 350 * during kexec, shutdown or reboot. 351 * Make this power and Loongson specific because 352 * it breaks some other boards. 353 */ 354 radeon_suspend_kms(pci_get_drvdata(pdev), true, true, false); 355#endif 356} 357 358static int radeon_pmops_suspend(struct device *dev) 359{ 360 struct drm_device *drm_dev = dev_get_drvdata(dev); 361 362 return radeon_suspend_kms(drm_dev, true, true, false); 363} 364 365static int radeon_pmops_resume(struct device *dev) 366{ 367 struct drm_device *drm_dev = dev_get_drvdata(dev); 368 369 /* GPU comes up enabled by the bios on resume */ 370 if (radeon_is_px(drm_dev)) { 371 pm_runtime_disable(dev); 372 pm_runtime_set_active(dev); 373 pm_runtime_enable(dev); 374 } 375 376 return radeon_resume_kms(drm_dev, true, true); 377} 378 379static int radeon_pmops_freeze(struct device *dev) 380{ 381 struct drm_device *drm_dev = dev_get_drvdata(dev); 382 383 return radeon_suspend_kms(drm_dev, false, true, true); 384} 385 386static int radeon_pmops_thaw(struct device *dev) 387{ 388 struct drm_device *drm_dev = dev_get_drvdata(dev); 389 390 return radeon_resume_kms(drm_dev, false, true); 391} 392 393static int radeon_pmops_runtime_suspend(struct device *dev) 394{ 395 struct pci_dev *pdev = to_pci_dev(dev); 396 struct drm_device *drm_dev = pci_get_drvdata(pdev); 397 398 if (!radeon_is_px(drm_dev)) { 399 pm_runtime_forbid(dev); 400 return -EBUSY; 401 } 402 403 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 404 drm_kms_helper_poll_disable(drm_dev); 405 406 radeon_suspend_kms(drm_dev, false, false, false); 407 pci_save_state(pdev); 408 pci_disable_device(pdev); 409 pci_ignore_hotplug(pdev); 410 if (radeon_is_atpx_hybrid()) 411 pci_set_power_state(pdev, PCI_D3cold); 412 else if (!radeon_has_atpx_dgpu_power_cntl()) 413 pci_set_power_state(pdev, PCI_D3hot); 414 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 415 416 return 0; 417} 418 419static int radeon_pmops_runtime_resume(struct device *dev) 420{ 421 struct pci_dev *pdev = to_pci_dev(dev); 422 struct drm_device *drm_dev = pci_get_drvdata(pdev); 423 int ret; 424 425 if (!radeon_is_px(drm_dev)) 426 return -EINVAL; 427 428 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 429 430 if (radeon_is_atpx_hybrid() || 431 !radeon_has_atpx_dgpu_power_cntl()) 432 pci_set_power_state(pdev, PCI_D0); 433 pci_restore_state(pdev); 434 ret = pci_enable_device(pdev); 435 if (ret) 436 return ret; 437 pci_set_master(pdev); 438 439 ret = radeon_resume_kms(drm_dev, false, false); 440 drm_kms_helper_poll_enable(drm_dev); 441 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 442 return 0; 443} 444 445static int radeon_pmops_runtime_idle(struct device *dev) 446{ 447 struct drm_device *drm_dev = dev_get_drvdata(dev); 448 struct drm_crtc *crtc; 449 450 if (!radeon_is_px(drm_dev)) { 451 pm_runtime_forbid(dev); 452 return -EBUSY; 453 } 454 455 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 456 if (crtc->enabled) { 457 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 458 return -EBUSY; 459 } 460 } 461 462 pm_runtime_mark_last_busy(dev); 463 pm_runtime_autosuspend(dev); 464 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 465 return 1; 466} 467 468long radeon_drm_ioctl(struct file *filp, 469 unsigned int cmd, unsigned long arg) 470{ 471 struct drm_file *file_priv = filp->private_data; 472 struct drm_device *dev; 473 long ret; 474 475 dev = file_priv->minor->dev; 476 ret = pm_runtime_get_sync(dev->dev); 477 if (ret < 0) { 478 pm_runtime_put_autosuspend(dev->dev); 479 return ret; 480 } 481 482 ret = drm_ioctl(filp, cmd, arg); 483 484 pm_runtime_mark_last_busy(dev->dev); 485 pm_runtime_put_autosuspend(dev->dev); 486 return ret; 487} 488 489#ifdef CONFIG_COMPAT 490static long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) 491{ 492 unsigned int nr = DRM_IOCTL_NR(cmd); 493 494 if (nr < DRM_COMMAND_BASE) 495 return drm_compat_ioctl(filp, cmd, arg); 496 497 return radeon_drm_ioctl(filp, cmd, arg); 498} 499#endif 500 501static const struct dev_pm_ops radeon_pm_ops = { 502 .suspend = radeon_pmops_suspend, 503 .resume = radeon_pmops_resume, 504 .freeze = radeon_pmops_freeze, 505 .thaw = radeon_pmops_thaw, 506 .poweroff = radeon_pmops_freeze, 507 .restore = radeon_pmops_resume, 508 .runtime_suspend = radeon_pmops_runtime_suspend, 509 .runtime_resume = radeon_pmops_runtime_resume, 510 .runtime_idle = radeon_pmops_runtime_idle, 511}; 512 513static const struct file_operations radeon_driver_kms_fops = { 514 .owner = THIS_MODULE, 515 .open = drm_open, 516 .release = drm_release, 517 .unlocked_ioctl = radeon_drm_ioctl, 518 .mmap = drm_gem_mmap, 519 .poll = drm_poll, 520 .read = drm_read, 521#ifdef CONFIG_COMPAT 522 .compat_ioctl = radeon_kms_compat_ioctl, 523#endif 524}; 525 526#endif /* __linux__ */ 527 528static const struct drm_ioctl_desc radeon_ioctls_kms[] = { 529 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 530 DRM_IOCTL_DEF_DRV(RADEON_CP_START, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 531 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 532 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 533 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, drm_invalid_op, DRM_AUTH), 534 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, drm_invalid_op, DRM_AUTH), 535 DRM_IOCTL_DEF_DRV(RADEON_RESET, drm_invalid_op, DRM_AUTH), 536 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, drm_invalid_op, DRM_AUTH), 537 DRM_IOCTL_DEF_DRV(RADEON_SWAP, drm_invalid_op, DRM_AUTH), 538 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, drm_invalid_op, DRM_AUTH), 539 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, drm_invalid_op, DRM_AUTH), 540 DRM_IOCTL_DEF_DRV(RADEON_INDICES, drm_invalid_op, DRM_AUTH), 541 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, drm_invalid_op, DRM_AUTH), 542 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, drm_invalid_op, DRM_AUTH), 543 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 544 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, drm_invalid_op, DRM_AUTH), 545 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, drm_invalid_op, DRM_AUTH), 546 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, drm_invalid_op, DRM_AUTH), 547 DRM_IOCTL_DEF_DRV(RADEON_FLIP, drm_invalid_op, DRM_AUTH), 548 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, drm_invalid_op, DRM_AUTH), 549 DRM_IOCTL_DEF_DRV(RADEON_FREE, drm_invalid_op, DRM_AUTH), 550 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 551 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, drm_invalid_op, DRM_AUTH), 552 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, drm_invalid_op, DRM_AUTH), 553 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, drm_invalid_op, DRM_AUTH), 554 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, drm_invalid_op, DRM_AUTH), 555 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, drm_invalid_op, DRM_AUTH), 556 /* KMS */ 557 DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 558 DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 559 DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 560 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 561 DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 562 DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 563 DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 564 DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 565 DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 566 DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 567 DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 568 DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 569 DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 570}; 571 572static const struct drm_driver kms_driver = { 573 .driver_features = 574 DRIVER_GEM | DRIVER_RENDER | DRIVER_MODESET, 575#ifdef notyet 576 .load = radeon_driver_load_kms, 577#endif 578 .open = radeon_driver_open_kms, 579#ifdef __OpenBSD__ 580 .mmap = drm_gem_mmap, 581#endif 582 .postclose = radeon_driver_postclose_kms, 583#ifdef notyet 584 .unload = radeon_driver_unload_kms, 585#endif 586 .ioctls = radeon_ioctls_kms, 587 .num_ioctls = ARRAY_SIZE(radeon_ioctls_kms), 588#ifdef __OpenBSD__ 589 .gem_size = sizeof(struct radeon_bo), 590#endif 591 .dumb_create = radeon_mode_dumb_create, 592 .dumb_map_offset = radeon_mode_dumb_mmap, 593#ifdef __linux__ 594 .fops = &radeon_driver_kms_fops, 595#endif 596 597#ifdef notyet 598 .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table, 599#endif 600 601 .name = DRIVER_NAME, 602 .desc = DRIVER_DESC, 603 .date = DRIVER_DATE, 604 .major = KMS_DRIVER_MAJOR, 605 .minor = KMS_DRIVER_MINOR, 606 .patchlevel = KMS_DRIVER_PATCHLEVEL, 607}; 608 609#ifdef __linux__ 610static struct pci_driver radeon_kms_pci_driver = { 611 .name = DRIVER_NAME, 612 .id_table = pciidlist, 613 .probe = radeon_pci_probe, 614 .remove = radeon_pci_remove, 615 .shutdown = radeon_pci_shutdown, 616 .driver.pm = &radeon_pm_ops, 617}; 618#endif 619 620#ifdef notyet 621static int __init radeon_module_init(void) 622{ 623 if (drm_firmware_drivers_only() && radeon_modeset == -1) 624 radeon_modeset = 0; 625 626 if (radeon_modeset == 0) 627 return -EINVAL; 628 629 DRM_INFO("radeon kernel modesetting enabled.\n"); 630 radeon_register_atpx_handler(); 631 632 return pci_register_driver(&radeon_kms_pci_driver); 633} 634 635static void __exit radeon_module_exit(void) 636{ 637 pci_unregister_driver(&radeon_kms_pci_driver); 638 radeon_unregister_atpx_handler(); 639 mmu_notifier_synchronize(); 640} 641#endif /* notyet */ 642 643module_init(radeon_module_init); 644module_exit(radeon_module_exit); 645 646MODULE_AUTHOR(DRIVER_AUTHOR); 647MODULE_DESCRIPTION(DRIVER_DESC); 648MODULE_LICENSE("GPL and additional rights"); 649 650#if defined(CONFIG_VGA_SWITCHEROO) 651bool radeon_has_atpx(void); 652#else 653static inline bool radeon_has_atpx(void) { return false; } 654#endif 655 656#include <drm/drm_drv.h> 657#include <drm/drm_fb_helper.h> 658#include "vga.h" 659 660#if NVGA > 0 661#include <dev/ic/mc6845reg.h> 662#include <dev/ic/pcdisplayvar.h> 663#include <dev/ic/vgareg.h> 664#include <dev/ic/vgavar.h> 665 666extern int vga_console_attached; 667#endif 668 669#ifdef __amd64__ 670#include "efifb.h" 671#include <machine/biosvar.h> 672#endif 673 674#if NEFIFB > 0 675#include <machine/efifbvar.h> 676#endif 677 678int radeondrm_probe(struct device *, void *, void *); 679void radeondrm_attach_kms(struct device *, struct device *, void *); 680int radeondrm_detach_kms(struct device *, int); 681int radeondrm_activate_kms(struct device *, int); 682void radeondrm_attachhook(struct device *); 683int radeondrm_forcedetach(struct radeon_device *); 684 685bool radeon_msi_ok(struct radeon_device *); 686irqreturn_t radeon_driver_irq_handler_kms(void *); 687 688/* 689 * set if the mountroot hook has a fatal error 690 * such as not being able to find the firmware on newer cards 691 */ 692int radeon_fatal_error; 693 694const struct cfattach radeondrm_ca = { 695 sizeof (struct radeon_device), radeondrm_probe, radeondrm_attach_kms, 696 radeondrm_detach_kms, radeondrm_activate_kms 697}; 698 699struct cfdriver radeondrm_cd = { 700 NULL, "radeondrm", DV_DULL 701}; 702 703int 704radeondrm_probe(struct device *parent, void *match, void *aux) 705{ 706 if (radeon_fatal_error) 707 return 0; 708 if (drm_pciprobe(aux, pciidlist)) 709 return 20; 710 return 0; 711} 712 713int 714radeondrm_detach_kms(struct device *self, int flags) 715{ 716 struct radeon_device *rdev = (struct radeon_device *)self; 717 718 if (rdev == NULL) 719 return 0; 720 721 pci_intr_disestablish(rdev->pc, rdev->irqh); 722 723#ifdef notyet 724 pm_runtime_get_sync(dev->dev); 725 726 radeon_kfd_device_fini(rdev); 727#endif 728 729 radeon_acpi_fini(rdev); 730 731 radeon_modeset_fini(rdev); 732 radeon_device_fini(rdev); 733 734 if (rdev->ddev != NULL) { 735 config_detach(rdev->ddev->dev, flags); 736 rdev->ddev = NULL; 737 } 738 739 return 0; 740} 741 742void radeondrm_burner(void *, u_int, u_int); 743int radeondrm_wsioctl(void *, u_long, caddr_t, int, struct proc *); 744paddr_t radeondrm_wsmmap(void *, off_t, int); 745int radeondrm_alloc_screen(void *, const struct wsscreen_descr *, 746 void **, int *, int *, uint32_t *); 747void radeondrm_free_screen(void *, void *); 748int radeondrm_show_screen(void *, void *, int, 749 void (*)(void *, int, int), void *); 750void radeondrm_doswitch(void *); 751void radeondrm_enter_ddb(void *, void *); 752#ifdef __sparc64__ 753void radeondrm_setcolor(void *, u_int, u_int8_t, u_int8_t, u_int8_t); 754#endif 755void radeondrm_setpal(struct radeon_device *, struct rasops_info *); 756 757struct wsscreen_descr radeondrm_stdscreen = { 758 "std", 759 0, 0, 760 0, 761 0, 0, 762 WSSCREEN_UNDERLINE | WSSCREEN_HILIT | 763 WSSCREEN_REVERSE | WSSCREEN_WSCOLORS 764}; 765 766const struct wsscreen_descr *radeondrm_scrlist[] = { 767 &radeondrm_stdscreen, 768}; 769 770struct wsscreen_list radeondrm_screenlist = { 771 nitems(radeondrm_scrlist), radeondrm_scrlist 772}; 773 774struct wsdisplay_accessops radeondrm_accessops = { 775 .ioctl = radeondrm_wsioctl, 776 .mmap = radeondrm_wsmmap, 777 .alloc_screen = radeondrm_alloc_screen, 778 .free_screen = radeondrm_free_screen, 779 .show_screen = radeondrm_show_screen, 780 .enter_ddb = radeondrm_enter_ddb, 781 .getchar = rasops_getchar, 782 .load_font = rasops_load_font, 783 .list_font = rasops_list_font, 784 .scrollback = rasops_scrollback, 785 .burn_screen = radeondrm_burner 786}; 787 788int 789radeondrm_wsioctl(void *v, u_long cmd, caddr_t data, int flag, struct proc *p) 790{ 791 struct rasops_info *ri = v; 792 struct wsdisplay_fbinfo *wdf; 793 struct wsdisplay_param *dp = (struct wsdisplay_param *)data; 794 795 switch (cmd) { 796 case WSDISPLAYIO_GTYPE: 797 *(u_int *)data = WSDISPLAY_TYPE_RADEONDRM; 798 return 0; 799 case WSDISPLAYIO_GINFO: 800 wdf = (struct wsdisplay_fbinfo *)data; 801 wdf->width = ri->ri_width; 802 wdf->height = ri->ri_height; 803 wdf->depth = ri->ri_depth; 804 wdf->stride = ri->ri_stride; 805 wdf->offset = 0; 806 wdf->cmsize = 0; 807 return 0; 808 case WSDISPLAYIO_GETPARAM: 809 if (ws_get_param == NULL) 810 return 0; 811 return ws_get_param(dp); 812 case WSDISPLAYIO_SETPARAM: 813 if (ws_set_param == NULL) 814 return 0; 815 return ws_set_param(dp); 816 case WSDISPLAYIO_SVIDEO: 817 case WSDISPLAYIO_GVIDEO: 818 return 0; 819 default: 820 return -1; 821 } 822} 823 824paddr_t 825radeondrm_wsmmap(void *v, off_t off, int prot) 826{ 827 return (-1); 828} 829 830int 831radeondrm_alloc_screen(void *v, const struct wsscreen_descr *type, 832 void **cookiep, int *curxp, int *curyp, uint32_t *attrp) 833{ 834 return rasops_alloc_screen(v, cookiep, curxp, curyp, attrp); 835} 836 837void 838radeondrm_free_screen(void *v, void *cookie) 839{ 840 return rasops_free_screen(v, cookie); 841} 842 843int 844radeondrm_show_screen(void *v, void *cookie, int waitok, 845 void (*cb)(void *, int, int), void *cbarg) 846{ 847 struct rasops_info *ri = v; 848 struct radeon_device *rdev = ri->ri_hw; 849 850 if (cookie == ri->ri_active) 851 return (0); 852 853 rdev->switchcb = cb; 854 rdev->switchcbarg = cbarg; 855 rdev->switchcookie = cookie; 856 if (cb) { 857 task_add(systq, &rdev->switchtask); 858 return (EAGAIN); 859 } 860 861 radeondrm_doswitch(v); 862 863 return (0); 864} 865 866void 867radeondrm_doswitch(void *v) 868{ 869 struct rasops_info *ri = v; 870 struct radeon_device *rdev = ri->ri_hw; 871 872 rasops_show_screen(ri, rdev->switchcookie, 0, NULL, NULL); 873#ifdef __sparc64__ 874 fbwscons_setcolormap(&rdev->sf, radeondrm_setcolor); 875#else 876 radeondrm_setpal(rdev, ri); 877#endif 878 drm_fb_helper_restore_fbdev_mode_unlocked(rdev->ddev->fb_helper); 879 880 if (rdev->switchcb) 881 (rdev->switchcb)(rdev->switchcbarg, 0, 0); 882} 883 884void 885radeondrm_enter_ddb(void *v, void *cookie) 886{ 887 struct rasops_info *ri = v; 888 struct radeon_device *rdev = ri->ri_hw; 889 struct drm_fb_helper *fb_helper = rdev->ddev->fb_helper; 890 891 if (cookie == ri->ri_active) 892 return; 893 894 rasops_show_screen(ri, cookie, 0, NULL, NULL); 895 drm_fb_helper_debug_enter(fb_helper->info); 896} 897 898#ifdef __sparc64__ 899void 900radeondrm_setcolor(void *v, u_int index, u_int8_t r, u_int8_t g, u_int8_t b) 901{ 902 struct sunfb *sf = v; 903 struct radeon_device *rdev = sf->sf_ro.ri_hw; 904 905 /* see legacy_crtc_load_lut() */ 906 if (rdev->family < CHIP_RS600) { 907 WREG8(RADEON_PALETTE_INDEX, index); 908 WREG32(RADEON_PALETTE_30_DATA, 909 (r << 22) | (g << 12) | (b << 2)); 910 } else { 911 printf("%s: setcolor family %d not handled\n", 912 rdev->self.dv_xname, rdev->family); 913 } 914} 915#endif 916 917void 918radeondrm_setpal(struct radeon_device *rdev, struct rasops_info *ri) 919{ 920 struct drm_device *dev = rdev->ddev; 921 struct drm_crtc *crtc; 922 uint16_t *r_base, *g_base, *b_base; 923 int i, index, ret = 0; 924 const u_char *p; 925 926 if (ri->ri_depth != 8) 927 return; 928 929 for (i = 0; i < rdev->num_crtc; i++) { 930 struct drm_modeset_acquire_ctx ctx; 931 crtc = &rdev->mode_info.crtcs[i]->base; 932 933 r_base = crtc->gamma_store; 934 g_base = r_base + crtc->gamma_size; 935 b_base = g_base + crtc->gamma_size; 936 937 DRM_MODESET_LOCK_ALL_BEGIN(dev, ctx, 0, ret); 938 939 p = rasops_cmap; 940 for (index = 0; index < 256; index++) { 941 r_base[index] = *p++ << 8; 942 g_base[index] = *p++ << 8; 943 b_base[index] = *p++ << 8; 944 } 945 946 crtc->funcs->gamma_set(crtc, NULL, NULL, NULL, 0, NULL); 947 948 DRM_MODESET_LOCK_ALL_END(dev, ctx, ret); 949 } 950} 951 952void 953radeondrm_attach_kms(struct device *parent, struct device *self, void *aux) 954{ 955 struct radeon_device *rdev = (struct radeon_device *)self; 956 struct drm_device *dev; 957 struct pci_attach_args *pa = aux; 958 const struct pci_device_id *id_entry; 959 int is_agp; 960 pcireg_t type; 961 int i; 962 uint8_t rmmio_bar; 963 paddr_t fb_aper; 964 pcireg_t addr, mask; 965 int s; 966 967#if defined(__sparc64__) || defined(__macppc__) 968 extern int fbnode; 969#endif 970 971 id_entry = drm_find_description(PCI_VENDOR(pa->pa_id), 972 PCI_PRODUCT(pa->pa_id), pciidlist); 973 rdev->flags = id_entry->driver_data; 974 rdev->family = rdev->flags & RADEON_FAMILY_MASK; 975 rdev->pc = pa->pa_pc; 976 rdev->pa_tag = pa->pa_tag; 977 rdev->iot = pa->pa_iot; 978 rdev->memt = pa->pa_memt; 979 rdev->dmat = pa->pa_dmat; 980 981#if defined(__sparc64__) || defined(__macppc__) 982 if (fbnode == PCITAG_NODE(rdev->pa_tag)) 983 rdev->console = rdev->primary = 1; 984#else 985 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_DISPLAY && 986 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_DISPLAY_VGA && 987 (pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) 988 & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE)) 989 == (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE)) { 990 rdev->primary = 1; 991#if NVGA > 0 992 rdev->console = vga_is_console(pa->pa_iot, -1); 993 vga_console_attached = 1; 994#endif 995 } 996 997#if NEFIFB > 0 998 if (efifb_is_primary(pa)) { 999 rdev->primary = 1; 1000 rdev->console = efifb_is_console(pa); 1001 efifb_detach(); 1002 } 1003#endif 1004#endif 1005 1006#define RADEON_PCI_MEM 0x10 1007 1008 type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, RADEON_PCI_MEM); 1009 if (PCI_MAPREG_TYPE(type) != PCI_MAPREG_TYPE_MEM || 1010 pci_mapreg_info(pa->pa_pc, pa->pa_tag, RADEON_PCI_MEM, 1011 type, &rdev->fb_aper_offset, &rdev->fb_aper_size, NULL)) { 1012 printf(": can't get frambuffer info\n"); 1013 return; 1014 } 1015 if (rdev->fb_aper_offset == 0) { 1016 bus_size_t start, end; 1017 bus_addr_t base; 1018 1019 KASSERT(pa->pa_memex != NULL); 1020 1021 start = max(PCI_MEM_START, pa->pa_memex->ex_start); 1022 end = min(PCI_MEM_END, pa->pa_memex->ex_end); 1023 if (extent_alloc_subregion(pa->pa_memex, start, end, 1024 rdev->fb_aper_size, rdev->fb_aper_size, 0, 0, 0, &base)) { 1025 printf(": can't reserve framebuffer space\n"); 1026 return; 1027 } 1028 pci_conf_write(pa->pa_pc, pa->pa_tag, RADEON_PCI_MEM, base); 1029 if (PCI_MAPREG_MEM_TYPE(type) == PCI_MAPREG_MEM_TYPE_64BIT) 1030 pci_conf_write(pa->pa_pc, pa->pa_tag, 1031 RADEON_PCI_MEM + 4, (uint64_t)base >> 32); 1032 rdev->fb_aper_offset = base; 1033 } 1034 1035 for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) { 1036 type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, i); 1037 if (type == PCI_MAPREG_TYPE_IO) { 1038 pci_mapreg_map(pa, i, type, 0, NULL, 1039 &rdev->rio_mem, NULL, &rdev->rio_mem_size, 0); 1040 break; 1041 } 1042 if (type == PCI_MAPREG_MEM_TYPE_64BIT) 1043 i += 4; 1044 } 1045 1046 if (rdev->family >= CHIP_BONAIRE) { 1047 type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 0x18); 1048 if (PCI_MAPREG_TYPE(type) != PCI_MAPREG_TYPE_MEM || 1049 pci_mapreg_map(pa, 0x18, type, BUS_SPACE_MAP_LINEAR, NULL, 1050 &rdev->doorbell.bsh, &rdev->doorbell.base, 1051 &rdev->doorbell.size, 0)) { 1052 printf(": can't map doorbell space\n"); 1053 return; 1054 } 1055 rdev->doorbell.ptr = bus_space_vaddr(rdev->memt, 1056 rdev->doorbell.bsh); 1057 } 1058 1059 if (rdev->family >= CHIP_BONAIRE) 1060 rmmio_bar = 0x24; 1061 else 1062 rmmio_bar = 0x18; 1063 1064 type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, rmmio_bar); 1065 if (PCI_MAPREG_TYPE(type) != PCI_MAPREG_TYPE_MEM || 1066 pci_mapreg_map(pa, rmmio_bar, type, BUS_SPACE_MAP_LINEAR, NULL, 1067 &rdev->rmmio_bsh, &rdev->rmmio_base, &rdev->rmmio_size, 0)) { 1068 printf(": can't map rmmio space\n"); 1069 return; 1070 } 1071 rdev->rmmio = bus_space_vaddr(rdev->memt, rdev->rmmio_bsh); 1072 1073 /* 1074 * Make sure we have a base address for the ROM such that we 1075 * can map it later. 1076 */ 1077 s = splhigh(); 1078 addr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ROM_REG); 1079 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, ~PCI_ROM_ENABLE); 1080 mask = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ROM_REG); 1081 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, addr); 1082 splx(s); 1083 1084 if (addr == 0 && PCI_ROM_SIZE(mask) != 0 && pa->pa_memex) { 1085 bus_size_t size, start, end; 1086 bus_addr_t base; 1087 1088 size = PCI_ROM_SIZE(mask); 1089 start = max(PCI_MEM_START, pa->pa_memex->ex_start); 1090 end = min(PCI_MEM_END, pa->pa_memex->ex_end); 1091 if (extent_alloc_subregion(pa->pa_memex, start, end, size, 1092 size, 0, 0, 0, &base) == 0) 1093 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_ROM_REG, base); 1094 } 1095 1096 /* update BUS flag */ 1097 if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP, NULL, NULL)) { 1098 rdev->flags |= RADEON_IS_AGP; 1099 } else if (pci_get_capability(pa->pa_pc, pa->pa_tag, 1100 PCI_CAP_PCIEXPRESS, NULL, NULL)) { 1101 rdev->flags |= RADEON_IS_PCIE; 1102 } else { 1103 rdev->flags |= RADEON_IS_PCI; 1104 } 1105 1106 if ((radeon_runtime_pm != 0) && 1107 radeon_has_atpx() && 1108 ((rdev->flags & RADEON_IS_IGP) == 0)) 1109 rdev->flags |= RADEON_IS_PX; 1110 1111 DRM_DEBUG("%s card detected\n", 1112 ((rdev->flags & RADEON_IS_AGP) ? "AGP" : 1113 (((rdev->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI")))); 1114 1115 is_agp = pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP, 1116 NULL, NULL); 1117 1118 printf("\n"); 1119 1120 dev = drm_attach_pci(&kms_driver, pa, is_agp, rdev->primary, 1121 self, NULL); 1122 if (dev == NULL) { 1123 printf("%s: drm attach failed\n", rdev->self.dv_xname); 1124 return; 1125 } 1126 rdev->ddev = dev; 1127 rdev->pdev = dev->pdev; 1128 1129 if (!radeon_msi_ok(rdev)) 1130 pa->pa_flags &= ~PCI_FLAGS_MSI_ENABLED; 1131 1132 rdev->msi_enabled = 0; 1133 if (pci_intr_map_msi(pa, &rdev->intrh) == 0) 1134 rdev->msi_enabled = 1; 1135 else if (pci_intr_map(pa, &rdev->intrh) != 0) { 1136 printf("%s: couldn't map interrupt\n", rdev->self.dv_xname); 1137 return; 1138 } 1139 printf("%s: %s\n", rdev->self.dv_xname, 1140 pci_intr_string(pa->pa_pc, rdev->intrh)); 1141 1142 rdev->irqh = pci_intr_establish(pa->pa_pc, rdev->intrh, IPL_TTY, 1143 radeon_driver_irq_handler_kms, rdev->ddev, rdev->self.dv_xname); 1144 if (rdev->irqh == NULL) { 1145 printf("%s: couldn't establish interrupt\n", 1146 rdev->self.dv_xname); 1147 return; 1148 } 1149 rdev->pdev->irq = -1; 1150 1151#ifdef __sparc64__ 1152{ 1153 struct rasops_info *ri; 1154 int node, console; 1155 1156 node = PCITAG_NODE(pa->pa_tag); 1157 console = (fbnode == node); 1158 1159 fb_setsize(&rdev->sf, 8, 1152, 900, node, 0); 1160 1161 /* 1162 * The firmware sets up the framebuffer such that it starts at 1163 * an offset from the start of video memory. 1164 */ 1165 rdev->fb_offset = 1166 bus_space_read_4(rdev->memt, rdev->rmmio_bsh, RADEON_CRTC_OFFSET); 1167 if (bus_space_map(rdev->memt, rdev->fb_aper_offset + rdev->fb_offset, 1168 rdev->sf.sf_fbsize, BUS_SPACE_MAP_LINEAR, &rdev->memh)) { 1169 printf("%s: can't map video memory\n", rdev->self.dv_xname); 1170 return; 1171 } 1172 1173 ri = &rdev->sf.sf_ro; 1174 ri->ri_bits = bus_space_vaddr(rdev->memt, rdev->memh); 1175 ri->ri_hw = rdev; 1176 ri->ri_updatecursor = NULL; 1177 1178 fbwscons_init(&rdev->sf, RI_VCONS | RI_WRONLY | RI_BSWAP, console); 1179 if (console) 1180 fbwscons_console_init(&rdev->sf, -1); 1181} 1182#endif 1183 1184 fb_aper = bus_space_mmap(rdev->memt, rdev->fb_aper_offset, 0, 0, 0); 1185 if (fb_aper != -1) 1186 rasops_claim_framebuffer(fb_aper, rdev->fb_aper_size, self); 1187 1188 rdev->shutdown = true; 1189 config_mountroot(self, radeondrm_attachhook); 1190} 1191 1192int 1193radeondrm_forcedetach(struct radeon_device *rdev) 1194{ 1195 struct pci_softc *sc = (struct pci_softc *)rdev->self.dv_parent; 1196 pcitag_t tag = rdev->pa_tag; 1197 1198#if NVGA > 0 1199 if (rdev->primary) 1200 vga_console_attached = 0; 1201#endif 1202 1203 /* reprobe pci device for non efi systems */ 1204#if NEFIFB > 0 1205 if (bios_efiinfo == NULL && !efifb_cb_found()) { 1206#endif 1207 config_detach(&rdev->self, 0); 1208 return pci_probe_device(sc, tag, NULL, NULL); 1209#if NEFIFB > 0 1210 } else if (rdev->primary) { 1211 efifb_reattach(); 1212 } 1213#endif 1214 1215 return 0; 1216} 1217 1218void 1219radeondrm_attachhook(struct device *self) 1220{ 1221 struct radeon_device *rdev = (struct radeon_device *)self; 1222 struct drm_device *dev = rdev->ddev; 1223 int r, acpi_status; 1224 1225 /* radeon_device_init should report only fatal error 1226 * like memory allocation failure or iomapping failure, 1227 * or memory manager initialization failure, it must 1228 * properly initialize the GPU MC controller and permit 1229 * VRAM allocation 1230 */ 1231 r = radeon_device_init(rdev, rdev->ddev, rdev->ddev->pdev, rdev->flags); 1232 if (r) { 1233 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n"); 1234 radeon_fatal_error = 1; 1235 radeondrm_forcedetach(rdev); 1236 return; 1237 } 1238 1239 /* Again modeset_init should fail only on fatal error 1240 * otherwise it should provide enough functionalities 1241 * for shadowfb to run 1242 */ 1243 r = radeon_modeset_init(rdev); 1244 if (r) 1245 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n"); 1246 1247 /* Call ACPI methods: require modeset init 1248 * but failure is not fatal 1249 */ 1250 if (!r) { 1251 acpi_status = radeon_acpi_init(rdev); 1252 if (acpi_status) 1253 DRM_DEBUG("Error during ACPI methods call\n"); 1254 } 1255 1256#ifdef notyet 1257 radeon_kfd_device_probe(rdev); 1258 radeon_kfd_device_init(rdev); 1259#endif 1260 1261 if (radeon_is_px(rdev->ddev)) { 1262 pm_runtime_use_autosuspend(dev->dev); 1263 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 1264 pm_runtime_set_active(dev->dev); 1265 pm_runtime_allow(dev->dev); 1266 pm_runtime_mark_last_busy(dev->dev); 1267 pm_runtime_put_autosuspend(dev->dev); 1268 } 1269 1270{ 1271 struct wsemuldisplaydev_attach_args aa; 1272 struct rasops_info *ri = &rdev->ro; 1273 1274 task_set(&rdev->switchtask, radeondrm_doswitch, ri); 1275 1276 /* 1277 * in linux via radeon_pci_probe -> drm_get_pci_dev -> drm_dev_register 1278 */ 1279 drm_dev_register(rdev->ddev, rdev->flags); 1280 1281 radeon_fbdev_setup(rdev); 1282 1283 if (ri->ri_bits == NULL) 1284 return; 1285 1286#ifdef __sparc64__ 1287 fbwscons_setcolormap(&rdev->sf, radeondrm_setcolor); 1288 ri = &rdev->sf.sf_ro; 1289#else 1290 radeondrm_setpal(rdev, ri); 1291 ri->ri_flg = RI_CENTER | RI_VCONS | RI_WRONLY; 1292 rasops_init(ri, 160, 160); 1293 1294 ri->ri_hw = rdev; 1295#endif 1296 1297 radeondrm_stdscreen.capabilities = ri->ri_caps; 1298 radeondrm_stdscreen.nrows = ri->ri_rows; 1299 radeondrm_stdscreen.ncols = ri->ri_cols; 1300 radeondrm_stdscreen.textops = &ri->ri_ops; 1301 radeondrm_stdscreen.fontwidth = ri->ri_font->fontwidth; 1302 radeondrm_stdscreen.fontheight = ri->ri_font->fontheight; 1303 1304 aa.console = rdev->console; 1305 aa.primary = rdev->primary; 1306 aa.scrdata = &radeondrm_screenlist; 1307 aa.accessops = &radeondrm_accessops; 1308 aa.accesscookie = ri; 1309 aa.defaultscreens = 0; 1310 1311 if (rdev->console) { 1312 uint32_t defattr; 1313 1314 ri->ri_ops.pack_attr(ri->ri_active, 0, 0, 0, &defattr); 1315 wsdisplay_cnattach(&radeondrm_stdscreen, ri->ri_active, 1316 ri->ri_ccol, ri->ri_crow, defattr); 1317 } 1318 1319 /* 1320 * Now that we've taken over the console, disable decoding of 1321 * VGA legacy addresses, and opt out of arbitration. 1322 */ 1323 radeon_vga_set_state(rdev, false); 1324 pci_disable_legacy_vga(&rdev->self); 1325 1326 printf("%s: %dx%d, %dbpp\n", rdev->self.dv_xname, 1327 ri->ri_width, ri->ri_height, ri->ri_depth); 1328 1329 config_found_sm(&rdev->self, &aa, wsemuldisplaydevprint, 1330 wsemuldisplaydevsubmatch); 1331} 1332} 1333 1334int 1335radeondrm_activate_kms(struct device *self, int act) 1336{ 1337 struct radeon_device *rdev = (struct radeon_device *)self; 1338 int rv = 0; 1339 1340 if (rdev->ddev == NULL || radeon_fatal_error) 1341 return (0); 1342 1343 switch (act) { 1344 case DVACT_QUIESCE: 1345 rv = config_activate_children(self, act); 1346 radeon_suspend_kms(rdev->ddev, true, true, false); 1347 break; 1348 case DVACT_SUSPEND: 1349 break; 1350 case DVACT_RESUME: 1351 break; 1352 case DVACT_WAKEUP: 1353 radeon_resume_kms(rdev->ddev, true, true); 1354 rv = config_activate_children(self, act); 1355 break; 1356 } 1357 1358 return (rv); 1359} 1360