1/* 2 * File: include/asm-blackfin/mach-bf561/mem_init.h 3 * Based on: 4 * Author: 5 * 6 * Created: 7 * Description: 8 * 9 * Rev: 10 * 11 * Modified: 12 * 13 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 14 * 15 * This program is free software; you can redistribute it and/or modify 16 * it under the terms of the GNU General Public License as published by 17 * the Free Software Foundation; either version 2, or (at your option) 18 * any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; see the file COPYING. 27 * If not, write to the Free Software Foundation, 28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 29 */ 30 31#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || \ 32 CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC8M32B2B5_7) 33#if (CONFIG_SCLK_HZ > 119402985) 34#define SDRAM_tRP TRP_2 35#define SDRAM_tRP_num 2 36#define SDRAM_tRAS TRAS_7 37#define SDRAM_tRAS_num 7 38#define SDRAM_tRCD TRCD_2 39#define SDRAM_tWR TWR_2 40#endif 41#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985) 42#define SDRAM_tRP TRP_2 43#define SDRAM_tRP_num 2 44#define SDRAM_tRAS TRAS_6 45#define SDRAM_tRAS_num 6 46#define SDRAM_tRCD TRCD_2 47#define SDRAM_tWR TWR_2 48#endif 49#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612) 50#define SDRAM_tRP TRP_2 51#define SDRAM_tRP_num 2 52#define SDRAM_tRAS TRAS_5 53#define SDRAM_tRAS_num 5 54#define SDRAM_tRCD TRCD_2 55#define SDRAM_tWR TWR_2 56#endif 57#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239) 58#define SDRAM_tRP TRP_2 59#define SDRAM_tRP_num 2 60#define SDRAM_tRAS TRAS_4 61#define SDRAM_tRAS_num 4 62#define SDRAM_tRCD TRCD_2 63#define SDRAM_tWR TWR_2 64#endif 65#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866) 66#define SDRAM_tRP TRP_2 67#define SDRAM_tRP_num 2 68#define SDRAM_tRAS TRAS_3 69#define SDRAM_tRAS_num 3 70#define SDRAM_tRCD TRCD_2 71#define SDRAM_tWR TWR_2 72#endif 73#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667) 74#define SDRAM_tRP TRP_1 75#define SDRAM_tRP_num 1 76#define SDRAM_tRAS TRAS_4 77#define SDRAM_tRAS_num 3 78#define SDRAM_tRCD TRCD_1 79#define SDRAM_tWR TWR_2 80#endif 81#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493) 82#define SDRAM_tRP TRP_1 83#define SDRAM_tRP_num 1 84#define SDRAM_tRAS TRAS_3 85#define SDRAM_tRAS_num 3 86#define SDRAM_tRCD TRCD_1 87#define SDRAM_tWR TWR_2 88#endif 89#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119) 90#define SDRAM_tRP TRP_1 91#define SDRAM_tRP_num 1 92#define SDRAM_tRAS TRAS_2 93#define SDRAM_tRAS_num 2 94#define SDRAM_tRCD TRCD_1 95#define SDRAM_tWR TWR_2 96#endif 97#if (CONFIG_SCLK_HZ <= 29850746) 98#define SDRAM_tRP TRP_1 99#define SDRAM_tRP_num 1 100#define SDRAM_tRAS TRAS_1 101#define SDRAM_tRAS_num 1 102#define SDRAM_tRCD TRCD_1 103#define SDRAM_tWR TWR_2 104#endif 105#endif 106 107#if CONFIG_MEM_MT48LC16M16A2TG_75 108 /*SDRAM INFORMATION: */ 109#define SDRAM_Tref 64 /* Refresh period in milliseconds */ 110#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ 111#define SDRAM_CL CL_3 112#endif 113 114#if CONFIG_MEM_MT48LC64M4A2FB_7E 115 /*SDRAM INFORMATION: */ 116#define SDRAM_Tref 64 /* Refresh period in milliseconds */ 117#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ 118#define SDRAM_CL CL_3 119#endif 120 121#if CONFIG_MEM_MT48LC8M32B2B5_7 122 /*SDRAM INFORMATION: */ 123#define SDRAM_Tref 64 /* Refresh period in milliseconds */ 124#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */ 125#define SDRAM_CL CL_3 126#endif 127 128#if CONFIG_MEM_GENERIC_BOARD 129 /*SDRAM INFORMATION: Modify this for your board */ 130#define SDRAM_Tref 64 /* Refresh period in milliseconds */ 131#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ 132#define SDRAM_CL CL_3 133#endif 134 135#if (CONFIG_MEM_SIZE == 128) 136#define SDRAM_SIZE EB0_SZ_128 137#endif 138#if (CONFIG_MEM_SIZE == 64) 139#define SDRAM_SIZE EB0_SZ_64 140#endif 141#if ( CONFIG_MEM_SIZE == 32) 142#define SDRAM_SIZE EB0_SZ_32 143#endif 144#if (CONFIG_MEM_SIZE == 16) 145#define SDRAM_SIZE EB0_SZ_16 146#endif 147#if (CONFIG_MEM_ADD_WIDTH == 11) 148#define SDRAM_WIDTH EB0_CAW_11 149#endif 150#if (CONFIG_MEM_ADD_WIDTH == 10) 151#define SDRAM_WIDTH EB0_CAW_10 152#endif 153#if (CONFIG_MEM_ADD_WIDTH == 9) 154#define SDRAM_WIDTH EB0_CAW_9 155#endif 156#if (CONFIG_MEM_ADD_WIDTH == 8) 157#define SDRAM_WIDTH EB0_CAW_8 158#endif 159 160#define mem_SDBCTL (SDRAM_WIDTH | SDRAM_SIZE | EB0_E) 161 162/* Equation from section 17 (p17-46) of BF533 HRM */ 163#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num) 164 165/* Enable SCLK Out */ 166#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS) 167 168#if defined CONFIG_CLKIN_HALF 169#define CLKIN_HALF 1 170#else 171#define CLKIN_HALF 0 172#endif 173 174#if defined CONFIG_PLL_BYPASS 175#define PLL_BYPASS 1 176#else 177#define PLL_BYPASS 0 178#endif 179 180/***************************************Currently Not Being Used *********************************/ 181#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 182#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 183#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ)) 184#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 185#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1 186 187#if (flash_EBIU_AMBCTL_TT > 3) 188#define flash_EBIU_AMBCTL0_TT B0TT_4 189#endif 190#if (flash_EBIU_AMBCTL_TT == 3) 191#define flash_EBIU_AMBCTL0_TT B0TT_3 192#endif 193#if (flash_EBIU_AMBCTL_TT == 2) 194#define flash_EBIU_AMBCTL0_TT B0TT_2 195#endif 196#if (flash_EBIU_AMBCTL_TT < 2) 197#define flash_EBIU_AMBCTL0_TT B0TT_1 198#endif 199 200#if (flash_EBIU_AMBCTL_ST > 3) 201#define flash_EBIU_AMBCTL0_ST B0ST_4 202#endif 203#if (flash_EBIU_AMBCTL_ST == 3) 204#define flash_EBIU_AMBCTL0_ST B0ST_3 205#endif 206#if (flash_EBIU_AMBCTL_ST == 2) 207#define flash_EBIU_AMBCTL0_ST B0ST_2 208#endif 209#if (flash_EBIU_AMBCTL_ST < 2) 210#define flash_EBIU_AMBCTL0_ST B0ST_1 211#endif 212 213#if (flash_EBIU_AMBCTL_HT > 2) 214#define flash_EBIU_AMBCTL0_HT B0HT_3 215#endif 216#if (flash_EBIU_AMBCTL_HT == 2) 217#define flash_EBIU_AMBCTL0_HT B0HT_2 218#endif 219#if (flash_EBIU_AMBCTL_HT == 1) 220#define flash_EBIU_AMBCTL0_HT B0HT_1 221#endif 222#if (flash_EBIU_AMBCTL_HT == 1) 223#define flash_EBIU_AMBCTL0_HT B0HT_0 224#endif 225#if (flash_EBIU_AMBCTL_HT == 0) 226#define flash_EBIU_AMBCTL0_HT B0HT_1 227#endif 228 229#if (flash_EBIU_AMBCTL_WAT > 14) 230#define flash_EBIU_AMBCTL0_WAT B0WAT_15 231#endif 232#if (flash_EBIU_AMBCTL_WAT == 14) 233#define flash_EBIU_AMBCTL0_WAT B0WAT_14 234#endif 235#if (flash_EBIU_AMBCTL_WAT == 13) 236#define flash_EBIU_AMBCTL0_WAT B0WAT_13 237#endif 238#if (flash_EBIU_AMBCTL_WAT == 12) 239#define flash_EBIU_AMBCTL0_WAT B0WAT_12 240#endif 241#if (flash_EBIU_AMBCTL_WAT == 11) 242#define flash_EBIU_AMBCTL0_WAT B0WAT_11 243#endif 244#if (flash_EBIU_AMBCTL_WAT == 10) 245#define flash_EBIU_AMBCTL0_WAT B0WAT_10 246#endif 247#if (flash_EBIU_AMBCTL_WAT == 9) 248#define flash_EBIU_AMBCTL0_WAT B0WAT_9 249#endif 250#if (flash_EBIU_AMBCTL_WAT == 8) 251#define flash_EBIU_AMBCTL0_WAT B0WAT_8 252#endif 253#if (flash_EBIU_AMBCTL_WAT == 7) 254#define flash_EBIU_AMBCTL0_WAT B0WAT_7 255#endif 256#if (flash_EBIU_AMBCTL_WAT == 6) 257#define flash_EBIU_AMBCTL0_WAT B0WAT_6 258#endif 259#if (flash_EBIU_AMBCTL_WAT == 5) 260#define flash_EBIU_AMBCTL0_WAT B0WAT_5 261#endif 262#if (flash_EBIU_AMBCTL_WAT == 4) 263#define flash_EBIU_AMBCTL0_WAT B0WAT_4 264#endif 265#if (flash_EBIU_AMBCTL_WAT == 3) 266#define flash_EBIU_AMBCTL0_WAT B0WAT_3 267#endif 268#if (flash_EBIU_AMBCTL_WAT == 2) 269#define flash_EBIU_AMBCTL0_WAT B0WAT_2 270#endif 271#if (flash_EBIU_AMBCTL_WAT == 1) 272#define flash_EBIU_AMBCTL0_WAT B0WAT_1 273#endif 274 275#if (flash_EBIU_AMBCTL_RAT > 14) 276#define flash_EBIU_AMBCTL0_RAT B0RAT_15 277#endif 278#if (flash_EBIU_AMBCTL_RAT == 14) 279#define flash_EBIU_AMBCTL0_RAT B0RAT_14 280#endif 281#if (flash_EBIU_AMBCTL_RAT == 13) 282#define flash_EBIU_AMBCTL0_RAT B0RAT_13 283#endif 284#if (flash_EBIU_AMBCTL_RAT == 12) 285#define flash_EBIU_AMBCTL0_RAT B0RAT_12 286#endif 287#if (flash_EBIU_AMBCTL_RAT == 11) 288#define flash_EBIU_AMBCTL0_RAT B0RAT_11 289#endif 290#if (flash_EBIU_AMBCTL_RAT == 10) 291#define flash_EBIU_AMBCTL0_RAT B0RAT_10 292#endif 293#if (flash_EBIU_AMBCTL_RAT == 9) 294#define flash_EBIU_AMBCTL0_RAT B0RAT_9 295#endif 296#if (flash_EBIU_AMBCTL_RAT == 8) 297#define flash_EBIU_AMBCTL0_RAT B0RAT_8 298#endif 299#if (flash_EBIU_AMBCTL_RAT == 7) 300#define flash_EBIU_AMBCTL0_RAT B0RAT_7 301#endif 302#if (flash_EBIU_AMBCTL_RAT == 6) 303#define flash_EBIU_AMBCTL0_RAT B0RAT_6 304#endif 305#if (flash_EBIU_AMBCTL_RAT == 5) 306#define flash_EBIU_AMBCTL0_RAT B0RAT_5 307#endif 308#if (flash_EBIU_AMBCTL_RAT == 4) 309#define flash_EBIU_AMBCTL0_RAT B0RAT_4 310#endif 311#if (flash_EBIU_AMBCTL_RAT == 3) 312#define flash_EBIU_AMBCTL0_RAT B0RAT_3 313#endif 314#if (flash_EBIU_AMBCTL_RAT == 2) 315#define flash_EBIU_AMBCTL0_RAT B0RAT_2 316#endif 317#if (flash_EBIU_AMBCTL_RAT == 1) 318#define flash_EBIU_AMBCTL0_RAT B0RAT_1 319#endif 320 321#define flash_EBIU_AMBCTL0 \ 322 (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \ 323 flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN) 324