1/* sunhme.c: Sparc HME/BigMac 10/100baseT half/full duplex auto switching, 2 * auto carrier detecting ethernet driver. Also known as the 3 * "Happy Meal Ethernet" found on SunSwift SBUS cards. 4 * 5 * Copyright (C) 1996, 1998, 1999, 2002, 2003, 6 2006 David S. Miller (davem@davemloft.net) 7 * 8 * Changes : 9 * 2000/11/11 Willy Tarreau <willy AT meta-x.org> 10 * - port to non-sparc architectures. Tested only on x86 and 11 * only currently works with QFE PCI cards. 12 * - ability to specify the MAC address at module load time by passing this 13 * argument : macaddr=0x00,0x10,0x20,0x30,0x40,0x50 14 */ 15 16#include <linux/module.h> 17#include <linux/kernel.h> 18#include <linux/types.h> 19#include <linux/fcntl.h> 20#include <linux/interrupt.h> 21#include <linux/ioport.h> 22#include <linux/in.h> 23#include <linux/slab.h> 24#include <linux/string.h> 25#include <linux/delay.h> 26#include <linux/init.h> 27#include <linux/ethtool.h> 28#include <linux/mii.h> 29#include <linux/crc32.h> 30#include <linux/random.h> 31#include <linux/errno.h> 32#include <linux/netdevice.h> 33#include <linux/etherdevice.h> 34#include <linux/skbuff.h> 35#include <linux/mm.h> 36#include <linux/bitops.h> 37 38#include <asm/system.h> 39#include <asm/io.h> 40#include <asm/dma.h> 41#include <asm/byteorder.h> 42 43#ifdef CONFIG_SPARC 44#include <asm/idprom.h> 45#include <asm/sbus.h> 46#include <asm/openprom.h> 47#include <asm/oplib.h> 48#include <asm/prom.h> 49#include <asm/auxio.h> 50#endif 51#include <asm/uaccess.h> 52 53#include <asm/pgtable.h> 54#include <asm/irq.h> 55 56#ifdef CONFIG_PCI 57#include <linux/pci.h> 58#endif 59 60#include "sunhme.h" 61 62#define DRV_NAME "sunhme" 63#define DRV_VERSION "3.00" 64#define DRV_RELDATE "June 23, 2006" 65#define DRV_AUTHOR "David S. Miller (davem@davemloft.net)" 66 67static char version[] = 68 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n"; 69 70MODULE_VERSION(DRV_VERSION); 71MODULE_AUTHOR(DRV_AUTHOR); 72MODULE_DESCRIPTION("Sun HappyMealEthernet(HME) 10/100baseT ethernet driver"); 73MODULE_LICENSE("GPL"); 74 75static int macaddr[6]; 76 77/* accept MAC address of the form macaddr=0x08,0x00,0x20,0x30,0x40,0x50 */ 78module_param_array(macaddr, int, NULL, 0); 79MODULE_PARM_DESC(macaddr, "Happy Meal MAC address to set"); 80 81#ifdef CONFIG_SBUS 82static struct quattro *qfe_sbus_list; 83#endif 84 85#ifdef CONFIG_PCI 86static struct quattro *qfe_pci_list; 87#endif 88 89#undef HMEDEBUG 90#undef SXDEBUG 91#undef RXDEBUG 92#undef TXDEBUG 93#undef TXLOGGING 94 95#ifdef TXLOGGING 96struct hme_tx_logent { 97 unsigned int tstamp; 98 int tx_new, tx_old; 99 unsigned int action; 100#define TXLOG_ACTION_IRQ 0x01 101#define TXLOG_ACTION_TXMIT 0x02 102#define TXLOG_ACTION_TBUSY 0x04 103#define TXLOG_ACTION_NBUFS 0x08 104 unsigned int status; 105}; 106#define TX_LOG_LEN 128 107static struct hme_tx_logent tx_log[TX_LOG_LEN]; 108static int txlog_cur_entry; 109static __inline__ void tx_add_log(struct happy_meal *hp, unsigned int a, unsigned int s) 110{ 111 struct hme_tx_logent *tlp; 112 unsigned long flags; 113 114 save_and_cli(flags); 115 tlp = &tx_log[txlog_cur_entry]; 116 tlp->tstamp = (unsigned int)jiffies; 117 tlp->tx_new = hp->tx_new; 118 tlp->tx_old = hp->tx_old; 119 tlp->action = a; 120 tlp->status = s; 121 txlog_cur_entry = (txlog_cur_entry + 1) & (TX_LOG_LEN - 1); 122 restore_flags(flags); 123} 124static __inline__ void tx_dump_log(void) 125{ 126 int i, this; 127 128 this = txlog_cur_entry; 129 for (i = 0; i < TX_LOG_LEN; i++) { 130 printk("TXLOG[%d]: j[%08x] tx[N(%d)O(%d)] action[%08x] stat[%08x]\n", i, 131 tx_log[this].tstamp, 132 tx_log[this].tx_new, tx_log[this].tx_old, 133 tx_log[this].action, tx_log[this].status); 134 this = (this + 1) & (TX_LOG_LEN - 1); 135 } 136} 137static __inline__ void tx_dump_ring(struct happy_meal *hp) 138{ 139 struct hmeal_init_block *hb = hp->happy_block; 140 struct happy_meal_txd *tp = &hb->happy_meal_txd[0]; 141 int i; 142 143 for (i = 0; i < TX_RING_SIZE; i+=4) { 144 printk("TXD[%d..%d]: [%08x:%08x] [%08x:%08x] [%08x:%08x] [%08x:%08x]\n", 145 i, i + 4, 146 le32_to_cpu(tp[i].tx_flags), le32_to_cpu(tp[i].tx_addr), 147 le32_to_cpu(tp[i + 1].tx_flags), le32_to_cpu(tp[i + 1].tx_addr), 148 le32_to_cpu(tp[i + 2].tx_flags), le32_to_cpu(tp[i + 2].tx_addr), 149 le32_to_cpu(tp[i + 3].tx_flags), le32_to_cpu(tp[i + 3].tx_addr)); 150 } 151} 152#else 153#define tx_add_log(hp, a, s) do { } while(0) 154#define tx_dump_log() do { } while(0) 155#define tx_dump_ring(hp) do { } while(0) 156#endif 157 158#ifdef HMEDEBUG 159#define HMD(x) printk x 160#else 161#define HMD(x) 162#endif 163 164/* #define AUTO_SWITCH_DEBUG */ 165 166#ifdef AUTO_SWITCH_DEBUG 167#define ASD(x) printk x 168#else 169#define ASD(x) 170#endif 171 172#define DEFAULT_IPG0 16 /* For lance-mode only */ 173#define DEFAULT_IPG1 8 /* For all modes */ 174#define DEFAULT_IPG2 4 /* For all modes */ 175#define DEFAULT_JAMSIZE 4 /* Toe jam */ 176 177/* NOTE: In the descriptor writes one _must_ write the address 178 * member _first_. The card must not be allowed to see 179 * the updated descriptor flags until the address is 180 * correct. I've added a write memory barrier between 181 * the two stores so that I can sleep well at night... -DaveM 182 */ 183 184#if defined(CONFIG_SBUS) && defined(CONFIG_PCI) 185static void sbus_hme_write32(void __iomem *reg, u32 val) 186{ 187 sbus_writel(val, reg); 188} 189 190static u32 sbus_hme_read32(void __iomem *reg) 191{ 192 return sbus_readl(reg); 193} 194 195static void sbus_hme_write_rxd(struct happy_meal_rxd *rxd, u32 flags, u32 addr) 196{ 197 rxd->rx_addr = addr; 198 wmb(); 199 rxd->rx_flags = flags; 200} 201 202static void sbus_hme_write_txd(struct happy_meal_txd *txd, u32 flags, u32 addr) 203{ 204 txd->tx_addr = addr; 205 wmb(); 206 txd->tx_flags = flags; 207} 208 209static u32 sbus_hme_read_desc32(u32 *p) 210{ 211 return *p; 212} 213 214static void pci_hme_write32(void __iomem *reg, u32 val) 215{ 216 writel(val, reg); 217} 218 219static u32 pci_hme_read32(void __iomem *reg) 220{ 221 return readl(reg); 222} 223 224static void pci_hme_write_rxd(struct happy_meal_rxd *rxd, u32 flags, u32 addr) 225{ 226 rxd->rx_addr = cpu_to_le32(addr); 227 wmb(); 228 rxd->rx_flags = cpu_to_le32(flags); 229} 230 231static void pci_hme_write_txd(struct happy_meal_txd *txd, u32 flags, u32 addr) 232{ 233 txd->tx_addr = cpu_to_le32(addr); 234 wmb(); 235 txd->tx_flags = cpu_to_le32(flags); 236} 237 238static u32 pci_hme_read_desc32(u32 *p) 239{ 240 return cpu_to_le32p(p); 241} 242 243#define hme_write32(__hp, __reg, __val) \ 244 ((__hp)->write32((__reg), (__val))) 245#define hme_read32(__hp, __reg) \ 246 ((__hp)->read32(__reg)) 247#define hme_write_rxd(__hp, __rxd, __flags, __addr) \ 248 ((__hp)->write_rxd((__rxd), (__flags), (__addr))) 249#define hme_write_txd(__hp, __txd, __flags, __addr) \ 250 ((__hp)->write_txd((__txd), (__flags), (__addr))) 251#define hme_read_desc32(__hp, __p) \ 252 ((__hp)->read_desc32(__p)) 253#define hme_dma_map(__hp, __ptr, __size, __dir) \ 254 ((__hp)->dma_map((__hp)->happy_dev, (__ptr), (__size), (__dir))) 255#define hme_dma_unmap(__hp, __addr, __size, __dir) \ 256 ((__hp)->dma_unmap((__hp)->happy_dev, (__addr), (__size), (__dir))) 257#define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \ 258 ((__hp)->dma_sync_for_cpu((__hp)->happy_dev, (__addr), (__size), (__dir))) 259#define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \ 260 ((__hp)->dma_sync_for_device((__hp)->happy_dev, (__addr), (__size), (__dir))) 261#else 262#ifdef CONFIG_SBUS 263/* SBUS only compilation */ 264#define hme_write32(__hp, __reg, __val) \ 265 sbus_writel((__val), (__reg)) 266#define hme_read32(__hp, __reg) \ 267 sbus_readl(__reg) 268#define hme_write_rxd(__hp, __rxd, __flags, __addr) \ 269do { (__rxd)->rx_addr = (__addr); \ 270 wmb(); \ 271 (__rxd)->rx_flags = (__flags); \ 272} while(0) 273#define hme_write_txd(__hp, __txd, __flags, __addr) \ 274do { (__txd)->tx_addr = (__addr); \ 275 wmb(); \ 276 (__txd)->tx_flags = (__flags); \ 277} while(0) 278#define hme_read_desc32(__hp, __p) (*(__p)) 279#define hme_dma_map(__hp, __ptr, __size, __dir) \ 280 sbus_map_single((__hp)->happy_dev, (__ptr), (__size), (__dir)) 281#define hme_dma_unmap(__hp, __addr, __size, __dir) \ 282 sbus_unmap_single((__hp)->happy_dev, (__addr), (__size), (__dir)) 283#define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \ 284 sbus_dma_sync_single_for_cpu((__hp)->happy_dev, (__addr), (__size), (__dir)) 285#define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \ 286 sbus_dma_sync_single_for_device((__hp)->happy_dev, (__addr), (__size), (__dir)) 287#else 288/* PCI only compilation */ 289#define hme_write32(__hp, __reg, __val) \ 290 writel((__val), (__reg)) 291#define hme_read32(__hp, __reg) \ 292 readl(__reg) 293#define hme_write_rxd(__hp, __rxd, __flags, __addr) \ 294do { (__rxd)->rx_addr = cpu_to_le32(__addr); \ 295 wmb(); \ 296 (__rxd)->rx_flags = cpu_to_le32(__flags); \ 297} while(0) 298#define hme_write_txd(__hp, __txd, __flags, __addr) \ 299do { (__txd)->tx_addr = cpu_to_le32(__addr); \ 300 wmb(); \ 301 (__txd)->tx_flags = cpu_to_le32(__flags); \ 302} while(0) 303#define hme_read_desc32(__hp, __p) cpu_to_le32p(__p) 304#define hme_dma_map(__hp, __ptr, __size, __dir) \ 305 pci_map_single((__hp)->happy_dev, (__ptr), (__size), (__dir)) 306#define hme_dma_unmap(__hp, __addr, __size, __dir) \ 307 pci_unmap_single((__hp)->happy_dev, (__addr), (__size), (__dir)) 308#define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \ 309 pci_dma_sync_single_for_cpu((__hp)->happy_dev, (__addr), (__size), (__dir)) 310#define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \ 311 pci_dma_sync_single_for_device((__hp)->happy_dev, (__addr), (__size), (__dir)) 312#endif 313#endif 314 315 316#ifdef SBUS_DMA_BIDIRECTIONAL 317# define DMA_BIDIRECTIONAL SBUS_DMA_BIDIRECTIONAL 318#else 319# define DMA_BIDIRECTIONAL 0 320#endif 321 322#ifdef SBUS_DMA_FROMDEVICE 323# define DMA_FROMDEVICE SBUS_DMA_FROMDEVICE 324#else 325# define DMA_TODEVICE 1 326#endif 327 328#ifdef SBUS_DMA_TODEVICE 329# define DMA_TODEVICE SBUS_DMA_TODEVICE 330#else 331# define DMA_FROMDEVICE 2 332#endif 333 334 335/* Oh yes, the MIF BitBang is mighty fun to program. BitBucket is more like it. */ 336static void BB_PUT_BIT(struct happy_meal *hp, void __iomem *tregs, int bit) 337{ 338 hme_write32(hp, tregs + TCVR_BBDATA, bit); 339 hme_write32(hp, tregs + TCVR_BBCLOCK, 0); 340 hme_write32(hp, tregs + TCVR_BBCLOCK, 1); 341} 342 343 344static u32 BB_GET_BIT2(struct happy_meal *hp, void __iomem *tregs, int internal) 345{ 346 u32 retval; 347 348 hme_write32(hp, tregs + TCVR_BBCLOCK, 0); 349 udelay(1); 350 retval = hme_read32(hp, tregs + TCVR_CFG); 351 if (internal) 352 retval &= TCV_CFG_MDIO0; 353 else 354 retval &= TCV_CFG_MDIO1; 355 hme_write32(hp, tregs + TCVR_BBCLOCK, 1); 356 357 return retval; 358} 359 360#define TCVR_FAILURE 0x80000000 /* Impossible MIF read value */ 361 362static int happy_meal_bb_read(struct happy_meal *hp, 363 void __iomem *tregs, int reg) 364{ 365 u32 tmp; 366 int retval = 0; 367 int i; 368 369 ASD(("happy_meal_bb_read: reg=%d ", reg)); 370 371 /* Enable the MIF BitBang outputs. */ 372 hme_write32(hp, tregs + TCVR_BBOENAB, 1); 373 374 /* Force BitBang into the idle state. */ 375 for (i = 0; i < 32; i++) 376 BB_PUT_BIT(hp, tregs, 1); 377 378 /* Give it the read sequence. */ 379 BB_PUT_BIT(hp, tregs, 0); 380 BB_PUT_BIT(hp, tregs, 1); 381 BB_PUT_BIT(hp, tregs, 1); 382 BB_PUT_BIT(hp, tregs, 0); 383 384 /* Give it the PHY address. */ 385 tmp = hp->paddr & 0xff; 386 for (i = 4; i >= 0; i--) 387 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1)); 388 389 /* Tell it what register we want to read. */ 390 tmp = (reg & 0xff); 391 for (i = 4; i >= 0; i--) 392 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1)); 393 394 /* Close down the MIF BitBang outputs. */ 395 hme_write32(hp, tregs + TCVR_BBOENAB, 0); 396 397 /* Now read in the value. */ 398 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal)); 399 for (i = 15; i >= 0; i--) 400 retval |= BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal)); 401 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal)); 402 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal)); 403 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal)); 404 ASD(("value=%x\n", retval)); 405 return retval; 406} 407 408static void happy_meal_bb_write(struct happy_meal *hp, 409 void __iomem *tregs, int reg, 410 unsigned short value) 411{ 412 u32 tmp; 413 int i; 414 415 ASD(("happy_meal_bb_write: reg=%d value=%x\n", reg, value)); 416 417 /* Enable the MIF BitBang outputs. */ 418 hme_write32(hp, tregs + TCVR_BBOENAB, 1); 419 420 /* Force BitBang into the idle state. */ 421 for (i = 0; i < 32; i++) 422 BB_PUT_BIT(hp, tregs, 1); 423 424 /* Give it write sequence. */ 425 BB_PUT_BIT(hp, tregs, 0); 426 BB_PUT_BIT(hp, tregs, 1); 427 BB_PUT_BIT(hp, tregs, 0); 428 BB_PUT_BIT(hp, tregs, 1); 429 430 /* Give it the PHY address. */ 431 tmp = (hp->paddr & 0xff); 432 for (i = 4; i >= 0; i--) 433 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1)); 434 435 /* Tell it what register we will be writing. */ 436 tmp = (reg & 0xff); 437 for (i = 4; i >= 0; i--) 438 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1)); 439 440 /* Tell it to become ready for the bits. */ 441 BB_PUT_BIT(hp, tregs, 1); 442 BB_PUT_BIT(hp, tregs, 0); 443 444 for (i = 15; i >= 0; i--) 445 BB_PUT_BIT(hp, tregs, ((value >> i) & 1)); 446 447 /* Close down the MIF BitBang outputs. */ 448 hme_write32(hp, tregs + TCVR_BBOENAB, 0); 449} 450 451#define TCVR_READ_TRIES 16 452 453static int happy_meal_tcvr_read(struct happy_meal *hp, 454 void __iomem *tregs, int reg) 455{ 456 int tries = TCVR_READ_TRIES; 457 int retval; 458 459 ASD(("happy_meal_tcvr_read: reg=0x%02x ", reg)); 460 if (hp->tcvr_type == none) { 461 ASD(("no transceiver, value=TCVR_FAILURE\n")); 462 return TCVR_FAILURE; 463 } 464 465 if (!(hp->happy_flags & HFLAG_FENABLE)) { 466 ASD(("doing bit bang\n")); 467 return happy_meal_bb_read(hp, tregs, reg); 468 } 469 470 hme_write32(hp, tregs + TCVR_FRAME, 471 (FRAME_READ | (hp->paddr << 23) | ((reg & 0xff) << 18))); 472 while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries) 473 udelay(20); 474 if (!tries) { 475 printk(KERN_ERR "happy meal: Aieee, transceiver MIF read bolixed\n"); 476 return TCVR_FAILURE; 477 } 478 retval = hme_read32(hp, tregs + TCVR_FRAME) & 0xffff; 479 ASD(("value=%04x\n", retval)); 480 return retval; 481} 482 483#define TCVR_WRITE_TRIES 16 484 485static void happy_meal_tcvr_write(struct happy_meal *hp, 486 void __iomem *tregs, int reg, 487 unsigned short value) 488{ 489 int tries = TCVR_WRITE_TRIES; 490 491 ASD(("happy_meal_tcvr_write: reg=0x%02x value=%04x\n", reg, value)); 492 493 /* Welcome to Sun Microsystems, can I take your order please? */ 494 if (!(hp->happy_flags & HFLAG_FENABLE)) { 495 happy_meal_bb_write(hp, tregs, reg, value); 496 return; 497 } 498 499 /* Would you like fries with that? */ 500 hme_write32(hp, tregs + TCVR_FRAME, 501 (FRAME_WRITE | (hp->paddr << 23) | 502 ((reg & 0xff) << 18) | (value & 0xffff))); 503 while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries) 504 udelay(20); 505 506 /* Anything else? */ 507 if (!tries) 508 printk(KERN_ERR "happy meal: Aieee, transceiver MIF write bolixed\n"); 509 510 /* Fifty-two cents is your change, have a nice day. */ 511} 512 513/* Auto negotiation. The scheme is very simple. We have a timer routine 514 * that keeps watching the auto negotiation process as it progresses. 515 * The DP83840 is first told to start doing it's thing, we set up the time 516 * and place the timer state machine in it's initial state. 517 * 518 * Here the timer peeks at the DP83840 status registers at each click to see 519 * if the auto negotiation has completed, we assume here that the DP83840 PHY 520 * will time out at some point and just tell us what (didn't) happen. For 521 * complete coverage we only allow so many of the ticks at this level to run, 522 * when this has expired we print a warning message and try another strategy. 523 * This "other" strategy is to force the interface into various speed/duplex 524 * configurations and we stop when we see a link-up condition before the 525 * maximum number of "peek" ticks have occurred. 526 * 527 * Once a valid link status has been detected we configure the BigMAC and 528 * the rest of the Happy Meal to speak the most efficient protocol we could 529 * get a clean link for. The priority for link configurations, highest first 530 * is: 531 * 100 Base-T Full Duplex 532 * 100 Base-T Half Duplex 533 * 10 Base-T Full Duplex 534 * 10 Base-T Half Duplex 535 * 536 * We start a new timer now, after a successful auto negotiation status has 537 * been detected. This timer just waits for the link-up bit to get set in 538 * the BMCR of the DP83840. When this occurs we print a kernel log message 539 * describing the link type in use and the fact that it is up. 540 * 541 * If a fatal error of some sort is signalled and detected in the interrupt 542 * service routine, and the chip is reset, or the link is ifconfig'd down 543 * and then back up, this entire process repeats itself all over again. 544 */ 545static int try_next_permutation(struct happy_meal *hp, void __iomem *tregs) 546{ 547 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR); 548 549 /* Downgrade from full to half duplex. Only possible 550 * via ethtool. 551 */ 552 if (hp->sw_bmcr & BMCR_FULLDPLX) { 553 hp->sw_bmcr &= ~(BMCR_FULLDPLX); 554 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr); 555 return 0; 556 } 557 558 /* Downgrade from 100 to 10. */ 559 if (hp->sw_bmcr & BMCR_SPEED100) { 560 hp->sw_bmcr &= ~(BMCR_SPEED100); 561 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr); 562 return 0; 563 } 564 565 /* We've tried everything. */ 566 return -1; 567} 568 569static void display_link_mode(struct happy_meal *hp, void __iomem *tregs) 570{ 571 printk(KERN_INFO "%s: Link is up using ", hp->dev->name); 572 if (hp->tcvr_type == external) 573 printk("external "); 574 else 575 printk("internal "); 576 printk("transceiver at "); 577 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA); 578 if (hp->sw_lpa & (LPA_100HALF | LPA_100FULL)) { 579 if (hp->sw_lpa & LPA_100FULL) 580 printk("100Mb/s, Full Duplex.\n"); 581 else 582 printk("100Mb/s, Half Duplex.\n"); 583 } else { 584 if (hp->sw_lpa & LPA_10FULL) 585 printk("10Mb/s, Full Duplex.\n"); 586 else 587 printk("10Mb/s, Half Duplex.\n"); 588 } 589} 590 591static void display_forced_link_mode(struct happy_meal *hp, void __iomem *tregs) 592{ 593 printk(KERN_INFO "%s: Link has been forced up using ", hp->dev->name); 594 if (hp->tcvr_type == external) 595 printk("external "); 596 else 597 printk("internal "); 598 printk("transceiver at "); 599 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR); 600 if (hp->sw_bmcr & BMCR_SPEED100) 601 printk("100Mb/s, "); 602 else 603 printk("10Mb/s, "); 604 if (hp->sw_bmcr & BMCR_FULLDPLX) 605 printk("Full Duplex.\n"); 606 else 607 printk("Half Duplex.\n"); 608} 609 610static int set_happy_link_modes(struct happy_meal *hp, void __iomem *tregs) 611{ 612 int full; 613 614 /* All we care about is making sure the bigmac tx_cfg has a 615 * proper duplex setting. 616 */ 617 if (hp->timer_state == arbwait) { 618 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA); 619 if (!(hp->sw_lpa & (LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL))) 620 goto no_response; 621 if (hp->sw_lpa & LPA_100FULL) 622 full = 1; 623 else if (hp->sw_lpa & LPA_100HALF) 624 full = 0; 625 else if (hp->sw_lpa & LPA_10FULL) 626 full = 1; 627 else 628 full = 0; 629 } else { 630 /* Forcing a link mode. */ 631 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR); 632 if (hp->sw_bmcr & BMCR_FULLDPLX) 633 full = 1; 634 else 635 full = 0; 636 } 637 638 /* Before changing other bits in the tx_cfg register, and in 639 * general any of other the TX config registers too, you 640 * must: 641 * 1) Clear Enable 642 * 2) Poll with reads until that bit reads back as zero 643 * 3) Make TX configuration changes 644 * 4) Set Enable once more 645 */ 646 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG, 647 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) & 648 ~(BIGMAC_TXCFG_ENABLE)); 649 while (hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) & BIGMAC_TXCFG_ENABLE) 650 barrier(); 651 if (full) { 652 hp->happy_flags |= HFLAG_FULL; 653 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG, 654 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) | 655 BIGMAC_TXCFG_FULLDPLX); 656 } else { 657 hp->happy_flags &= ~(HFLAG_FULL); 658 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG, 659 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) & 660 ~(BIGMAC_TXCFG_FULLDPLX)); 661 } 662 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG, 663 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) | 664 BIGMAC_TXCFG_ENABLE); 665 return 0; 666no_response: 667 return 1; 668} 669 670static int happy_meal_init(struct happy_meal *hp); 671 672static int is_lucent_phy(struct happy_meal *hp) 673{ 674 void __iomem *tregs = hp->tcvregs; 675 unsigned short mr2, mr3; 676 int ret = 0; 677 678 mr2 = happy_meal_tcvr_read(hp, tregs, 2); 679 mr3 = happy_meal_tcvr_read(hp, tregs, 3); 680 if ((mr2 & 0xffff) == 0x0180 && 681 ((mr3 & 0xffff) >> 10) == 0x1d) 682 ret = 1; 683 684 return ret; 685} 686 687static void happy_meal_timer(unsigned long data) 688{ 689 struct happy_meal *hp = (struct happy_meal *) data; 690 void __iomem *tregs = hp->tcvregs; 691 int restart_timer = 0; 692 693 spin_lock_irq(&hp->happy_lock); 694 695 hp->timer_ticks++; 696 switch(hp->timer_state) { 697 case arbwait: 698 /* Only allow for 5 ticks, thats 10 seconds and much too 699 * long to wait for arbitration to complete. 700 */ 701 if (hp->timer_ticks >= 10) { 702 /* Enter force mode. */ 703 do_force_mode: 704 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR); 705 printk(KERN_NOTICE "%s: Auto-Negotiation unsuccessful, trying force link mode\n", 706 hp->dev->name); 707 hp->sw_bmcr = BMCR_SPEED100; 708 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr); 709 710 if (!is_lucent_phy(hp)) { 711 /* OK, seems we need do disable the transceiver for the first 712 * tick to make sure we get an accurate link state at the 713 * second tick. 714 */ 715 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG); 716 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB); 717 happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG, hp->sw_csconfig); 718 } 719 hp->timer_state = ltrywait; 720 hp->timer_ticks = 0; 721 restart_timer = 1; 722 } else { 723 /* Anything interesting happen? */ 724 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR); 725 if (hp->sw_bmsr & BMSR_ANEGCOMPLETE) { 726 int ret; 727 728 /* Just what we've been waiting for... */ 729 ret = set_happy_link_modes(hp, tregs); 730 if (ret) { 731 goto do_force_mode; 732 } 733 734 /* Success, at least so far, advance our state engine. */ 735 hp->timer_state = lupwait; 736 restart_timer = 1; 737 } else { 738 restart_timer = 1; 739 } 740 } 741 break; 742 743 case lupwait: 744 /* Auto negotiation was successful and we are awaiting a 745 * link up status. I have decided to let this timer run 746 * forever until some sort of error is signalled, reporting 747 * a message to the user at 10 second intervals. 748 */ 749 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR); 750 if (hp->sw_bmsr & BMSR_LSTATUS) { 751 /* Wheee, it's up, display the link mode in use and put 752 * the timer to sleep. 753 */ 754 display_link_mode(hp, tregs); 755 hp->timer_state = asleep; 756 restart_timer = 0; 757 } else { 758 if (hp->timer_ticks >= 10) { 759 printk(KERN_NOTICE "%s: Auto negotiation successful, link still " 760 "not completely up.\n", hp->dev->name); 761 hp->timer_ticks = 0; 762 restart_timer = 1; 763 } else { 764 restart_timer = 1; 765 } 766 } 767 break; 768 769 case ltrywait: 770 /* Making the timeout here too long can make it take 771 * annoyingly long to attempt all of the link mode 772 * permutations, but then again this is essentially 773 * error recovery code for the most part. 774 */ 775 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR); 776 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG); 777 if (hp->timer_ticks == 1) { 778 if (!is_lucent_phy(hp)) { 779 /* Re-enable transceiver, we'll re-enable the transceiver next 780 * tick, then check link state on the following tick. 781 */ 782 hp->sw_csconfig |= CSCONFIG_TCVDISAB; 783 happy_meal_tcvr_write(hp, tregs, 784 DP83840_CSCONFIG, hp->sw_csconfig); 785 } 786 restart_timer = 1; 787 break; 788 } 789 if (hp->timer_ticks == 2) { 790 if (!is_lucent_phy(hp)) { 791 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB); 792 happy_meal_tcvr_write(hp, tregs, 793 DP83840_CSCONFIG, hp->sw_csconfig); 794 } 795 restart_timer = 1; 796 break; 797 } 798 if (hp->sw_bmsr & BMSR_LSTATUS) { 799 /* Force mode selection success. */ 800 display_forced_link_mode(hp, tregs); 801 set_happy_link_modes(hp, tregs); 802 hp->timer_state = asleep; 803 restart_timer = 0; 804 } else { 805 if (hp->timer_ticks >= 4) { /* 6 seconds or so... */ 806 int ret; 807 808 ret = try_next_permutation(hp, tregs); 809 if (ret == -1) { 810 /* Aieee, tried them all, reset the 811 * chip and try all over again. 812 */ 813 814 /* Let the user know... */ 815 printk(KERN_NOTICE "%s: Link down, cable problem?\n", 816 hp->dev->name); 817 818 ret = happy_meal_init(hp); 819 if (ret) { 820 /* ho hum... */ 821 printk(KERN_ERR "%s: Error, cannot re-init the " 822 "Happy Meal.\n", hp->dev->name); 823 } 824 goto out; 825 } 826 if (!is_lucent_phy(hp)) { 827 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, 828 DP83840_CSCONFIG); 829 hp->sw_csconfig |= CSCONFIG_TCVDISAB; 830 happy_meal_tcvr_write(hp, tregs, 831 DP83840_CSCONFIG, hp->sw_csconfig); 832 } 833 hp->timer_ticks = 0; 834 restart_timer = 1; 835 } else { 836 restart_timer = 1; 837 } 838 } 839 break; 840 841 case asleep: 842 default: 843 /* Can't happens.... */ 844 printk(KERN_ERR "%s: Aieee, link timer is asleep but we got one anyways!\n", 845 hp->dev->name); 846 restart_timer = 0; 847 hp->timer_ticks = 0; 848 hp->timer_state = asleep; /* foo on you */ 849 break; 850 }; 851 852 if (restart_timer) { 853 hp->happy_timer.expires = jiffies + ((12 * HZ)/10); /* 1.2 sec. */ 854 add_timer(&hp->happy_timer); 855 } 856 857out: 858 spin_unlock_irq(&hp->happy_lock); 859} 860 861#define TX_RESET_TRIES 32 862#define RX_RESET_TRIES 32 863 864/* hp->happy_lock must be held */ 865static void happy_meal_tx_reset(struct happy_meal *hp, void __iomem *bregs) 866{ 867 int tries = TX_RESET_TRIES; 868 869 HMD(("happy_meal_tx_reset: reset, ")); 870 871 /* Would you like to try our SMCC Delux? */ 872 hme_write32(hp, bregs + BMAC_TXSWRESET, 0); 873 while ((hme_read32(hp, bregs + BMAC_TXSWRESET) & 1) && --tries) 874 udelay(20); 875 876 /* Lettuce, tomato, buggy hardware (no extra charge)? */ 877 if (!tries) 878 printk(KERN_ERR "happy meal: Transceiver BigMac ATTACK!"); 879 880 /* Take care. */ 881 HMD(("done\n")); 882} 883 884/* hp->happy_lock must be held */ 885static void happy_meal_rx_reset(struct happy_meal *hp, void __iomem *bregs) 886{ 887 int tries = RX_RESET_TRIES; 888 889 HMD(("happy_meal_rx_reset: reset, ")); 890 891 /* We have a special on GNU/Viking hardware bugs today. */ 892 hme_write32(hp, bregs + BMAC_RXSWRESET, 0); 893 while ((hme_read32(hp, bregs + BMAC_RXSWRESET) & 1) && --tries) 894 udelay(20); 895 896 /* Will that be all? */ 897 if (!tries) 898 printk(KERN_ERR "happy meal: Receiver BigMac ATTACK!"); 899 900 /* Don't forget your vik_1137125_wa. Have a nice day. */ 901 HMD(("done\n")); 902} 903 904#define STOP_TRIES 16 905 906/* hp->happy_lock must be held */ 907static void happy_meal_stop(struct happy_meal *hp, void __iomem *gregs) 908{ 909 int tries = STOP_TRIES; 910 911 HMD(("happy_meal_stop: reset, ")); 912 913 /* We're consolidating our STB products, it's your lucky day. */ 914 hme_write32(hp, gregs + GREG_SWRESET, GREG_RESET_ALL); 915 while (hme_read32(hp, gregs + GREG_SWRESET) && --tries) 916 udelay(20); 917 918 /* Come back next week when we are "Sun Microelectronics". */ 919 if (!tries) 920 printk(KERN_ERR "happy meal: Fry guys."); 921 922 /* Remember: "Different name, same old buggy as shit hardware." */ 923 HMD(("done\n")); 924} 925 926/* hp->happy_lock must be held */ 927static void happy_meal_get_counters(struct happy_meal *hp, void __iomem *bregs) 928{ 929 struct net_device_stats *stats = &hp->net_stats; 930 931 stats->rx_crc_errors += hme_read32(hp, bregs + BMAC_RCRCECTR); 932 hme_write32(hp, bregs + BMAC_RCRCECTR, 0); 933 934 stats->rx_frame_errors += hme_read32(hp, bregs + BMAC_UNALECTR); 935 hme_write32(hp, bregs + BMAC_UNALECTR, 0); 936 937 stats->rx_length_errors += hme_read32(hp, bregs + BMAC_GLECTR); 938 hme_write32(hp, bregs + BMAC_GLECTR, 0); 939 940 stats->tx_aborted_errors += hme_read32(hp, bregs + BMAC_EXCTR); 941 942 stats->collisions += 943 (hme_read32(hp, bregs + BMAC_EXCTR) + 944 hme_read32(hp, bregs + BMAC_LTCTR)); 945 hme_write32(hp, bregs + BMAC_EXCTR, 0); 946 hme_write32(hp, bregs + BMAC_LTCTR, 0); 947} 948 949/* hp->happy_lock must be held */ 950static void happy_meal_poll_stop(struct happy_meal *hp, void __iomem *tregs) 951{ 952 ASD(("happy_meal_poll_stop: ")); 953 954 /* If polling disabled or not polling already, nothing to do. */ 955 if ((hp->happy_flags & (HFLAG_POLLENABLE | HFLAG_POLL)) != 956 (HFLAG_POLLENABLE | HFLAG_POLL)) { 957 HMD(("not polling, return\n")); 958 return; 959 } 960 961 /* Shut up the MIF. */ 962 ASD(("were polling, mif ints off, ")); 963 hme_write32(hp, tregs + TCVR_IMASK, 0xffff); 964 965 /* Turn off polling. */ 966 ASD(("polling off, ")); 967 hme_write32(hp, tregs + TCVR_CFG, 968 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_PENABLE)); 969 970 /* We are no longer polling. */ 971 hp->happy_flags &= ~(HFLAG_POLL); 972 973 /* Let the bits set. */ 974 udelay(200); 975 ASD(("done\n")); 976} 977 978/* Only Sun can take such nice parts and fuck up the programming interface 979 * like this. Good job guys... 980 */ 981#define TCVR_RESET_TRIES 16 /* It should reset quickly */ 982#define TCVR_UNISOLATE_TRIES 32 /* Dis-isolation can take longer. */ 983 984/* hp->happy_lock must be held */ 985static int happy_meal_tcvr_reset(struct happy_meal *hp, void __iomem *tregs) 986{ 987 u32 tconfig; 988 int result, tries = TCVR_RESET_TRIES; 989 990 tconfig = hme_read32(hp, tregs + TCVR_CFG); 991 ASD(("happy_meal_tcvr_reset: tcfg<%08lx> ", tconfig)); 992 if (hp->tcvr_type == external) { 993 ASD(("external<")); 994 hme_write32(hp, tregs + TCVR_CFG, tconfig & ~(TCV_CFG_PSELECT)); 995 hp->tcvr_type = internal; 996 hp->paddr = TCV_PADDR_ITX; 997 ASD(("ISOLATE,")); 998 happy_meal_tcvr_write(hp, tregs, MII_BMCR, 999 (BMCR_LOOPBACK|BMCR_PDOWN|BMCR_ISOLATE)); 1000 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR); 1001 if (result == TCVR_FAILURE) { 1002 ASD(("phyread_fail>\n")); 1003 return -1; 1004 } 1005 ASD(("phyread_ok,PSELECT>")); 1006 hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT); 1007 hp->tcvr_type = external; 1008 hp->paddr = TCV_PADDR_ETX; 1009 } else { 1010 if (tconfig & TCV_CFG_MDIO1) { 1011 ASD(("internal<PSELECT,")); 1012 hme_write32(hp, tregs + TCVR_CFG, (tconfig | TCV_CFG_PSELECT)); 1013 ASD(("ISOLATE,")); 1014 happy_meal_tcvr_write(hp, tregs, MII_BMCR, 1015 (BMCR_LOOPBACK|BMCR_PDOWN|BMCR_ISOLATE)); 1016 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR); 1017 if (result == TCVR_FAILURE) { 1018 ASD(("phyread_fail>\n")); 1019 return -1; 1020 } 1021 ASD(("phyread_ok,~PSELECT>")); 1022 hme_write32(hp, tregs + TCVR_CFG, (tconfig & ~(TCV_CFG_PSELECT))); 1023 hp->tcvr_type = internal; 1024 hp->paddr = TCV_PADDR_ITX; 1025 } 1026 } 1027 1028 ASD(("BMCR_RESET ")); 1029 happy_meal_tcvr_write(hp, tregs, MII_BMCR, BMCR_RESET); 1030 1031 while (--tries) { 1032 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR); 1033 if (result == TCVR_FAILURE) 1034 return -1; 1035 hp->sw_bmcr = result; 1036 if (!(result & BMCR_RESET)) 1037 break; 1038 udelay(20); 1039 } 1040 if (!tries) { 1041 ASD(("BMCR RESET FAILED!\n")); 1042 return -1; 1043 } 1044 ASD(("RESET_OK\n")); 1045 1046 /* Get fresh copies of the PHY registers. */ 1047 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR); 1048 hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID1); 1049 hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID2); 1050 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE); 1051 1052 ASD(("UNISOLATE")); 1053 hp->sw_bmcr &= ~(BMCR_ISOLATE); 1054 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr); 1055 1056 tries = TCVR_UNISOLATE_TRIES; 1057 while (--tries) { 1058 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR); 1059 if (result == TCVR_FAILURE) 1060 return -1; 1061 if (!(result & BMCR_ISOLATE)) 1062 break; 1063 udelay(20); 1064 } 1065 if (!tries) { 1066 ASD((" FAILED!\n")); 1067 return -1; 1068 } 1069 ASD((" SUCCESS and CSCONFIG_DFBYPASS\n")); 1070 if (!is_lucent_phy(hp)) { 1071 result = happy_meal_tcvr_read(hp, tregs, 1072 DP83840_CSCONFIG); 1073 happy_meal_tcvr_write(hp, tregs, 1074 DP83840_CSCONFIG, (result | CSCONFIG_DFBYPASS)); 1075 } 1076 return 0; 1077} 1078 1079/* Figure out whether we have an internal or external transceiver. 1080 * 1081 * hp->happy_lock must be held 1082 */ 1083static void happy_meal_transceiver_check(struct happy_meal *hp, void __iomem *tregs) 1084{ 1085 unsigned long tconfig = hme_read32(hp, tregs + TCVR_CFG); 1086 1087 ASD(("happy_meal_transceiver_check: tcfg=%08lx ", tconfig)); 1088 if (hp->happy_flags & HFLAG_POLL) { 1089 /* If we are polling, we must stop to get the transceiver type. */ 1090 ASD(("<polling> ")); 1091 if (hp->tcvr_type == internal) { 1092 if (tconfig & TCV_CFG_MDIO1) { 1093 ASD(("<internal> <poll stop> ")); 1094 happy_meal_poll_stop(hp, tregs); 1095 hp->paddr = TCV_PADDR_ETX; 1096 hp->tcvr_type = external; 1097 ASD(("<external>\n")); 1098 tconfig &= ~(TCV_CFG_PENABLE); 1099 tconfig |= TCV_CFG_PSELECT; 1100 hme_write32(hp, tregs + TCVR_CFG, tconfig); 1101 } 1102 } else { 1103 if (hp->tcvr_type == external) { 1104 ASD(("<external> ")); 1105 if (!(hme_read32(hp, tregs + TCVR_STATUS) >> 16)) { 1106 ASD(("<poll stop> ")); 1107 happy_meal_poll_stop(hp, tregs); 1108 hp->paddr = TCV_PADDR_ITX; 1109 hp->tcvr_type = internal; 1110 ASD(("<internal>\n")); 1111 hme_write32(hp, tregs + TCVR_CFG, 1112 hme_read32(hp, tregs + TCVR_CFG) & 1113 ~(TCV_CFG_PSELECT)); 1114 } 1115 ASD(("\n")); 1116 } else { 1117 ASD(("<none>\n")); 1118 } 1119 } 1120 } else { 1121 u32 reread = hme_read32(hp, tregs + TCVR_CFG); 1122 1123 /* Else we can just work off of the MDIO bits. */ 1124 ASD(("<not polling> ")); 1125 if (reread & TCV_CFG_MDIO1) { 1126 hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT); 1127 hp->paddr = TCV_PADDR_ETX; 1128 hp->tcvr_type = external; 1129 ASD(("<external>\n")); 1130 } else { 1131 if (reread & TCV_CFG_MDIO0) { 1132 hme_write32(hp, tregs + TCVR_CFG, 1133 tconfig & ~(TCV_CFG_PSELECT)); 1134 hp->paddr = TCV_PADDR_ITX; 1135 hp->tcvr_type = internal; 1136 ASD(("<internal>\n")); 1137 } else { 1138 printk(KERN_ERR "happy meal: Transceiver and a coke please."); 1139 hp->tcvr_type = none; /* Grrr... */ 1140 ASD(("<none>\n")); 1141 } 1142 } 1143 } 1144} 1145 1146/* The receive ring buffers are a bit tricky to get right. Here goes... 1147 * 1148 * The buffers we dma into must be 64 byte aligned. So we use a special 1149 * alloc_skb() routine for the happy meal to allocate 64 bytes more than 1150 * we really need. 1151 * 1152 * We use skb_reserve() to align the data block we get in the skb. We 1153 * also program the etxregs->cfg register to use an offset of 2. This 1154 * imperical constant plus the ethernet header size will always leave 1155 * us with a nicely aligned ip header once we pass things up to the 1156 * protocol layers. 1157 * 1158 * The numbers work out to: 1159 * 1160 * Max ethernet frame size 1518 1161 * Ethernet header size 14 1162 * Happy Meal base offset 2 1163 * 1164 * Say a skb data area is at 0xf001b010, and its size alloced is 1165 * (ETH_FRAME_LEN + 64 + 2) = (1514 + 64 + 2) = 1580 bytes. 1166 * 1167 * First our alloc_skb() routine aligns the data base to a 64 byte 1168 * boundary. We now have 0xf001b040 as our skb data address. We 1169 * plug this into the receive descriptor address. 1170 * 1171 * Next, we skb_reserve() 2 bytes to account for the Happy Meal offset. 1172 * So now the data we will end up looking at starts at 0xf001b042. When 1173 * the packet arrives, we will check out the size received and subtract 1174 * this from the skb->length. Then we just pass the packet up to the 1175 * protocols as is, and allocate a new skb to replace this slot we have 1176 * just received from. 1177 * 1178 * The ethernet layer will strip the ether header from the front of the 1179 * skb we just sent to it, this leaves us with the ip header sitting 1180 * nicely aligned at 0xf001b050. Also, for tcp and udp packets the 1181 * Happy Meal has even checksummed the tcp/udp data for us. The 16 1182 * bit checksum is obtained from the low bits of the receive descriptor 1183 * flags, thus: 1184 * 1185 * skb->csum = rxd->rx_flags & 0xffff; 1186 * skb->ip_summed = CHECKSUM_COMPLETE; 1187 * 1188 * before sending off the skb to the protocols, and we are good as gold. 1189 */ 1190static void happy_meal_clean_rings(struct happy_meal *hp) 1191{ 1192 int i; 1193 1194 for (i = 0; i < RX_RING_SIZE; i++) { 1195 if (hp->rx_skbs[i] != NULL) { 1196 struct sk_buff *skb = hp->rx_skbs[i]; 1197 struct happy_meal_rxd *rxd; 1198 u32 dma_addr; 1199 1200 rxd = &hp->happy_block->happy_meal_rxd[i]; 1201 dma_addr = hme_read_desc32(hp, &rxd->rx_addr); 1202 hme_dma_unmap(hp, dma_addr, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE); 1203 dev_kfree_skb_any(skb); 1204 hp->rx_skbs[i] = NULL; 1205 } 1206 } 1207 1208 for (i = 0; i < TX_RING_SIZE; i++) { 1209 if (hp->tx_skbs[i] != NULL) { 1210 struct sk_buff *skb = hp->tx_skbs[i]; 1211 struct happy_meal_txd *txd; 1212 u32 dma_addr; 1213 int frag; 1214 1215 hp->tx_skbs[i] = NULL; 1216 1217 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) { 1218 txd = &hp->happy_block->happy_meal_txd[i]; 1219 dma_addr = hme_read_desc32(hp, &txd->tx_addr); 1220 hme_dma_unmap(hp, dma_addr, 1221 (hme_read_desc32(hp, &txd->tx_flags) 1222 & TXFLAG_SIZE), 1223 DMA_TODEVICE); 1224 1225 if (frag != skb_shinfo(skb)->nr_frags) 1226 i++; 1227 } 1228 1229 dev_kfree_skb_any(skb); 1230 } 1231 } 1232} 1233 1234/* hp->happy_lock must be held */ 1235static void happy_meal_init_rings(struct happy_meal *hp) 1236{ 1237 struct hmeal_init_block *hb = hp->happy_block; 1238 struct net_device *dev = hp->dev; 1239 int i; 1240 1241 HMD(("happy_meal_init_rings: counters to zero, ")); 1242 hp->rx_new = hp->rx_old = hp->tx_new = hp->tx_old = 0; 1243 1244 /* Free any skippy bufs left around in the rings. */ 1245 HMD(("clean, ")); 1246 happy_meal_clean_rings(hp); 1247 1248 /* Now get new skippy bufs for the receive ring. */ 1249 HMD(("init rxring, ")); 1250 for (i = 0; i < RX_RING_SIZE; i++) { 1251 struct sk_buff *skb; 1252 1253 skb = happy_meal_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC); 1254 if (!skb) { 1255 hme_write_rxd(hp, &hb->happy_meal_rxd[i], 0, 0); 1256 continue; 1257 } 1258 hp->rx_skbs[i] = skb; 1259 skb->dev = dev; 1260 1261 /* Because we reserve afterwards. */ 1262 skb_put(skb, (ETH_FRAME_LEN + RX_OFFSET)); 1263 hme_write_rxd(hp, &hb->happy_meal_rxd[i], 1264 (RXFLAG_OWN | ((RX_BUF_ALLOC_SIZE - RX_OFFSET) << 16)), 1265 hme_dma_map(hp, skb->data, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE)); 1266 skb_reserve(skb, RX_OFFSET); 1267 } 1268 1269 HMD(("init txring, ")); 1270 for (i = 0; i < TX_RING_SIZE; i++) 1271 hme_write_txd(hp, &hb->happy_meal_txd[i], 0, 0); 1272 1273 HMD(("done\n")); 1274} 1275 1276/* hp->happy_lock must be held */ 1277static void happy_meal_begin_auto_negotiation(struct happy_meal *hp, 1278 void __iomem *tregs, 1279 struct ethtool_cmd *ep) 1280{ 1281 int timeout; 1282 1283 /* Read all of the registers we are interested in now. */ 1284 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR); 1285 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR); 1286 hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID1); 1287 hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID2); 1288 1289 1290 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE); 1291 if (ep == NULL || ep->autoneg == AUTONEG_ENABLE) { 1292 /* Advertise everything we can support. */ 1293 if (hp->sw_bmsr & BMSR_10HALF) 1294 hp->sw_advertise |= (ADVERTISE_10HALF); 1295 else 1296 hp->sw_advertise &= ~(ADVERTISE_10HALF); 1297 1298 if (hp->sw_bmsr & BMSR_10FULL) 1299 hp->sw_advertise |= (ADVERTISE_10FULL); 1300 else 1301 hp->sw_advertise &= ~(ADVERTISE_10FULL); 1302 if (hp->sw_bmsr & BMSR_100HALF) 1303 hp->sw_advertise |= (ADVERTISE_100HALF); 1304 else 1305 hp->sw_advertise &= ~(ADVERTISE_100HALF); 1306 if (hp->sw_bmsr & BMSR_100FULL) 1307 hp->sw_advertise |= (ADVERTISE_100FULL); 1308 else 1309 hp->sw_advertise &= ~(ADVERTISE_100FULL); 1310 happy_meal_tcvr_write(hp, tregs, MII_ADVERTISE, hp->sw_advertise); 1311 1312 1313#ifdef AUTO_SWITCH_DEBUG 1314 ASD(("%s: Advertising [ ", hp->dev->name)); 1315 if (hp->sw_advertise & ADVERTISE_10HALF) 1316 ASD(("10H ")); 1317 if (hp->sw_advertise & ADVERTISE_10FULL) 1318 ASD(("10F ")); 1319 if (hp->sw_advertise & ADVERTISE_100HALF) 1320 ASD(("100H ")); 1321 if (hp->sw_advertise & ADVERTISE_100FULL) 1322 ASD(("100F ")); 1323#endif 1324 1325 /* Enable Auto-Negotiation, this is usually on already... */ 1326 hp->sw_bmcr |= BMCR_ANENABLE; 1327 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr); 1328 1329 /* Restart it to make sure it is going. */ 1330 hp->sw_bmcr |= BMCR_ANRESTART; 1331 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr); 1332 1333 /* BMCR_ANRESTART self clears when the process has begun. */ 1334 1335 timeout = 64; /* More than enough. */ 1336 while (--timeout) { 1337 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR); 1338 if (!(hp->sw_bmcr & BMCR_ANRESTART)) 1339 break; /* got it. */ 1340 udelay(10); 1341 } 1342 if (!timeout) { 1343 printk(KERN_ERR "%s: Happy Meal would not start auto negotiation " 1344 "BMCR=0x%04x\n", hp->dev->name, hp->sw_bmcr); 1345 printk(KERN_NOTICE "%s: Performing force link detection.\n", 1346 hp->dev->name); 1347 goto force_link; 1348 } else { 1349 hp->timer_state = arbwait; 1350 } 1351 } else { 1352force_link: 1353 /* Force the link up, trying first a particular mode. 1354 * Either we are here at the request of ethtool or 1355 * because the Happy Meal would not start to autoneg. 1356 */ 1357 1358 /* Disable auto-negotiation in BMCR, enable the duplex and 1359 * speed setting, init the timer state machine, and fire it off. 1360 */ 1361 if (ep == NULL || ep->autoneg == AUTONEG_ENABLE) { 1362 hp->sw_bmcr = BMCR_SPEED100; 1363 } else { 1364 if (ep->speed == SPEED_100) 1365 hp->sw_bmcr = BMCR_SPEED100; 1366 else 1367 hp->sw_bmcr = 0; 1368 if (ep->duplex == DUPLEX_FULL) 1369 hp->sw_bmcr |= BMCR_FULLDPLX; 1370 } 1371 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr); 1372 1373 if (!is_lucent_phy(hp)) { 1374 /* OK, seems we need do disable the transceiver for the first 1375 * tick to make sure we get an accurate link state at the 1376 * second tick. 1377 */ 1378 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, 1379 DP83840_CSCONFIG); 1380 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB); 1381 happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG, 1382 hp->sw_csconfig); 1383 } 1384 hp->timer_state = ltrywait; 1385 } 1386 1387 hp->timer_ticks = 0; 1388 hp->happy_timer.expires = jiffies + (12 * HZ)/10; /* 1.2 sec. */ 1389 hp->happy_timer.data = (unsigned long) hp; 1390 hp->happy_timer.function = &happy_meal_timer; 1391 add_timer(&hp->happy_timer); 1392} 1393 1394/* hp->happy_lock must be held */ 1395static int happy_meal_init(struct happy_meal *hp) 1396{ 1397 void __iomem *gregs = hp->gregs; 1398 void __iomem *etxregs = hp->etxregs; 1399 void __iomem *erxregs = hp->erxregs; 1400 void __iomem *bregs = hp->bigmacregs; 1401 void __iomem *tregs = hp->tcvregs; 1402 u32 regtmp, rxcfg; 1403 unsigned char *e = &hp->dev->dev_addr[0]; 1404 1405 /* If auto-negotiation timer is running, kill it. */ 1406 del_timer(&hp->happy_timer); 1407 1408 HMD(("happy_meal_init: happy_flags[%08x] ", 1409 hp->happy_flags)); 1410 if (!(hp->happy_flags & HFLAG_INIT)) { 1411 HMD(("set HFLAG_INIT, ")); 1412 hp->happy_flags |= HFLAG_INIT; 1413 happy_meal_get_counters(hp, bregs); 1414 } 1415 1416 /* Stop polling. */ 1417 HMD(("to happy_meal_poll_stop\n")); 1418 happy_meal_poll_stop(hp, tregs); 1419 1420 /* Stop transmitter and receiver. */ 1421 HMD(("happy_meal_init: to happy_meal_stop\n")); 1422 happy_meal_stop(hp, gregs); 1423 1424 /* Alloc and reset the tx/rx descriptor chains. */ 1425 HMD(("happy_meal_init: to happy_meal_init_rings\n")); 1426 happy_meal_init_rings(hp); 1427 1428 /* Shut up the MIF. */ 1429 HMD(("happy_meal_init: Disable all MIF irqs (old[%08x]), ", 1430 hme_read32(hp, tregs + TCVR_IMASK))); 1431 hme_write32(hp, tregs + TCVR_IMASK, 0xffff); 1432 1433 /* See if we can enable the MIF frame on this card to speak to the DP83840. */ 1434 if (hp->happy_flags & HFLAG_FENABLE) { 1435 HMD(("use frame old[%08x], ", 1436 hme_read32(hp, tregs + TCVR_CFG))); 1437 hme_write32(hp, tregs + TCVR_CFG, 1438 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE)); 1439 } else { 1440 HMD(("use bitbang old[%08x], ", 1441 hme_read32(hp, tregs + TCVR_CFG))); 1442 hme_write32(hp, tregs + TCVR_CFG, 1443 hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE); 1444 } 1445 1446 /* Check the state of the transceiver. */ 1447 HMD(("to happy_meal_transceiver_check\n")); 1448 happy_meal_transceiver_check(hp, tregs); 1449 1450 /* Put the Big Mac into a sane state. */ 1451 HMD(("happy_meal_init: ")); 1452 switch(hp->tcvr_type) { 1453 case none: 1454 /* Cannot operate if we don't know the transceiver type! */ 1455 HMD(("AAIEEE no transceiver type, EAGAIN")); 1456 return -EAGAIN; 1457 1458 case internal: 1459 /* Using the MII buffers. */ 1460 HMD(("internal, using MII, ")); 1461 hme_write32(hp, bregs + BMAC_XIFCFG, 0); 1462 break; 1463 1464 case external: 1465 /* Not using the MII, disable it. */ 1466 HMD(("external, disable MII, ")); 1467 hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB); 1468 break; 1469 }; 1470 1471 if (happy_meal_tcvr_reset(hp, tregs)) 1472 return -EAGAIN; 1473 1474 /* Reset the Happy Meal Big Mac transceiver and the receiver. */ 1475 HMD(("tx/rx reset, ")); 1476 happy_meal_tx_reset(hp, bregs); 1477 happy_meal_rx_reset(hp, bregs); 1478 1479 /* Set jam size and inter-packet gaps to reasonable defaults. */ 1480 HMD(("jsize/ipg1/ipg2, ")); 1481 hme_write32(hp, bregs + BMAC_JSIZE, DEFAULT_JAMSIZE); 1482 hme_write32(hp, bregs + BMAC_IGAP1, DEFAULT_IPG1); 1483 hme_write32(hp, bregs + BMAC_IGAP2, DEFAULT_IPG2); 1484 1485 /* Load up the MAC address and random seed. */ 1486 HMD(("rseed/macaddr, ")); 1487 1488 /* The docs recommend to use the 10LSB of our MAC here. */ 1489 hme_write32(hp, bregs + BMAC_RSEED, ((e[5] | e[4]<<8)&0x3ff)); 1490 1491 hme_write32(hp, bregs + BMAC_MACADDR2, ((e[4] << 8) | e[5])); 1492 hme_write32(hp, bregs + BMAC_MACADDR1, ((e[2] << 8) | e[3])); 1493 hme_write32(hp, bregs + BMAC_MACADDR0, ((e[0] << 8) | e[1])); 1494 1495 HMD(("htable, ")); 1496 if ((hp->dev->flags & IFF_ALLMULTI) || 1497 (hp->dev->mc_count > 64)) { 1498 hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff); 1499 hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff); 1500 hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff); 1501 hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff); 1502 } else if ((hp->dev->flags & IFF_PROMISC) == 0) { 1503 u16 hash_table[4]; 1504 struct dev_mc_list *dmi = hp->dev->mc_list; 1505 char *addrs; 1506 int i; 1507 u32 crc; 1508 1509 for (i = 0; i < 4; i++) 1510 hash_table[i] = 0; 1511 1512 for (i = 0; i < hp->dev->mc_count; i++) { 1513 addrs = dmi->dmi_addr; 1514 dmi = dmi->next; 1515 1516 if (!(*addrs & 1)) 1517 continue; 1518 1519 crc = ether_crc_le(6, addrs); 1520 crc >>= 26; 1521 hash_table[crc >> 4] |= 1 << (crc & 0xf); 1522 } 1523 hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]); 1524 hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]); 1525 hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]); 1526 hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]); 1527 } else { 1528 hme_write32(hp, bregs + BMAC_HTABLE3, 0); 1529 hme_write32(hp, bregs + BMAC_HTABLE2, 0); 1530 hme_write32(hp, bregs + BMAC_HTABLE1, 0); 1531 hme_write32(hp, bregs + BMAC_HTABLE0, 0); 1532 } 1533 1534 /* Set the RX and TX ring ptrs. */ 1535 HMD(("ring ptrs rxr[%08x] txr[%08x]\n", 1536 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)), 1537 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_txd, 0)))); 1538 hme_write32(hp, erxregs + ERX_RING, 1539 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0))); 1540 hme_write32(hp, etxregs + ETX_RING, 1541 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_txd, 0))); 1542 1543 /* Parity issues in the ERX unit of some HME revisions can cause some 1544 * registers to not be written unless their parity is even. Detect such 1545 * lost writes and simply rewrite with a low bit set (which will be ignored 1546 * since the rxring needs to be 2K aligned). 1547 */ 1548 if (hme_read32(hp, erxregs + ERX_RING) != 1549 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0))) 1550 hme_write32(hp, erxregs + ERX_RING, 1551 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)) 1552 | 0x4); 1553 1554 /* Set the supported burst sizes. */ 1555 HMD(("happy_meal_init: old[%08x] bursts<", 1556 hme_read32(hp, gregs + GREG_CFG))); 1557 1558#ifndef CONFIG_SPARC 1559 /* It is always PCI and can handle 64byte bursts. */ 1560 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST64); 1561#else 1562 if ((hp->happy_bursts & DMA_BURST64) && 1563 ((hp->happy_flags & HFLAG_PCI) != 0 1564#ifdef CONFIG_SBUS 1565 || sbus_can_burst64(hp->happy_dev) 1566#endif 1567 || 0)) { 1568 u32 gcfg = GREG_CFG_BURST64; 1569 1570 /* I have no idea if I should set the extended 1571 * transfer mode bit for Cheerio, so for now I 1572 * do not. -DaveM 1573 */ 1574#ifdef CONFIG_SBUS 1575 if ((hp->happy_flags & HFLAG_PCI) == 0 && 1576 sbus_can_dma_64bit(hp->happy_dev)) { 1577 sbus_set_sbus64(hp->happy_dev, 1578 hp->happy_bursts); 1579 gcfg |= GREG_CFG_64BIT; 1580 } 1581#endif 1582 1583 HMD(("64>")); 1584 hme_write32(hp, gregs + GREG_CFG, gcfg); 1585 } else if (hp->happy_bursts & DMA_BURST32) { 1586 HMD(("32>")); 1587 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST32); 1588 } else if (hp->happy_bursts & DMA_BURST16) { 1589 HMD(("16>")); 1590 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST16); 1591 } else { 1592 HMD(("XXX>")); 1593 hme_write32(hp, gregs + GREG_CFG, 0); 1594 } 1595#endif /* CONFIG_SPARC */ 1596 1597 /* Turn off interrupts we do not want to hear. */ 1598 HMD((", enable global interrupts, ")); 1599 hme_write32(hp, gregs + GREG_IMASK, 1600 (GREG_IMASK_GOTFRAME | GREG_IMASK_RCNTEXP | 1601 GREG_IMASK_SENTFRAME | GREG_IMASK_TXPERR)); 1602 1603 /* Set the transmit ring buffer size. */ 1604 HMD(("tx rsize=%d oreg[%08x], ", (int)TX_RING_SIZE, 1605 hme_read32(hp, etxregs + ETX_RSIZE))); 1606 hme_write32(hp, etxregs + ETX_RSIZE, (TX_RING_SIZE >> ETX_RSIZE_SHIFT) - 1); 1607 1608 /* Enable transmitter DVMA. */ 1609 HMD(("tx dma enable old[%08x], ", 1610 hme_read32(hp, etxregs + ETX_CFG))); 1611 hme_write32(hp, etxregs + ETX_CFG, 1612 hme_read32(hp, etxregs + ETX_CFG) | ETX_CFG_DMAENABLE); 1613 1614 /* This chip really rots, for the receiver sometimes when you 1615 * write to its control registers not all the bits get there 1616 * properly. I cannot think of a sane way to provide complete 1617 * coverage for this hardware bug yet. 1618 */ 1619 HMD(("erx regs bug old[%08x]\n", 1620 hme_read32(hp, erxregs + ERX_CFG))); 1621 hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET)); 1622 regtmp = hme_read32(hp, erxregs + ERX_CFG); 1623 hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET)); 1624 if (hme_read32(hp, erxregs + ERX_CFG) != ERX_CFG_DEFAULT(RX_OFFSET)) { 1625 printk(KERN_ERR "happy meal: Eieee, rx config register gets greasy fries.\n"); 1626 printk(KERN_ERR "happy meal: Trying to set %08x, reread gives %08x\n", 1627 ERX_CFG_DEFAULT(RX_OFFSET), regtmp); 1628 } 1629 1630 /* Enable Big Mac hash table filter. */ 1631 HMD(("happy_meal_init: enable hash rx_cfg_old[%08x], ", 1632 hme_read32(hp, bregs + BMAC_RXCFG))); 1633 rxcfg = BIGMAC_RXCFG_HENABLE | BIGMAC_RXCFG_REJME; 1634 if (hp->dev->flags & IFF_PROMISC) 1635 rxcfg |= BIGMAC_RXCFG_PMISC; 1636 hme_write32(hp, bregs + BMAC_RXCFG, rxcfg); 1637 1638 /* Let the bits settle in the chip. */ 1639 udelay(10); 1640 1641 /* Ok, configure the Big Mac transmitter. */ 1642 HMD(("BIGMAC init, ")); 1643 regtmp = 0; 1644 if (hp->happy_flags & HFLAG_FULL) 1645 regtmp |= BIGMAC_TXCFG_FULLDPLX; 1646 1647 /* Don't turn on the "don't give up" bit for now. It could cause hme 1648 * to deadlock with the PHY if a Jabber occurs. 1649 */ 1650 hme_write32(hp, bregs + BMAC_TXCFG, regtmp /*| BIGMAC_TXCFG_DGIVEUP*/); 1651 1652 /* Give up after 16 TX attempts. */ 1653 hme_write32(hp, bregs + BMAC_ALIMIT, 16); 1654 1655 /* Enable the output drivers no matter what. */ 1656 regtmp = BIGMAC_XCFG_ODENABLE; 1657 1658 /* If card can do lance mode, enable it. */ 1659 if (hp->happy_flags & HFLAG_LANCE) 1660 regtmp |= (DEFAULT_IPG0 << 5) | BIGMAC_XCFG_LANCE; 1661 1662 /* Disable the MII buffers if using external transceiver. */ 1663 if (hp->tcvr_type == external) 1664 regtmp |= BIGMAC_XCFG_MIIDISAB; 1665 1666 HMD(("XIF config old[%08x], ", 1667 hme_read32(hp, bregs + BMAC_XIFCFG))); 1668 hme_write32(hp, bregs + BMAC_XIFCFG, regtmp); 1669 1670 /* Start things up. */ 1671 HMD(("tx old[%08x] and rx [%08x] ON!\n", 1672 hme_read32(hp, bregs + BMAC_TXCFG), 1673 hme_read32(hp, bregs + BMAC_RXCFG))); 1674 hme_write32(hp, bregs + BMAC_TXCFG, 1675 hme_read32(hp, bregs + BMAC_TXCFG) | BIGMAC_TXCFG_ENABLE); 1676 hme_write32(hp, bregs + BMAC_RXCFG, 1677 hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_ENABLE); 1678 1679 /* Get the autonegotiation started, and the watch timer ticking. */ 1680 happy_meal_begin_auto_negotiation(hp, tregs, NULL); 1681 1682 /* Success. */ 1683 return 0; 1684} 1685 1686/* hp->happy_lock must be held */ 1687static void happy_meal_set_initial_advertisement(struct happy_meal *hp) 1688{ 1689 void __iomem *tregs = hp->tcvregs; 1690 void __iomem *bregs = hp->bigmacregs; 1691 void __iomem *gregs = hp->gregs; 1692 1693 happy_meal_stop(hp, gregs); 1694 hme_write32(hp, tregs + TCVR_IMASK, 0xffff); 1695 if (hp->happy_flags & HFLAG_FENABLE) 1696 hme_write32(hp, tregs + TCVR_CFG, 1697 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE)); 1698 else 1699 hme_write32(hp, tregs + TCVR_CFG, 1700 hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE); 1701 happy_meal_transceiver_check(hp, tregs); 1702 switch(hp->tcvr_type) { 1703 case none: 1704 return; 1705 case internal: 1706 hme_write32(hp, bregs + BMAC_XIFCFG, 0); 1707 break; 1708 case external: 1709 hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB); 1710 break; 1711 }; 1712 if (happy_meal_tcvr_reset(hp, tregs)) 1713 return; 1714 1715 /* Latch PHY registers as of now. */ 1716 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR); 1717 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE); 1718 1719 /* Advertise everything we can support. */ 1720 if (hp->sw_bmsr & BMSR_10HALF) 1721 hp->sw_advertise |= (ADVERTISE_10HALF); 1722 else 1723 hp->sw_advertise &= ~(ADVERTISE_10HALF); 1724 1725 if (hp->sw_bmsr & BMSR_10FULL) 1726 hp->sw_advertise |= (ADVERTISE_10FULL); 1727 else 1728 hp->sw_advertise &= ~(ADVERTISE_10FULL); 1729 if (hp->sw_bmsr & BMSR_100HALF) 1730 hp->sw_advertise |= (ADVERTISE_100HALF); 1731 else 1732 hp->sw_advertise &= ~(ADVERTISE_100HALF); 1733 if (hp->sw_bmsr & BMSR_100FULL) 1734 hp->sw_advertise |= (ADVERTISE_100FULL); 1735 else 1736 hp->sw_advertise &= ~(ADVERTISE_100FULL); 1737 1738 /* Update the PHY advertisement register. */ 1739 happy_meal_tcvr_write(hp, tregs, MII_ADVERTISE, hp->sw_advertise); 1740} 1741 1742/* Once status is latched (by happy_meal_interrupt) it is cleared by 1743 * the hardware, so we cannot re-read it and get a correct value. 1744 * 1745 * hp->happy_lock must be held 1746 */ 1747static int happy_meal_is_not_so_happy(struct happy_meal *hp, u32 status) 1748{ 1749 int reset = 0; 1750 1751 /* Only print messages for non-counter related interrupts. */ 1752 if (status & (GREG_STAT_STSTERR | GREG_STAT_TFIFO_UND | 1753 GREG_STAT_MAXPKTERR | GREG_STAT_RXERR | 1754 GREG_STAT_RXPERR | GREG_STAT_RXTERR | GREG_STAT_EOPERR | 1755 GREG_STAT_MIFIRQ | GREG_STAT_TXEACK | GREG_STAT_TXLERR | 1756 GREG_STAT_TXPERR | GREG_STAT_TXTERR | GREG_STAT_SLVERR | 1757 GREG_STAT_SLVPERR)) 1758 printk(KERN_ERR "%s: Error interrupt for happy meal, status = %08x\n", 1759 hp->dev->name, status); 1760 1761 if (status & GREG_STAT_RFIFOVF) { 1762 /* Receive FIFO overflow is harmless and the hardware will take 1763 care of it, just some packets are lost. Who cares. */ 1764 printk(KERN_DEBUG "%s: Happy Meal receive FIFO overflow.\n", hp->dev->name); 1765 } 1766 1767 if (status & GREG_STAT_STSTERR) { 1768 /* BigMAC SQE link test failed. */ 1769 printk(KERN_ERR "%s: Happy Meal BigMAC SQE test failed.\n", hp->dev->name); 1770 reset = 1; 1771 } 1772 1773 if (status & GREG_STAT_TFIFO_UND) { 1774 /* Transmit FIFO underrun, again DMA error likely. */ 1775 printk(KERN_ERR "%s: Happy Meal transmitter FIFO underrun, DMA error.\n", 1776 hp->dev->name); 1777 reset = 1; 1778 } 1779 1780 if (status & GREG_STAT_MAXPKTERR) { 1781 /* Driver error, tried to transmit something larger 1782 * than ethernet max mtu. 1783 */ 1784 printk(KERN_ERR "%s: Happy Meal MAX Packet size error.\n", hp->dev->name); 1785 reset = 1; 1786 } 1787 1788 if (status & GREG_STAT_NORXD) { 1789 /* This is harmless, it just means the system is 1790 * quite loaded and the incoming packet rate was 1791 * faster than the interrupt handler could keep up 1792 * with. 1793 */ 1794 printk(KERN_INFO "%s: Happy Meal out of receive " 1795 "descriptors, packet dropped.\n", 1796 hp->dev->name); 1797 } 1798 1799 if (status & (GREG_STAT_RXERR|GREG_STAT_RXPERR|GREG_STAT_RXTERR)) { 1800 /* All sorts of DMA receive errors. */ 1801 printk(KERN_ERR "%s: Happy Meal rx DMA errors [ ", hp->dev->name); 1802 if (status & GREG_STAT_RXERR) 1803 printk("GenericError "); 1804 if (status & GREG_STAT_RXPERR) 1805 printk("ParityError "); 1806 if (status & GREG_STAT_RXTERR) 1807 printk("RxTagBotch "); 1808 printk("]\n"); 1809 reset = 1; 1810 } 1811 1812 if (status & GREG_STAT_EOPERR) { 1813 /* Driver bug, didn't set EOP bit in tx descriptor given 1814 * to the happy meal. 1815 */ 1816 printk(KERN_ERR "%s: EOP not set in happy meal transmit descriptor!\n", 1817 hp->dev->name); 1818 reset = 1; 1819 } 1820 1821 if (status & GREG_STAT_MIFIRQ) { 1822 /* MIF signalled an interrupt, were we polling it? */ 1823 printk(KERN_ERR "%s: Happy Meal MIF interrupt.\n", hp->dev->name); 1824 } 1825 1826 if (status & 1827 (GREG_STAT_TXEACK|GREG_STAT_TXLERR|GREG_STAT_TXPERR|GREG_STAT_TXTERR)) { 1828 /* All sorts of transmit DMA errors. */ 1829 printk(KERN_ERR "%s: Happy Meal tx DMA errors [ ", hp->dev->name); 1830 if (status & GREG_STAT_TXEACK) 1831 printk("GenericError "); 1832 if (status & GREG_STAT_TXLERR) 1833 printk("LateError "); 1834 if (status & GREG_STAT_TXPERR) 1835 printk("ParityErro "); 1836 if (status & GREG_STAT_TXTERR) 1837 printk("TagBotch "); 1838 printk("]\n"); 1839 reset = 1; 1840 } 1841 1842 if (status & (GREG_STAT_SLVERR|GREG_STAT_SLVPERR)) { 1843 /* Bus or parity error when cpu accessed happy meal registers 1844 * or it's internal FIFO's. Should never see this. 1845 */ 1846 printk(KERN_ERR "%s: Happy Meal register access SBUS slave (%s) error.\n", 1847 hp->dev->name, 1848 (status & GREG_STAT_SLVPERR) ? "parity" : "generic"); 1849 reset = 1; 1850 } 1851 1852 if (reset) { 1853 printk(KERN_NOTICE "%s: Resetting...\n", hp->dev->name); 1854 happy_meal_init(hp); 1855 return 1; 1856 } 1857 return 0; 1858} 1859 1860/* hp->happy_lock must be held */ 1861static void happy_meal_mif_interrupt(struct happy_meal *hp) 1862{ 1863 void __iomem *tregs = hp->tcvregs; 1864 1865 printk(KERN_INFO "%s: Link status change.\n", hp->dev->name); 1866 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR); 1867 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA); 1868 1869 /* Use the fastest transmission protocol possible. */ 1870 if (hp->sw_lpa & LPA_100FULL) { 1871 printk(KERN_INFO "%s: Switching to 100Mbps at full duplex.", hp->dev->name); 1872 hp->sw_bmcr |= (BMCR_FULLDPLX | BMCR_SPEED100); 1873 } else if (hp->sw_lpa & LPA_100HALF) { 1874 printk(KERN_INFO "%s: Switching to 100MBps at half duplex.", hp->dev->name); 1875 hp->sw_bmcr |= BMCR_SPEED100; 1876 } else if (hp->sw_lpa & LPA_10FULL) { 1877 printk(KERN_INFO "%s: Switching to 10MBps at full duplex.", hp->dev->name); 1878 hp->sw_bmcr |= BMCR_FULLDPLX; 1879 } else { 1880 printk(KERN_INFO "%s: Using 10Mbps at half duplex.", hp->dev->name); 1881 } 1882 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr); 1883 1884 /* Finally stop polling and shut up the MIF. */ 1885 happy_meal_poll_stop(hp, tregs); 1886} 1887 1888#ifdef TXDEBUG 1889#define TXD(x) printk x 1890#else 1891#define TXD(x) 1892#endif 1893 1894/* hp->happy_lock must be held */ 1895static void happy_meal_tx(struct happy_meal *hp) 1896{ 1897 struct happy_meal_txd *txbase = &hp->happy_block->happy_meal_txd[0]; 1898 struct happy_meal_txd *this; 1899 struct net_device *dev = hp->dev; 1900 int elem; 1901 1902 elem = hp->tx_old; 1903 TXD(("TX<")); 1904 while (elem != hp->tx_new) { 1905 struct sk_buff *skb; 1906 u32 flags, dma_addr, dma_len; 1907 int frag; 1908 1909 TXD(("[%d]", elem)); 1910 this = &txbase[elem]; 1911 flags = hme_read_desc32(hp, &this->tx_flags); 1912 if (flags & TXFLAG_OWN) 1913 break; 1914 skb = hp->tx_skbs[elem]; 1915 if (skb_shinfo(skb)->nr_frags) { 1916 int last; 1917 1918 last = elem + skb_shinfo(skb)->nr_frags; 1919 last &= (TX_RING_SIZE - 1); 1920 flags = hme_read_desc32(hp, &txbase[last].tx_flags); 1921 if (flags & TXFLAG_OWN) 1922 break; 1923 } 1924 hp->tx_skbs[elem] = NULL; 1925 hp->net_stats.tx_bytes += skb->len; 1926 1927 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) { 1928 dma_addr = hme_read_desc32(hp, &this->tx_addr); 1929 dma_len = hme_read_desc32(hp, &this->tx_flags); 1930 1931 dma_len &= TXFLAG_SIZE; 1932 hme_dma_unmap(hp, dma_addr, dma_len, DMA_TODEVICE); 1933 1934 elem = NEXT_TX(elem); 1935 this = &txbase[elem]; 1936 } 1937 1938 dev_kfree_skb_irq(skb); 1939 hp->net_stats.tx_packets++; 1940 } 1941 hp->tx_old = elem; 1942 TXD((">")); 1943 1944 if (netif_queue_stopped(dev) && 1945 TX_BUFFS_AVAIL(hp) > (MAX_SKB_FRAGS + 1)) 1946 netif_wake_queue(dev); 1947} 1948 1949#ifdef RXDEBUG 1950#define RXD(x) printk x 1951#else 1952#define RXD(x) 1953#endif 1954 1955/* Originally I used to handle the allocation failure by just giving back just 1956 * that one ring buffer to the happy meal. Problem is that usually when that 1957 * condition is triggered, the happy meal expects you to do something reasonable 1958 * with all of the packets it has DMA'd in. So now I just drop the entire 1959 * ring when we cannot get a new skb and give them all back to the happy meal, 1960 * maybe things will be "happier" now. 1961 * 1962 * hp->happy_lock must be held 1963 */ 1964static void happy_meal_rx(struct happy_meal *hp, struct net_device *dev) 1965{ 1966 struct happy_meal_rxd *rxbase = &hp->happy_block->happy_meal_rxd[0]; 1967 struct happy_meal_rxd *this; 1968 int elem = hp->rx_new, drops = 0; 1969 u32 flags; 1970 1971 RXD(("RX<")); 1972 this = &rxbase[elem]; 1973 while (!((flags = hme_read_desc32(hp, &this->rx_flags)) & RXFLAG_OWN)) { 1974 struct sk_buff *skb; 1975 int len = flags >> 16; 1976 u16 csum = flags & RXFLAG_CSUM; 1977 u32 dma_addr = hme_read_desc32(hp, &this->rx_addr); 1978 1979 RXD(("[%d ", elem)); 1980 1981 /* Check for errors. */ 1982 if ((len < ETH_ZLEN) || (flags & RXFLAG_OVERFLOW)) { 1983 RXD(("ERR(%08x)]", flags)); 1984 hp->net_stats.rx_errors++; 1985 if (len < ETH_ZLEN) 1986 hp->net_stats.rx_length_errors++; 1987 if (len & (RXFLAG_OVERFLOW >> 16)) { 1988 hp->net_stats.rx_over_errors++; 1989 hp->net_stats.rx_fifo_errors++; 1990 } 1991 1992 /* Return it to the Happy meal. */ 1993 drop_it: 1994 hp->net_stats.rx_dropped++; 1995 hme_write_rxd(hp, this, 1996 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)), 1997 dma_addr); 1998 goto next; 1999 } 2000 skb = hp->rx_skbs[elem]; 2001 if (len > RX_COPY_THRESHOLD) { 2002 struct sk_buff *new_skb; 2003 2004 /* Now refill the entry, if we can. */ 2005 new_skb = happy_meal_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC); 2006 if (new_skb == NULL) { 2007 drops++; 2008 goto drop_it; 2009 } 2010 hme_dma_unmap(hp, dma_addr, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE); 2011 hp->rx_skbs[elem] = new_skb; 2012 new_skb->dev = dev; 2013 skb_put(new_skb, (ETH_FRAME_LEN + RX_OFFSET)); 2014 hme_write_rxd(hp, this, 2015 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)), 2016 hme_dma_map(hp, new_skb->data, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE)); 2017 skb_reserve(new_skb, RX_OFFSET); 2018 2019 /* Trim the original skb for the netif. */ 2020 skb_trim(skb, len); 2021 } else { 2022 struct sk_buff *copy_skb = dev_alloc_skb(len + 2); 2023 2024 if (copy_skb == NULL) { 2025 drops++; 2026 goto drop_it; 2027 } 2028 2029 skb_reserve(copy_skb, 2); 2030 skb_put(copy_skb, len); 2031 hme_dma_sync_for_cpu(hp, dma_addr, len, DMA_FROMDEVICE); 2032 skb_copy_from_linear_data(skb, copy_skb->data, len); 2033 hme_dma_sync_for_device(hp, dma_addr, len, DMA_FROMDEVICE); 2034 2035 /* Reuse original ring buffer. */ 2036 hme_write_rxd(hp, this, 2037 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)), 2038 dma_addr); 2039 2040 skb = copy_skb; 2041 } 2042 2043 /* This card is _fucking_ hot... */ 2044 skb->csum = ntohs(csum ^ 0xffff); 2045 skb->ip_summed = CHECKSUM_COMPLETE; 2046 2047 RXD(("len=%d csum=%4x]", len, csum)); 2048 skb->protocol = eth_type_trans(skb, dev); 2049 netif_rx(skb); 2050 2051 dev->last_rx = jiffies; 2052 hp->net_stats.rx_packets++; 2053 hp->net_stats.rx_bytes += len; 2054 next: 2055 elem = NEXT_RX(elem); 2056 this = &rxbase[elem]; 2057 } 2058 hp->rx_new = elem; 2059 if (drops) 2060 printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n", hp->dev->name); 2061 RXD((">")); 2062} 2063 2064static irqreturn_t happy_meal_interrupt(int irq, void *dev_id) 2065{ 2066 struct net_device *dev = dev_id; 2067 struct happy_meal *hp = netdev_priv(dev); 2068 u32 happy_status = hme_read32(hp, hp->gregs + GREG_STAT); 2069 2070 HMD(("happy_meal_interrupt: status=%08x ", happy_status)); 2071 2072 spin_lock(&hp->happy_lock); 2073 2074 if (happy_status & GREG_STAT_ERRORS) { 2075 HMD(("ERRORS ")); 2076 if (happy_meal_is_not_so_happy(hp, /* un- */ happy_status)) 2077 goto out; 2078 } 2079 2080 if (happy_status & GREG_STAT_MIFIRQ) { 2081 HMD(("MIFIRQ ")); 2082 happy_meal_mif_interrupt(hp); 2083 } 2084 2085 if (happy_status & GREG_STAT_TXALL) { 2086 HMD(("TXALL ")); 2087 happy_meal_tx(hp); 2088 } 2089 2090 if (happy_status & GREG_STAT_RXTOHOST) { 2091 HMD(("RXTOHOST ")); 2092 happy_meal_rx(hp, dev); 2093 } 2094 2095 HMD(("done\n")); 2096out: 2097 spin_unlock(&hp->happy_lock); 2098 2099 return IRQ_HANDLED; 2100} 2101 2102#ifdef CONFIG_SBUS 2103static irqreturn_t quattro_sbus_interrupt(int irq, void *cookie) 2104{ 2105 struct quattro *qp = (struct quattro *) cookie; 2106 int i; 2107 2108 for (i = 0; i < 4; i++) { 2109 struct net_device *dev = qp->happy_meals[i]; 2110 struct happy_meal *hp = dev->priv; 2111 u32 happy_status = hme_read32(hp, hp->gregs + GREG_STAT); 2112 2113 HMD(("quattro_interrupt: status=%08x ", happy_status)); 2114 2115 if (!(happy_status & (GREG_STAT_ERRORS | 2116 GREG_STAT_MIFIRQ | 2117 GREG_STAT_TXALL | 2118 GREG_STAT_RXTOHOST))) 2119 continue; 2120 2121 spin_lock(&hp->happy_lock); 2122 2123 if (happy_status & GREG_STAT_ERRORS) { 2124 HMD(("ERRORS ")); 2125 if (happy_meal_is_not_so_happy(hp, happy_status)) 2126 goto next; 2127 } 2128 2129 if (happy_status & GREG_STAT_MIFIRQ) { 2130 HMD(("MIFIRQ ")); 2131 happy_meal_mif_interrupt(hp); 2132 } 2133 2134 if (happy_status & GREG_STAT_TXALL) { 2135 HMD(("TXALL ")); 2136 happy_meal_tx(hp); 2137 } 2138 2139 if (happy_status & GREG_STAT_RXTOHOST) { 2140 HMD(("RXTOHOST ")); 2141 happy_meal_rx(hp, dev); 2142 } 2143 2144 next: 2145 spin_unlock(&hp->happy_lock); 2146 } 2147 HMD(("done\n")); 2148 2149 return IRQ_HANDLED; 2150} 2151#endif 2152 2153static int happy_meal_open(struct net_device *dev) 2154{ 2155 struct happy_meal *hp = dev->priv; 2156 int res; 2157 2158 HMD(("happy_meal_open: ")); 2159 2160 /* On SBUS Quattro QFE cards, all hme interrupts are concentrated 2161 * into a single source which we register handling at probe time. 2162 */ 2163 if ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO) { 2164 if (request_irq(dev->irq, &happy_meal_interrupt, 2165 IRQF_SHARED, dev->name, (void *)dev)) { 2166 HMD(("EAGAIN\n")); 2167 printk(KERN_ERR "happy_meal(SBUS): Can't order irq %d to go.\n", 2168 dev->irq); 2169 2170 return -EAGAIN; 2171 } 2172 } 2173 2174 HMD(("to happy_meal_init\n")); 2175 2176 spin_lock_irq(&hp->happy_lock); 2177 res = happy_meal_init(hp); 2178 spin_unlock_irq(&hp->happy_lock); 2179 2180 if (res && ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO)) 2181 free_irq(dev->irq, dev); 2182 return res; 2183} 2184 2185static int happy_meal_close(struct net_device *dev) 2186{ 2187 struct happy_meal *hp = dev->priv; 2188 2189 spin_lock_irq(&hp->happy_lock); 2190 happy_meal_stop(hp, hp->gregs); 2191 happy_meal_clean_rings(hp); 2192 2193 /* If auto-negotiation timer is running, kill it. */ 2194 del_timer(&hp->happy_timer); 2195 2196 spin_unlock_irq(&hp->happy_lock); 2197 2198 /* On Quattro QFE cards, all hme interrupts are concentrated 2199 * into a single source which we register handling at probe 2200 * time and never unregister. 2201 */ 2202 if ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO) 2203 free_irq(dev->irq, dev); 2204 2205 return 0; 2206} 2207 2208#ifdef SXDEBUG 2209#define SXD(x) printk x 2210#else 2211#define SXD(x) 2212#endif 2213 2214static void happy_meal_tx_timeout(struct net_device *dev) 2215{ 2216 struct happy_meal *hp = dev->priv; 2217 2218 printk (KERN_ERR "%s: transmit timed out, resetting\n", dev->name); 2219 tx_dump_log(); 2220 printk (KERN_ERR "%s: Happy Status %08x TX[%08x:%08x]\n", dev->name, 2221 hme_read32(hp, hp->gregs + GREG_STAT), 2222 hme_read32(hp, hp->etxregs + ETX_CFG), 2223 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG)); 2224 2225 spin_lock_irq(&hp->happy_lock); 2226 happy_meal_init(hp); 2227 spin_unlock_irq(&hp->happy_lock); 2228 2229 netif_wake_queue(dev); 2230} 2231 2232static int happy_meal_start_xmit(struct sk_buff *skb, struct net_device *dev) 2233{ 2234 struct happy_meal *hp = dev->priv; 2235 int entry; 2236 u32 tx_flags; 2237 2238 tx_flags = TXFLAG_OWN; 2239 if (skb->ip_summed == CHECKSUM_PARTIAL) { 2240 const u32 csum_start_off = skb_transport_offset(skb); 2241 const u32 csum_stuff_off = csum_start_off + skb->csum_offset; 2242 2243 tx_flags = (TXFLAG_OWN | TXFLAG_CSENABLE | 2244 ((csum_start_off << 14) & TXFLAG_CSBUFBEGIN) | 2245 ((csum_stuff_off << 20) & TXFLAG_CSLOCATION)); 2246 } 2247 2248 spin_lock_irq(&hp->happy_lock); 2249 2250 if (TX_BUFFS_AVAIL(hp) <= (skb_shinfo(skb)->nr_frags + 1)) { 2251 netif_stop_queue(dev); 2252 spin_unlock_irq(&hp->happy_lock); 2253 printk(KERN_ERR "%s: BUG! Tx Ring full when queue awake!\n", 2254 dev->name); 2255 return 1; 2256 } 2257 2258 entry = hp->tx_new; 2259 SXD(("SX<l[%d]e[%d]>", len, entry)); 2260 hp->tx_skbs[entry] = skb; 2261 2262 if (skb_shinfo(skb)->nr_frags == 0) { 2263 u32 mapping, len; 2264 2265 len = skb->len; 2266 mapping = hme_dma_map(hp, skb->data, len, DMA_TODEVICE); 2267 tx_flags |= (TXFLAG_SOP | TXFLAG_EOP); 2268 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[entry], 2269 (tx_flags | (len & TXFLAG_SIZE)), 2270 mapping); 2271 entry = NEXT_TX(entry); 2272 } else { 2273 u32 first_len, first_mapping; 2274 int frag, first_entry = entry; 2275 2276 /* We must give this initial chunk to the device last. 2277 * Otherwise we could race with the device. 2278 */ 2279 first_len = skb_headlen(skb); 2280 first_mapping = hme_dma_map(hp, skb->data, first_len, DMA_TODEVICE); 2281 entry = NEXT_TX(entry); 2282 2283 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) { 2284 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag]; 2285 u32 len, mapping, this_txflags; 2286 2287 len = this_frag->size; 2288 mapping = hme_dma_map(hp, 2289 ((void *) page_address(this_frag->page) + 2290 this_frag->page_offset), 2291 len, DMA_TODEVICE); 2292 this_txflags = tx_flags; 2293 if (frag == skb_shinfo(skb)->nr_frags - 1) 2294 this_txflags |= TXFLAG_EOP; 2295 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[entry], 2296 (this_txflags | (len & TXFLAG_SIZE)), 2297 mapping); 2298 entry = NEXT_TX(entry); 2299 } 2300 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[first_entry], 2301 (tx_flags | TXFLAG_SOP | (first_len & TXFLAG_SIZE)), 2302 first_mapping); 2303 } 2304 2305 hp->tx_new = entry; 2306 2307 if (TX_BUFFS_AVAIL(hp) <= (MAX_SKB_FRAGS + 1)) 2308 netif_stop_queue(dev); 2309 2310 /* Get it going. */ 2311 hme_write32(hp, hp->etxregs + ETX_PENDING, ETX_TP_DMAWAKEUP); 2312 2313 spin_unlock_irq(&hp->happy_lock); 2314 2315 dev->trans_start = jiffies; 2316 2317 tx_add_log(hp, TXLOG_ACTION_TXMIT, 0); 2318 return 0; 2319} 2320 2321static struct net_device_stats *happy_meal_get_stats(struct net_device *dev) 2322{ 2323 struct happy_meal *hp = dev->priv; 2324 2325 spin_lock_irq(&hp->happy_lock); 2326 happy_meal_get_counters(hp, hp->bigmacregs); 2327 spin_unlock_irq(&hp->happy_lock); 2328 2329 return &hp->net_stats; 2330} 2331 2332static void happy_meal_set_multicast(struct net_device *dev) 2333{ 2334 struct happy_meal *hp = dev->priv; 2335 void __iomem *bregs = hp->bigmacregs; 2336 struct dev_mc_list *dmi = dev->mc_list; 2337 char *addrs; 2338 int i; 2339 u32 crc; 2340 2341 spin_lock_irq(&hp->happy_lock); 2342 2343 netif_stop_queue(dev); 2344 2345 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) { 2346 hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff); 2347 hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff); 2348 hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff); 2349 hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff); 2350 } else if (dev->flags & IFF_PROMISC) { 2351 hme_write32(hp, bregs + BMAC_RXCFG, 2352 hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_PMISC); 2353 } else { 2354 u16 hash_table[4]; 2355 2356 for (i = 0; i < 4; i++) 2357 hash_table[i] = 0; 2358 2359 for (i = 0; i < dev->mc_count; i++) { 2360 addrs = dmi->dmi_addr; 2361 dmi = dmi->next; 2362 2363 if (!(*addrs & 1)) 2364 continue; 2365 2366 crc = ether_crc_le(6, addrs); 2367 crc >>= 26; 2368 hash_table[crc >> 4] |= 1 << (crc & 0xf); 2369 } 2370 hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]); 2371 hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]); 2372 hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]); 2373 hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]); 2374 } 2375 2376 netif_wake_queue(dev); 2377 2378 spin_unlock_irq(&hp->happy_lock); 2379} 2380 2381/* Ethtool support... */ 2382static int hme_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 2383{ 2384 struct happy_meal *hp = dev->priv; 2385 2386 cmd->supported = 2387 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | 2388 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | 2389 SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII); 2390 2391 cmd->port = PORT_TP; 2392 cmd->transceiver = XCVR_INTERNAL; 2393 cmd->phy_address = 0; 2394 2395 /* Record PHY settings. */ 2396 spin_lock_irq(&hp->happy_lock); 2397 hp->sw_bmcr = happy_meal_tcvr_read(hp, hp->tcvregs, MII_BMCR); 2398 hp->sw_lpa = happy_meal_tcvr_read(hp, hp->tcvregs, MII_LPA); 2399 spin_unlock_irq(&hp->happy_lock); 2400 2401 if (hp->sw_bmcr & BMCR_ANENABLE) { 2402 cmd->autoneg = AUTONEG_ENABLE; 2403 cmd->speed = 2404 (hp->sw_lpa & (LPA_100HALF | LPA_100FULL)) ? 2405 SPEED_100 : SPEED_10; 2406 if (cmd->speed == SPEED_100) 2407 cmd->duplex = 2408 (hp->sw_lpa & (LPA_100FULL)) ? 2409 DUPLEX_FULL : DUPLEX_HALF; 2410 else 2411 cmd->duplex = 2412 (hp->sw_lpa & (LPA_10FULL)) ? 2413 DUPLEX_FULL : DUPLEX_HALF; 2414 } else { 2415 cmd->autoneg = AUTONEG_DISABLE; 2416 cmd->speed = 2417 (hp->sw_bmcr & BMCR_SPEED100) ? 2418 SPEED_100 : SPEED_10; 2419 cmd->duplex = 2420 (hp->sw_bmcr & BMCR_FULLDPLX) ? 2421 DUPLEX_FULL : DUPLEX_HALF; 2422 } 2423 return 0; 2424} 2425 2426static int hme_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 2427{ 2428 struct happy_meal *hp = dev->priv; 2429 2430 /* Verify the settings we care about. */ 2431 if (cmd->autoneg != AUTONEG_ENABLE && 2432 cmd->autoneg != AUTONEG_DISABLE) 2433 return -EINVAL; 2434 if (cmd->autoneg == AUTONEG_DISABLE && 2435 ((cmd->speed != SPEED_100 && 2436 cmd->speed != SPEED_10) || 2437 (cmd->duplex != DUPLEX_HALF && 2438 cmd->duplex != DUPLEX_FULL))) 2439 return -EINVAL; 2440 2441 /* Ok, do it to it. */ 2442 spin_lock_irq(&hp->happy_lock); 2443 del_timer(&hp->happy_timer); 2444 happy_meal_begin_auto_negotiation(hp, hp->tcvregs, cmd); 2445 spin_unlock_irq(&hp->happy_lock); 2446 2447 return 0; 2448} 2449 2450static void hme_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 2451{ 2452 struct happy_meal *hp = dev->priv; 2453 2454 strcpy(info->driver, "sunhme"); 2455 strcpy(info->version, "2.02"); 2456 if (hp->happy_flags & HFLAG_PCI) { 2457 struct pci_dev *pdev = hp->happy_dev; 2458 strcpy(info->bus_info, pci_name(pdev)); 2459 } 2460#ifdef CONFIG_SBUS 2461 else { 2462 struct sbus_dev *sdev = hp->happy_dev; 2463 sprintf(info->bus_info, "SBUS:%d", 2464 sdev->slot); 2465 } 2466#endif 2467} 2468 2469static u32 hme_get_link(struct net_device *dev) 2470{ 2471 struct happy_meal *hp = dev->priv; 2472 2473 spin_lock_irq(&hp->happy_lock); 2474 hp->sw_bmcr = happy_meal_tcvr_read(hp, hp->tcvregs, MII_BMCR); 2475 spin_unlock_irq(&hp->happy_lock); 2476 2477 return (hp->sw_bmsr & BMSR_LSTATUS); 2478} 2479 2480static const struct ethtool_ops hme_ethtool_ops = { 2481 .get_settings = hme_get_settings, 2482 .set_settings = hme_set_settings, 2483 .get_drvinfo = hme_get_drvinfo, 2484 .get_link = hme_get_link, 2485}; 2486 2487static int hme_version_printed; 2488 2489#ifdef CONFIG_SBUS 2490void __devinit quattro_get_ranges(struct quattro *qp) 2491{ 2492 struct sbus_dev *sdev = qp->quattro_dev; 2493 int err; 2494 2495 err = prom_getproperty(sdev->prom_node, 2496 "ranges", 2497 (char *)&qp->ranges[0], 2498 sizeof(qp->ranges)); 2499 if (err == 0 || err == -1) { 2500 qp->nranges = 0; 2501 return; 2502 } 2503 qp->nranges = (err / sizeof(struct linux_prom_ranges)); 2504} 2505 2506static void __devinit quattro_apply_ranges(struct quattro *qp, struct happy_meal *hp) 2507{ 2508 struct sbus_dev *sdev = hp->happy_dev; 2509 int rng; 2510 2511 for (rng = 0; rng < qp->nranges; rng++) { 2512 struct linux_prom_ranges *rngp = &qp->ranges[rng]; 2513 int reg; 2514 2515 for (reg = 0; reg < 5; reg++) { 2516 if (sdev->reg_addrs[reg].which_io == 2517 rngp->ot_child_space) 2518 break; 2519 } 2520 if (reg == 5) 2521 continue; 2522 2523 sdev->reg_addrs[reg].which_io = rngp->ot_parent_space; 2524 sdev->reg_addrs[reg].phys_addr += rngp->ot_parent_base; 2525 } 2526} 2527 2528/* Given a happy meal sbus device, find it's quattro parent. 2529 * If none exist, allocate and return a new one. 2530 * 2531 * Return NULL on failure. 2532 */ 2533static struct quattro * __devinit quattro_sbus_find(struct sbus_dev *goal_sdev) 2534{ 2535 struct sbus_dev *sdev; 2536 struct quattro *qp; 2537 int i; 2538 2539 for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) { 2540 for (i = 0, sdev = qp->quattro_dev; 2541 (sdev != NULL) && (i < 4); 2542 sdev = sdev->next, i++) { 2543 if (sdev == goal_sdev) 2544 return qp; 2545 } 2546 } 2547 2548 qp = kmalloc(sizeof(struct quattro), GFP_KERNEL); 2549 if (qp != NULL) { 2550 int i; 2551 2552 for (i = 0; i < 4; i++) 2553 qp->happy_meals[i] = NULL; 2554 2555 qp->quattro_dev = goal_sdev; 2556 qp->next = qfe_sbus_list; 2557 qfe_sbus_list = qp; 2558 quattro_get_ranges(qp); 2559 } 2560 return qp; 2561} 2562 2563/* After all quattro cards have been probed, we call these functions 2564 * to register the IRQ handlers. 2565 */ 2566static void __init quattro_sbus_register_irqs(void) 2567{ 2568 struct quattro *qp; 2569 2570 for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) { 2571 struct sbus_dev *sdev = qp->quattro_dev; 2572 int err; 2573 2574 err = request_irq(sdev->irqs[0], 2575 quattro_sbus_interrupt, 2576 IRQF_SHARED, "Quattro", 2577 qp); 2578 if (err != 0) { 2579 printk(KERN_ERR "Quattro: Fatal IRQ registery error %d.\n", err); 2580 panic("QFE request irq"); 2581 } 2582 } 2583} 2584 2585static void quattro_sbus_free_irqs(void) 2586{ 2587 struct quattro *qp; 2588 2589 for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) { 2590 struct sbus_dev *sdev = qp->quattro_dev; 2591 2592 free_irq(sdev->irqs[0], qp); 2593 } 2594} 2595#endif /* CONFIG_SBUS */ 2596 2597#ifdef CONFIG_PCI 2598static struct quattro * __init quattro_pci_find(struct pci_dev *pdev) 2599{ 2600 struct pci_dev *bdev = pdev->bus->self; 2601 struct quattro *qp; 2602 2603 if (!bdev) return NULL; 2604 for (qp = qfe_pci_list; qp != NULL; qp = qp->next) { 2605 struct pci_dev *qpdev = qp->quattro_dev; 2606 2607 if (qpdev == bdev) 2608 return qp; 2609 } 2610 qp = kmalloc(sizeof(struct quattro), GFP_KERNEL); 2611 if (qp != NULL) { 2612 int i; 2613 2614 for (i = 0; i < 4; i++) 2615 qp->happy_meals[i] = NULL; 2616 2617 qp->quattro_dev = bdev; 2618 qp->next = qfe_pci_list; 2619 qfe_pci_list = qp; 2620 2621 /* No range tricks necessary on PCI. */ 2622 qp->nranges = 0; 2623 } 2624 return qp; 2625} 2626#endif /* CONFIG_PCI */ 2627 2628#ifdef CONFIG_SBUS 2629static int __devinit happy_meal_sbus_probe_one(struct sbus_dev *sdev, int is_qfe) 2630{ 2631 struct device_node *dp = sdev->ofdev.node; 2632 struct quattro *qp = NULL; 2633 struct happy_meal *hp; 2634 struct net_device *dev; 2635 int i, qfe_slot = -1; 2636 int err = -ENODEV; 2637 2638 if (is_qfe) { 2639 qp = quattro_sbus_find(sdev); 2640 if (qp == NULL) 2641 goto err_out; 2642 for (qfe_slot = 0; qfe_slot < 4; qfe_slot++) 2643 if (qp->happy_meals[qfe_slot] == NULL) 2644 break; 2645 if (qfe_slot == 4) 2646 goto err_out; 2647 } 2648 2649 err = -ENOMEM; 2650 dev = alloc_etherdev(sizeof(struct happy_meal)); 2651 if (!dev) 2652 goto err_out; 2653 SET_MODULE_OWNER(dev); 2654 SET_NETDEV_DEV(dev, &sdev->ofdev.dev); 2655 2656 if (hme_version_printed++ == 0) 2657 printk(KERN_INFO "%s", version); 2658 2659 /* If user did not specify a MAC address specifically, use 2660 * the Quattro local-mac-address property... 2661 */ 2662 for (i = 0; i < 6; i++) { 2663 if (macaddr[i] != 0) 2664 break; 2665 } 2666 if (i < 6) { /* a mac address was given */ 2667 for (i = 0; i < 6; i++) 2668 dev->dev_addr[i] = macaddr[i]; 2669 macaddr[5]++; 2670 } else { 2671 const unsigned char *addr; 2672 int len; 2673 2674 addr = of_get_property(dp, "local-mac-address", &len); 2675 2676 if (qfe_slot != -1 && addr && len == 6) 2677 memcpy(dev->dev_addr, addr, 6); 2678 else 2679 memcpy(dev->dev_addr, idprom->id_ethaddr, 6); 2680 } 2681 2682 hp = dev->priv; 2683 2684 hp->happy_dev = sdev; 2685 2686 spin_lock_init(&hp->happy_lock); 2687 2688 err = -ENODEV; 2689 if (sdev->num_registers != 5) { 2690 printk(KERN_ERR "happymeal: Device needs 5 regs, has %d.\n", 2691 sdev->num_registers); 2692 goto err_out_free_netdev; 2693 } 2694 2695 if (qp != NULL) { 2696 hp->qfe_parent = qp; 2697 hp->qfe_ent = qfe_slot; 2698 qp->happy_meals[qfe_slot] = dev; 2699 quattro_apply_ranges(qp, hp); 2700 } 2701 2702 hp->gregs = sbus_ioremap(&sdev->resource[0], 0, 2703 GREG_REG_SIZE, "HME Global Regs"); 2704 if (!hp->gregs) { 2705 printk(KERN_ERR "happymeal: Cannot map global registers.\n"); 2706 goto err_out_free_netdev; 2707 } 2708 2709 hp->etxregs = sbus_ioremap(&sdev->resource[1], 0, 2710 ETX_REG_SIZE, "HME TX Regs"); 2711 if (!hp->etxregs) { 2712 printk(KERN_ERR "happymeal: Cannot map MAC TX registers.\n"); 2713 goto err_out_iounmap; 2714 } 2715 2716 hp->erxregs = sbus_ioremap(&sdev->resource[2], 0, 2717 ERX_REG_SIZE, "HME RX Regs"); 2718 if (!hp->erxregs) { 2719 printk(KERN_ERR "happymeal: Cannot map MAC RX registers.\n"); 2720 goto err_out_iounmap; 2721 } 2722 2723 hp->bigmacregs = sbus_ioremap(&sdev->resource[3], 0, 2724 BMAC_REG_SIZE, "HME BIGMAC Regs"); 2725 if (!hp->bigmacregs) { 2726 printk(KERN_ERR "happymeal: Cannot map BIGMAC registers.\n"); 2727 goto err_out_iounmap; 2728 } 2729 2730 hp->tcvregs = sbus_ioremap(&sdev->resource[4], 0, 2731 TCVR_REG_SIZE, "HME Tranceiver Regs"); 2732 if (!hp->tcvregs) { 2733 printk(KERN_ERR "happymeal: Cannot map TCVR registers.\n"); 2734 goto err_out_iounmap; 2735 } 2736 2737 hp->hm_revision = of_getintprop_default(dp, "hm-rev", 0xff); 2738 if (hp->hm_revision == 0xff) 2739 hp->hm_revision = 0xa0; 2740 2741 /* Now enable the feature flags we can. */ 2742 if (hp->hm_revision == 0x20 || hp->hm_revision == 0x21) 2743 hp->happy_flags = HFLAG_20_21; 2744 else if (hp->hm_revision != 0xa0) 2745 hp->happy_flags = HFLAG_NOT_A0; 2746 2747 if (qp != NULL) 2748 hp->happy_flags |= HFLAG_QUATTRO; 2749 2750 /* Get the supported DVMA burst sizes from our Happy SBUS. */ 2751 hp->happy_bursts = of_getintprop_default(sdev->bus->ofdev.node, 2752 "burst-sizes", 0x00); 2753 2754 hp->happy_block = sbus_alloc_consistent(hp->happy_dev, 2755 PAGE_SIZE, 2756 &hp->hblock_dvma); 2757 err = -ENOMEM; 2758 if (!hp->happy_block) { 2759 printk(KERN_ERR "happymeal: Cannot allocate descriptors.\n"); 2760 goto err_out_iounmap; 2761 } 2762 2763 /* Force check of the link first time we are brought up. */ 2764 hp->linkcheck = 0; 2765 2766 /* Force timer state to 'asleep' with count of zero. */ 2767 hp->timer_state = asleep; 2768 hp->timer_ticks = 0; 2769 2770 init_timer(&hp->happy_timer); 2771 2772 hp->dev = dev; 2773 dev->open = &happy_meal_open; 2774 dev->stop = &happy_meal_close; 2775 dev->hard_start_xmit = &happy_meal_start_xmit; 2776 dev->get_stats = &happy_meal_get_stats; 2777 dev->set_multicast_list = &happy_meal_set_multicast; 2778 dev->tx_timeout = &happy_meal_tx_timeout; 2779 dev->watchdog_timeo = 5*HZ; 2780 dev->ethtool_ops = &hme_ethtool_ops; 2781 2782 /* Happy Meal can do it all... except VLAN. */ 2783 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_VLAN_CHALLENGED; 2784 2785 dev->irq = sdev->irqs[0]; 2786 2787#if defined(CONFIG_SBUS) && defined(CONFIG_PCI) 2788 /* Hook up PCI register/dma accessors. */ 2789 hp->read_desc32 = sbus_hme_read_desc32; 2790 hp->write_txd = sbus_hme_write_txd; 2791 hp->write_rxd = sbus_hme_write_rxd; 2792 hp->dma_map = (u32 (*)(void *, void *, long, int))sbus_map_single; 2793 hp->dma_unmap = (void (*)(void *, u32, long, int))sbus_unmap_single; 2794 hp->dma_sync_for_cpu = (void (*)(void *, u32, long, int)) 2795 sbus_dma_sync_single_for_cpu; 2796 hp->dma_sync_for_device = (void (*)(void *, u32, long, int)) 2797 sbus_dma_sync_single_for_device; 2798 hp->read32 = sbus_hme_read32; 2799 hp->write32 = sbus_hme_write32; 2800#endif 2801 2802 /* Grrr, Happy Meal comes up by default not advertising 2803 * full duplex 100baseT capabilities, fix this. 2804 */ 2805 spin_lock_irq(&hp->happy_lock); 2806 happy_meal_set_initial_advertisement(hp); 2807 spin_unlock_irq(&hp->happy_lock); 2808 2809 if (register_netdev(hp->dev)) { 2810 printk(KERN_ERR "happymeal: Cannot register net device, " 2811 "aborting.\n"); 2812 goto err_out_free_consistent; 2813 } 2814 2815 dev_set_drvdata(&sdev->ofdev.dev, hp); 2816 2817 if (qfe_slot != -1) 2818 printk(KERN_INFO "%s: Quattro HME slot %d (SBUS) 10/100baseT Ethernet ", 2819 dev->name, qfe_slot); 2820 else 2821 printk(KERN_INFO "%s: HAPPY MEAL (SBUS) 10/100baseT Ethernet ", 2822 dev->name); 2823 2824 for (i = 0; i < 6; i++) 2825 printk("%2.2x%c", 2826 dev->dev_addr[i], i == 5 ? ' ' : ':'); 2827 printk("\n"); 2828 2829 return 0; 2830 2831err_out_free_consistent: 2832 sbus_free_consistent(hp->happy_dev, 2833 PAGE_SIZE, 2834 hp->happy_block, 2835 hp->hblock_dvma); 2836 2837err_out_iounmap: 2838 if (hp->gregs) 2839 sbus_iounmap(hp->gregs, GREG_REG_SIZE); 2840 if (hp->etxregs) 2841 sbus_iounmap(hp->etxregs, ETX_REG_SIZE); 2842 if (hp->erxregs) 2843 sbus_iounmap(hp->erxregs, ERX_REG_SIZE); 2844 if (hp->bigmacregs) 2845 sbus_iounmap(hp->bigmacregs, BMAC_REG_SIZE); 2846 if (hp->tcvregs) 2847 sbus_iounmap(hp->tcvregs, TCVR_REG_SIZE); 2848 2849err_out_free_netdev: 2850 free_netdev(dev); 2851 2852err_out: 2853 return err; 2854} 2855#endif 2856 2857#ifdef CONFIG_PCI 2858#ifndef CONFIG_SPARC 2859static int is_quattro_p(struct pci_dev *pdev) 2860{ 2861 struct pci_dev *busdev = pdev->bus->self; 2862 struct list_head *tmp; 2863 int n_hmes; 2864 2865 if (busdev == NULL || 2866 busdev->vendor != PCI_VENDOR_ID_DEC || 2867 busdev->device != PCI_DEVICE_ID_DEC_21153) 2868 return 0; 2869 2870 n_hmes = 0; 2871 tmp = pdev->bus->devices.next; 2872 while (tmp != &pdev->bus->devices) { 2873 struct pci_dev *this_pdev = pci_dev_b(tmp); 2874 2875 if (this_pdev->vendor == PCI_VENDOR_ID_SUN && 2876 this_pdev->device == PCI_DEVICE_ID_SUN_HAPPYMEAL) 2877 n_hmes++; 2878 2879 tmp = tmp->next; 2880 } 2881 2882 if (n_hmes != 4) 2883 return 0; 2884 2885 return 1; 2886} 2887 2888/* Fetch MAC address from vital product data of PCI ROM. */ 2889static int find_eth_addr_in_vpd(void __iomem *rom_base, int len, int index, unsigned char *dev_addr) 2890{ 2891 int this_offset; 2892 2893 for (this_offset = 0x20; this_offset < len; this_offset++) { 2894 void __iomem *p = rom_base + this_offset; 2895 2896 if (readb(p + 0) != 0x90 || 2897 readb(p + 1) != 0x00 || 2898 readb(p + 2) != 0x09 || 2899 readb(p + 3) != 0x4e || 2900 readb(p + 4) != 0x41 || 2901 readb(p + 5) != 0x06) 2902 continue; 2903 2904 this_offset += 6; 2905 p += 6; 2906 2907 if (index == 0) { 2908 int i; 2909 2910 for (i = 0; i < 6; i++) 2911 dev_addr[i] = readb(p + i); 2912 return 1; 2913 } 2914 index--; 2915 } 2916 return 0; 2917} 2918 2919static void get_hme_mac_nonsparc(struct pci_dev *pdev, unsigned char *dev_addr) 2920{ 2921 size_t size; 2922 void __iomem *p = pci_map_rom(pdev, &size); 2923 2924 if (p) { 2925 int index = 0; 2926 int found; 2927 2928 if (is_quattro_p(pdev)) 2929 index = PCI_SLOT(pdev->devfn); 2930 2931 found = readb(p) == 0x55 && 2932 readb(p + 1) == 0xaa && 2933 find_eth_addr_in_vpd(p, (64 * 1024), index, dev_addr); 2934 pci_unmap_rom(pdev, p); 2935 if (found) 2936 return; 2937 } 2938 2939 /* Sun MAC prefix then 3 random bytes. */ 2940 dev_addr[0] = 0x08; 2941 dev_addr[1] = 0x00; 2942 dev_addr[2] = 0x20; 2943 get_random_bytes(&dev_addr[3], 3); 2944 return; 2945} 2946#endif /* !(CONFIG_SPARC) */ 2947 2948static int __devinit happy_meal_pci_probe(struct pci_dev *pdev, 2949 const struct pci_device_id *ent) 2950{ 2951 struct quattro *qp = NULL; 2952#ifdef CONFIG_SPARC 2953 struct device_node *dp; 2954#endif 2955 struct happy_meal *hp; 2956 struct net_device *dev; 2957 void __iomem *hpreg_base; 2958 unsigned long hpreg_res; 2959 int i, qfe_slot = -1; 2960 char prom_name[64]; 2961 int err; 2962 2963 /* Now make sure pci_dev cookie is there. */ 2964#ifdef CONFIG_SPARC 2965 dp = pci_device_to_OF_node(pdev); 2966 strcpy(prom_name, dp->name); 2967#else 2968 if (is_quattro_p(pdev)) 2969 strcpy(prom_name, "SUNW,qfe"); 2970 else 2971 strcpy(prom_name, "SUNW,hme"); 2972#endif 2973 2974 err = -ENODEV; 2975 2976 if (pci_enable_device(pdev)) 2977 goto err_out; 2978 pci_set_master(pdev); 2979 2980 if (!strcmp(prom_name, "SUNW,qfe") || !strcmp(prom_name, "qfe")) { 2981 qp = quattro_pci_find(pdev); 2982 if (qp == NULL) 2983 goto err_out; 2984 for (qfe_slot = 0; qfe_slot < 4; qfe_slot++) 2985 if (qp->happy_meals[qfe_slot] == NULL) 2986 break; 2987 if (qfe_slot == 4) 2988 goto err_out; 2989 } 2990 2991 dev = alloc_etherdev(sizeof(struct happy_meal)); 2992 err = -ENOMEM; 2993 if (!dev) 2994 goto err_out; 2995 SET_MODULE_OWNER(dev); 2996 SET_NETDEV_DEV(dev, &pdev->dev); 2997 2998 if (hme_version_printed++ == 0) 2999 printk(KERN_INFO "%s", version); 3000 3001 dev->base_addr = (long) pdev; 3002 3003 hp = (struct happy_meal *)dev->priv; 3004 memset(hp, 0, sizeof(*hp)); 3005 3006 hp->happy_dev = pdev; 3007 3008 spin_lock_init(&hp->happy_lock); 3009 3010 if (qp != NULL) { 3011 hp->qfe_parent = qp; 3012 hp->qfe_ent = qfe_slot; 3013 qp->happy_meals[qfe_slot] = dev; 3014 } 3015 3016 hpreg_res = pci_resource_start(pdev, 0); 3017 err = -ENODEV; 3018 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) { 3019 printk(KERN_ERR "happymeal(PCI): Cannot find proper PCI device base address.\n"); 3020 goto err_out_clear_quattro; 3021 } 3022 if (pci_request_regions(pdev, DRV_NAME)) { 3023 printk(KERN_ERR "happymeal(PCI): Cannot obtain PCI resources, " 3024 "aborting.\n"); 3025 goto err_out_clear_quattro; 3026 } 3027 3028 if ((hpreg_base = ioremap(hpreg_res, 0x8000)) == 0) { 3029 printk(KERN_ERR "happymeal(PCI): Unable to remap card memory.\n"); 3030 goto err_out_free_res; 3031 } 3032 3033 for (i = 0; i < 6; i++) { 3034 if (macaddr[i] != 0) 3035 break; 3036 } 3037 if (i < 6) { /* a mac address was given */ 3038 for (i = 0; i < 6; i++) 3039 dev->dev_addr[i] = macaddr[i]; 3040 macaddr[5]++; 3041 } else { 3042#ifdef CONFIG_SPARC 3043 const unsigned char *addr; 3044 int len; 3045 3046 if (qfe_slot != -1 && 3047 (addr = of_get_property(dp, 3048 "local-mac-address", &len)) != NULL 3049 && len == 6) { 3050 memcpy(dev->dev_addr, addr, 6); 3051 } else { 3052 memcpy(dev->dev_addr, idprom->id_ethaddr, 6); 3053 } 3054#else 3055 get_hme_mac_nonsparc(pdev, &dev->dev_addr[0]); 3056#endif 3057 } 3058 3059 /* Layout registers. */ 3060 hp->gregs = (hpreg_base + 0x0000UL); 3061 hp->etxregs = (hpreg_base + 0x2000UL); 3062 hp->erxregs = (hpreg_base + 0x4000UL); 3063 hp->bigmacregs = (hpreg_base + 0x6000UL); 3064 hp->tcvregs = (hpreg_base + 0x7000UL); 3065 3066#ifdef CONFIG_SPARC 3067 hp->hm_revision = of_getintprop_default(dp, "hm-rev", 0xff); 3068 if (hp->hm_revision == 0xff) { 3069 unsigned char prev; 3070 3071 pci_read_config_byte(pdev, PCI_REVISION_ID, &prev); 3072 hp->hm_revision = 0xc0 | (prev & 0x0f); 3073 } 3074#else 3075 /* works with this on non-sparc hosts */ 3076 hp->hm_revision = 0x20; 3077#endif 3078 3079 /* Now enable the feature flags we can. */ 3080 if (hp->hm_revision == 0x20 || hp->hm_revision == 0x21) 3081 hp->happy_flags = HFLAG_20_21; 3082 else if (hp->hm_revision != 0xa0 && hp->hm_revision != 0xc0) 3083 hp->happy_flags = HFLAG_NOT_A0; 3084 3085 if (qp != NULL) 3086 hp->happy_flags |= HFLAG_QUATTRO; 3087 3088 /* And of course, indicate this is PCI. */ 3089 hp->happy_flags |= HFLAG_PCI; 3090 3091#ifdef CONFIG_SPARC 3092 /* Assume PCI happy meals can handle all burst sizes. */ 3093 hp->happy_bursts = DMA_BURSTBITS; 3094#endif 3095 3096 hp->happy_block = (struct hmeal_init_block *) 3097 pci_alloc_consistent(pdev, PAGE_SIZE, &hp->hblock_dvma); 3098 3099 err = -ENODEV; 3100 if (!hp->happy_block) { 3101 printk(KERN_ERR "happymeal(PCI): Cannot get hme init block.\n"); 3102 goto err_out_iounmap; 3103 } 3104 3105 hp->linkcheck = 0; 3106 hp->timer_state = asleep; 3107 hp->timer_ticks = 0; 3108 3109 init_timer(&hp->happy_timer); 3110 3111 hp->dev = dev; 3112 dev->open = &happy_meal_open; 3113 dev->stop = &happy_meal_close; 3114 dev->hard_start_xmit = &happy_meal_start_xmit; 3115 dev->get_stats = &happy_meal_get_stats; 3116 dev->set_multicast_list = &happy_meal_set_multicast; 3117 dev->tx_timeout = &happy_meal_tx_timeout; 3118 dev->watchdog_timeo = 5*HZ; 3119 dev->ethtool_ops = &hme_ethtool_ops; 3120 dev->irq = pdev->irq; 3121 dev->dma = 0; 3122 3123 /* Happy Meal can do it all... */ 3124 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM; 3125 3126#if defined(CONFIG_SBUS) && defined(CONFIG_PCI) 3127 /* Hook up PCI register/dma accessors. */ 3128 hp->read_desc32 = pci_hme_read_desc32; 3129 hp->write_txd = pci_hme_write_txd; 3130 hp->write_rxd = pci_hme_write_rxd; 3131 hp->dma_map = (u32 (*)(void *, void *, long, int))pci_map_single; 3132 hp->dma_unmap = (void (*)(void *, u32, long, int))pci_unmap_single; 3133 hp->dma_sync_for_cpu = (void (*)(void *, u32, long, int)) 3134 pci_dma_sync_single_for_cpu; 3135 hp->dma_sync_for_device = (void (*)(void *, u32, long, int)) 3136 pci_dma_sync_single_for_device; 3137 hp->read32 = pci_hme_read32; 3138 hp->write32 = pci_hme_write32; 3139#endif 3140 3141 /* Grrr, Happy Meal comes up by default not advertising 3142 * full duplex 100baseT capabilities, fix this. 3143 */ 3144 spin_lock_irq(&hp->happy_lock); 3145 happy_meal_set_initial_advertisement(hp); 3146 spin_unlock_irq(&hp->happy_lock); 3147 3148 if (register_netdev(hp->dev)) { 3149 printk(KERN_ERR "happymeal(PCI): Cannot register net device, " 3150 "aborting.\n"); 3151 goto err_out_iounmap; 3152 } 3153 3154 dev_set_drvdata(&pdev->dev, hp); 3155 3156 if (!qfe_slot) { 3157 struct pci_dev *qpdev = qp->quattro_dev; 3158 3159 prom_name[0] = 0; 3160 if (!strncmp(dev->name, "eth", 3)) { 3161 int i = simple_strtoul(dev->name + 3, NULL, 10); 3162 sprintf(prom_name, "-%d", i + 3); 3163 } 3164 printk(KERN_INFO "%s%s: Quattro HME (PCI/CheerIO) 10/100baseT Ethernet ", dev->name, prom_name); 3165 if (qpdev->vendor == PCI_VENDOR_ID_DEC && 3166 qpdev->device == PCI_DEVICE_ID_DEC_21153) 3167 printk("DEC 21153 PCI Bridge\n"); 3168 else 3169 printk("unknown bridge %04x.%04x\n", 3170 qpdev->vendor, qpdev->device); 3171 } 3172 3173 if (qfe_slot != -1) 3174 printk(KERN_INFO "%s: Quattro HME slot %d (PCI/CheerIO) 10/100baseT Ethernet ", 3175 dev->name, qfe_slot); 3176 else 3177 printk(KERN_INFO "%s: HAPPY MEAL (PCI/CheerIO) 10/100BaseT Ethernet ", 3178 dev->name); 3179 3180 for (i = 0; i < 6; i++) 3181 printk("%2.2x%c", dev->dev_addr[i], i == 5 ? ' ' : ':'); 3182 3183 printk("\n"); 3184 3185 return 0; 3186 3187err_out_iounmap: 3188 iounmap(hp->gregs); 3189 3190err_out_free_res: 3191 pci_release_regions(pdev); 3192 3193err_out_clear_quattro: 3194 if (qp != NULL) 3195 qp->happy_meals[qfe_slot] = NULL; 3196 3197 free_netdev(dev); 3198 3199err_out: 3200 return err; 3201} 3202 3203static void __devexit happy_meal_pci_remove(struct pci_dev *pdev) 3204{ 3205 struct happy_meal *hp = dev_get_drvdata(&pdev->dev); 3206 struct net_device *net_dev = hp->dev; 3207 3208 unregister_netdev(net_dev); 3209 3210 pci_free_consistent(hp->happy_dev, 3211 PAGE_SIZE, 3212 hp->happy_block, 3213 hp->hblock_dvma); 3214 iounmap(hp->gregs); 3215 pci_release_regions(hp->happy_dev); 3216 3217 free_netdev(net_dev); 3218 3219 dev_set_drvdata(&pdev->dev, NULL); 3220} 3221 3222static struct pci_device_id happymeal_pci_ids[] = { 3223 { PCI_DEVICE(PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_HAPPYMEAL) }, 3224 { } /* Terminating entry */ 3225}; 3226 3227MODULE_DEVICE_TABLE(pci, happymeal_pci_ids); 3228 3229static struct pci_driver hme_pci_driver = { 3230 .name = "hme", 3231 .id_table = happymeal_pci_ids, 3232 .probe = happy_meal_pci_probe, 3233 .remove = __devexit_p(happy_meal_pci_remove), 3234}; 3235 3236static int __init happy_meal_pci_init(void) 3237{ 3238 return pci_register_driver(&hme_pci_driver); 3239} 3240 3241static void happy_meal_pci_exit(void) 3242{ 3243 pci_unregister_driver(&hme_pci_driver); 3244 3245 while (qfe_pci_list) { 3246 struct quattro *qfe = qfe_pci_list; 3247 struct quattro *next = qfe->next; 3248 3249 kfree(qfe); 3250 3251 qfe_pci_list = next; 3252 } 3253} 3254 3255#endif 3256 3257#ifdef CONFIG_SBUS 3258static int __devinit hme_sbus_probe(struct of_device *dev, const struct of_device_id *match) 3259{ 3260 struct sbus_dev *sdev = to_sbus_device(&dev->dev); 3261 struct device_node *dp = dev->node; 3262 const char *model = of_get_property(dp, "model", NULL); 3263 int is_qfe = (match->data != NULL); 3264 3265 if (!is_qfe && model && !strcmp(model, "SUNW,sbus-qfe")) 3266 is_qfe = 1; 3267 3268 return happy_meal_sbus_probe_one(sdev, is_qfe); 3269} 3270 3271static int __devexit hme_sbus_remove(struct of_device *dev) 3272{ 3273 struct happy_meal *hp = dev_get_drvdata(&dev->dev); 3274 struct net_device *net_dev = hp->dev; 3275 3276 unregister_netdev(net_dev); 3277 3278 3279 sbus_iounmap(hp->gregs, GREG_REG_SIZE); 3280 sbus_iounmap(hp->etxregs, ETX_REG_SIZE); 3281 sbus_iounmap(hp->erxregs, ERX_REG_SIZE); 3282 sbus_iounmap(hp->bigmacregs, BMAC_REG_SIZE); 3283 sbus_iounmap(hp->tcvregs, TCVR_REG_SIZE); 3284 sbus_free_consistent(hp->happy_dev, 3285 PAGE_SIZE, 3286 hp->happy_block, 3287 hp->hblock_dvma); 3288 3289 free_netdev(net_dev); 3290 3291 dev_set_drvdata(&dev->dev, NULL); 3292 3293 return 0; 3294} 3295 3296static struct of_device_id hme_sbus_match[] = { 3297 { 3298 .name = "SUNW,hme", 3299 }, 3300 { 3301 .name = "SUNW,qfe", 3302 .data = (void *) 1, 3303 }, 3304 { 3305 .name = "qfe", 3306 .data = (void *) 1, 3307 }, 3308 {}, 3309}; 3310 3311MODULE_DEVICE_TABLE(of, hme_sbus_match); 3312 3313static struct of_platform_driver hme_sbus_driver = { 3314 .name = "hme", 3315 .match_table = hme_sbus_match, 3316 .probe = hme_sbus_probe, 3317 .remove = __devexit_p(hme_sbus_remove), 3318}; 3319 3320static int __init happy_meal_sbus_init(void) 3321{ 3322 int err; 3323 3324 err = of_register_driver(&hme_sbus_driver, &sbus_bus_type); 3325 if (!err) 3326 quattro_sbus_register_irqs(); 3327 3328 return err; 3329} 3330 3331static void happy_meal_sbus_exit(void) 3332{ 3333 of_unregister_driver(&hme_sbus_driver); 3334 quattro_sbus_free_irqs(); 3335 3336 while (qfe_sbus_list) { 3337 struct quattro *qfe = qfe_sbus_list; 3338 struct quattro *next = qfe->next; 3339 3340 kfree(qfe); 3341 3342 qfe_sbus_list = next; 3343 } 3344} 3345#endif 3346 3347static int __init happy_meal_probe(void) 3348{ 3349 int err = 0; 3350 3351#ifdef CONFIG_SBUS 3352 err = happy_meal_sbus_init(); 3353#endif 3354#ifdef CONFIG_PCI 3355 if (!err) { 3356 err = happy_meal_pci_init(); 3357#ifdef CONFIG_SBUS 3358 if (err) 3359 happy_meal_sbus_exit(); 3360#endif 3361 } 3362#endif 3363 3364 return err; 3365} 3366 3367 3368static void __exit happy_meal_exit(void) 3369{ 3370#ifdef CONFIG_SBUS 3371 happy_meal_sbus_exit(); 3372#endif 3373#ifdef CONFIG_PCI 3374 happy_meal_pci_exit(); 3375#endif 3376} 3377 3378module_init(happy_meal_probe); 3379module_exit(happy_meal_exit); 3380