1/*------------------------------------------------------------------------ 2 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device. 3 . 4 . Copyright (C) 1996 by Erik Stahlman 5 . Copyright (C) 2001 Standard Microsystems Corporation 6 . Developed by Simple Network Magic Corporation 7 . Copyright (C) 2003 Monta Vista Software, Inc. 8 . Unified SMC91x driver by Nicolas Pitre 9 . 10 . This program is free software; you can redistribute it and/or modify 11 . it under the terms of the GNU General Public License as published by 12 . the Free Software Foundation; either version 2 of the License, or 13 . (at your option) any later version. 14 . 15 . This program is distributed in the hope that it will be useful, 16 . but WITHOUT ANY WARRANTY; without even the implied warranty of 17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 . GNU General Public License for more details. 19 . 20 . You should have received a copy of the GNU General Public License 21 . along with this program; if not, write to the Free Software 22 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 . 24 . Information contained in this file was obtained from the LAN91C111 25 . manual from SMC. To get a copy, if you really want one, you can find 26 . information under www.smsc.com. 27 . 28 . Authors 29 . Erik Stahlman <erik@vt.edu> 30 . Daris A Nevil <dnevil@snmc.com> 31 . Nicolas Pitre <nico@cam.org> 32 . 33 ---------------------------------------------------------------------------*/ 34#ifndef _SMC91X_H_ 35#define _SMC91X_H_ 36 37 38/* 39 * Define your architecture specific bus configuration parameters here. 40 */ 41 42#if defined(CONFIG_ARCH_LUBBOCK) 43 44/* We can only do 16-bit reads and writes in the static memory space. */ 45#define SMC_CAN_USE_8BIT 0 46#define SMC_CAN_USE_16BIT 1 47#define SMC_CAN_USE_32BIT 0 48#define SMC_NOWAIT 1 49 50/* The first two address lines aren't connected... */ 51#define SMC_IO_SHIFT 2 52 53#define SMC_inw(a, r) readw((a) + (r)) 54#define SMC_outw(v, a, r) writew(v, (a) + (r)) 55#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) 56#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) 57 58#elif defined(CONFIG_BFIN) 59 60#define SMC_IRQ_FLAGS IRQF_TRIGGER_HIGH 61#define RPC_LSA_DEFAULT RPC_LED_100_10 62#define RPC_LSB_DEFAULT RPC_LED_TX_RX 63 64# if defined(CONFIG_BFIN561_EZKIT) 65#define SMC_CAN_USE_8BIT 0 66#define SMC_CAN_USE_16BIT 1 67#define SMC_CAN_USE_32BIT 1 68#define SMC_IO_SHIFT 0 69#define SMC_NOWAIT 1 70#define SMC_USE_BFIN_DMA 0 71 72 73#define SMC_inw(a, r) readw((a) + (r)) 74#define SMC_outw(v, a, r) writew(v, (a) + (r)) 75#define SMC_inl(a, r) readl((a) + (r)) 76#define SMC_outl(v, a, r) writel(v, (a) + (r)) 77#define SMC_outsl(a, r, p, l) outsl((unsigned long *)((a) + (r)), p, l) 78#define SMC_insl(a, r, p, l) insl ((unsigned long *)((a) + (r)), p, l) 79# else 80#define SMC_CAN_USE_8BIT 0 81#define SMC_CAN_USE_16BIT 1 82#define SMC_CAN_USE_32BIT 0 83#define SMC_IO_SHIFT 0 84#define SMC_NOWAIT 1 85#define SMC_USE_BFIN_DMA 0 86 87 88#define SMC_inw(a, r) readw((a) + (r)) 89#define SMC_outw(v, a, r) writew(v, (a) + (r)) 90#define SMC_outsw(a, r, p, l) outsw((unsigned long *)((a) + (r)), p, l) 91#define SMC_insw(a, r, p, l) insw ((unsigned long *)((a) + (r)), p, l) 92# endif 93/* check if the mac in reg is valid */ 94#define SMC_GET_MAC_ADDR(addr) \ 95 do { \ 96 unsigned int __v; \ 97 __v = SMC_inw(ioaddr, ADDR0_REG); \ 98 addr[0] = __v; addr[1] = __v >> 8; \ 99 __v = SMC_inw(ioaddr, ADDR1_REG); \ 100 addr[2] = __v; addr[3] = __v >> 8; \ 101 __v = SMC_inw(ioaddr, ADDR2_REG); \ 102 addr[4] = __v; addr[5] = __v >> 8; \ 103 if (*(u32 *)(&addr[0]) == 0xFFFFFFFF) { \ 104 random_ether_addr(addr); \ 105 } \ 106 } while (0) 107#elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6) 108 109/* We can only do 16-bit reads and writes in the static memory space. */ 110#define SMC_CAN_USE_8BIT 0 111#define SMC_CAN_USE_16BIT 1 112#define SMC_CAN_USE_32BIT 0 113#define SMC_NOWAIT 1 114 115#define SMC_IO_SHIFT 0 116 117#define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r))) 118#define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v) 119#define SMC_insw(a, r, p, l) \ 120 do { \ 121 unsigned long __port = (a) + (r); \ 122 u16 *__p = (u16 *)(p); \ 123 int __l = (l); \ 124 insw(__port, __p, __l); \ 125 while (__l > 0) { \ 126 *__p = swab16(*__p); \ 127 __p++; \ 128 __l--; \ 129 } \ 130 } while (0) 131#define SMC_outsw(a, r, p, l) \ 132 do { \ 133 unsigned long __port = (a) + (r); \ 134 u16 *__p = (u16 *)(p); \ 135 int __l = (l); \ 136 while (__l > 0) { \ 137 /* Believe it or not, the swab isn't needed. */ \ 138 outw( /* swab16 */ (*__p++), __port); \ 139 __l--; \ 140 } \ 141 } while (0) 142#define SMC_IRQ_FLAGS (0) 143 144#elif defined(CONFIG_SA1100_PLEB) 145/* We can only do 16-bit reads and writes in the static memory space. */ 146#define SMC_CAN_USE_8BIT 1 147#define SMC_CAN_USE_16BIT 1 148#define SMC_CAN_USE_32BIT 0 149#define SMC_IO_SHIFT 0 150#define SMC_NOWAIT 1 151 152#define SMC_inb(a, r) readb((a) + (r)) 153#define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l)) 154#define SMC_inw(a, r) readw((a) + (r)) 155#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) 156#define SMC_outb(v, a, r) writeb(v, (a) + (r)) 157#define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l)) 158#define SMC_outw(v, a, r) writew(v, (a) + (r)) 159#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) 160 161#define SMC_IRQ_FLAGS (0) 162 163#elif defined(CONFIG_SA1100_ASSABET) 164 165#include <asm/arch/neponset.h> 166 167/* We can only do 8-bit reads and writes in the static memory space. */ 168#define SMC_CAN_USE_8BIT 1 169#define SMC_CAN_USE_16BIT 0 170#define SMC_CAN_USE_32BIT 0 171#define SMC_NOWAIT 1 172 173/* The first two address lines aren't connected... */ 174#define SMC_IO_SHIFT 2 175 176#define SMC_inb(a, r) readb((a) + (r)) 177#define SMC_outb(v, a, r) writeb(v, (a) + (r)) 178#define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l)) 179#define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l)) 180 181#elif defined(CONFIG_MACH_LOGICPD_PXA270) 182 183#define SMC_CAN_USE_8BIT 0 184#define SMC_CAN_USE_16BIT 1 185#define SMC_CAN_USE_32BIT 0 186#define SMC_IO_SHIFT 0 187#define SMC_NOWAIT 1 188 189#define SMC_inw(a, r) readw((a) + (r)) 190#define SMC_outw(v, a, r) writew(v, (a) + (r)) 191#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) 192#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) 193 194#elif defined(CONFIG_ARCH_INNOKOM) || \ 195 defined(CONFIG_MACH_MAINSTONE) || \ 196 defined(CONFIG_ARCH_PXA_IDP) || \ 197 defined(CONFIG_ARCH_RAMSES) 198 199#define SMC_CAN_USE_8BIT 1 200#define SMC_CAN_USE_16BIT 1 201#define SMC_CAN_USE_32BIT 1 202#define SMC_IO_SHIFT 0 203#define SMC_NOWAIT 1 204#define SMC_USE_PXA_DMA 1 205 206#define SMC_inb(a, r) readb((a) + (r)) 207#define SMC_inw(a, r) readw((a) + (r)) 208#define SMC_inl(a, r) readl((a) + (r)) 209#define SMC_outb(v, a, r) writeb(v, (a) + (r)) 210#define SMC_outl(v, a, r) writel(v, (a) + (r)) 211#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) 212#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) 213 214/* We actually can't write halfwords properly if not word aligned */ 215static inline void 216SMC_outw(u16 val, void __iomem *ioaddr, int reg) 217{ 218 if (reg & 2) { 219 unsigned int v = val << 16; 220 v |= readl(ioaddr + (reg & ~2)) & 0xffff; 221 writel(v, ioaddr + (reg & ~2)); 222 } else { 223 writew(val, ioaddr + reg); 224 } 225} 226 227#elif defined(CONFIG_ARCH_OMAP) 228 229/* We can only do 16-bit reads and writes in the static memory space. */ 230#define SMC_CAN_USE_8BIT 0 231#define SMC_CAN_USE_16BIT 1 232#define SMC_CAN_USE_32BIT 0 233#define SMC_IO_SHIFT 0 234#define SMC_NOWAIT 1 235 236#define SMC_inw(a, r) readw((a) + (r)) 237#define SMC_outw(v, a, r) writew(v, (a) + (r)) 238#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) 239#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) 240 241#include <asm/mach-types.h> 242#include <asm/arch/cpu.h> 243 244#define SMC_IRQ_FLAGS (( \ 245 machine_is_omap_h2() \ 246 || machine_is_omap_h3() \ 247 || machine_is_omap_h4() \ 248 || (machine_is_omap_innovator() && !cpu_is_omap1510()) \ 249 ) ? IRQF_TRIGGER_FALLING : IRQF_TRIGGER_RISING) 250 251 252#elif defined(CONFIG_SH_SH4202_MICRODEV) 253 254#define SMC_CAN_USE_8BIT 0 255#define SMC_CAN_USE_16BIT 1 256#define SMC_CAN_USE_32BIT 0 257 258#define SMC_inb(a, r) inb((a) + (r) - 0xa0000000) 259#define SMC_inw(a, r) inw((a) + (r) - 0xa0000000) 260#define SMC_inl(a, r) inl((a) + (r) - 0xa0000000) 261#define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000) 262#define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000) 263#define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000) 264#define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l) 265#define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l) 266#define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l) 267#define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l) 268 269#define SMC_IRQ_FLAGS (0) 270 271#elif defined(CONFIG_ISA) 272 273#define SMC_CAN_USE_8BIT 1 274#define SMC_CAN_USE_16BIT 1 275#define SMC_CAN_USE_32BIT 0 276 277#define SMC_inb(a, r) inb((a) + (r)) 278#define SMC_inw(a, r) inw((a) + (r)) 279#define SMC_outb(v, a, r) outb(v, (a) + (r)) 280#define SMC_outw(v, a, r) outw(v, (a) + (r)) 281#define SMC_insw(a, r, p, l) insw((a) + (r), p, l) 282#define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l) 283 284#elif defined(CONFIG_SUPERH) 285 286#ifdef CONFIG_SOLUTION_ENGINE 287#define SMC_CAN_USE_8BIT 0 288#define SMC_CAN_USE_16BIT 1 289#define SMC_CAN_USE_32BIT 0 290#define SMC_IO_SHIFT 0 291#define SMC_NOWAIT 1 292 293#define SMC_inw(a, r) inw((a) + (r)) 294#define SMC_outw(v, a, r) outw(v, (a) + (r)) 295#define SMC_insw(a, r, p, l) insw((a) + (r), p, l) 296#define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l) 297 298#else /* BOARDS */ 299 300#define SMC_CAN_USE_8BIT 1 301#define SMC_CAN_USE_16BIT 1 302#define SMC_CAN_USE_32BIT 1 303 304#define SMC_inb(a, r) inb((a) + (r)) 305#define SMC_inw(a, r) inw((a) + (r)) 306#define SMC_outb(v, a, r) outb(v, (a) + (r)) 307#define SMC_outw(v, a, r) outw(v, (a) + (r)) 308#define SMC_insw(a, r, p, l) insw((a) + (r), p, l) 309#define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l) 310 311#endif /* BOARDS */ 312 313#define set_irq_type(irq, type) do {} while (0) 314 315#elif defined(CONFIG_M32R) 316 317#define SMC_CAN_USE_8BIT 0 318#define SMC_CAN_USE_16BIT 1 319#define SMC_CAN_USE_32BIT 0 320 321#define SMC_inb(a, r) inb(((u32)a) + (r)) 322#define SMC_inw(a, r) inw(((u32)a) + (r)) 323#define SMC_outb(v, a, r) outb(v, ((u32)a) + (r)) 324#define SMC_outw(v, a, r) outw(v, ((u32)a) + (r)) 325#define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l) 326#define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l) 327 328#define SMC_IRQ_FLAGS (0) 329 330#define RPC_LSA_DEFAULT RPC_LED_TX_RX 331#define RPC_LSB_DEFAULT RPC_LED_100_10 332 333#elif defined(CONFIG_MACH_LPD79520) \ 334 || defined(CONFIG_MACH_LPD7A400) \ 335 || defined(CONFIG_MACH_LPD7A404) 336 337/* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the 338 * way that the CPU handles chip selects and the way that the SMC chip 339 * expects the chip select to operate. Refer to 340 * Documentation/arm/Sharp-LH/IOBarrier for details. The read from 341 * IOBARRIER is a byte, in order that we read the least-common 342 * denominator. It would be wasteful to read 32 bits from an 8-bit 343 * accessible region. 344 * 345 * There is no explicit protection against interrupts intervening 346 * between the writew and the IOBARRIER. In SMC ISR there is a 347 * preamble that performs an IOBARRIER in the extremely unlikely event 348 * that the driver interrupts itself between a writew to the chip an 349 * the IOBARRIER that follows *and* the cache is large enough that the 350 * first off-chip access while handing the interrupt is to the SMC 351 * chip. Other devices in the same address space as the SMC chip must 352 * be aware of the potential for trouble and perform a similar 353 * IOBARRIER on entry to their ISR. 354 */ 355 356#include <asm/arch/constants.h> /* IOBARRIER_VIRT */ 357 358#define SMC_CAN_USE_8BIT 0 359#define SMC_CAN_USE_16BIT 1 360#define SMC_CAN_USE_32BIT 0 361#define SMC_NOWAIT 0 362#define LPD7X_IOBARRIER readb (IOBARRIER_VIRT) 363 364#define SMC_inw(a,r)\ 365 ({ unsigned short v = readw ((void*) ((a) + (r))); LPD7X_IOBARRIER; v; }) 366#define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7X_IOBARRIER; }) 367 368#define SMC_insw LPD7_SMC_insw 369static inline void LPD7_SMC_insw (unsigned char* a, int r, 370 unsigned char* p, int l) 371{ 372 unsigned short* ps = (unsigned short*) p; 373 while (l-- > 0) { 374 *ps++ = readw (a + r); 375 LPD7X_IOBARRIER; 376 } 377} 378 379#define SMC_outsw LPD7_SMC_outsw 380static inline void LPD7_SMC_outsw (unsigned char* a, int r, 381 unsigned char* p, int l) 382{ 383 unsigned short* ps = (unsigned short*) p; 384 while (l-- > 0) { 385 writew (*ps++, a + r); 386 LPD7X_IOBARRIER; 387 } 388} 389 390#define SMC_INTERRUPT_PREAMBLE LPD7X_IOBARRIER 391 392#define RPC_LSA_DEFAULT RPC_LED_TX_RX 393#define RPC_LSB_DEFAULT RPC_LED_100_10 394 395#elif defined(CONFIG_SOC_AU1X00) 396 397#include <au1xxx.h> 398 399/* We can only do 16-bit reads and writes in the static memory space. */ 400#define SMC_CAN_USE_8BIT 0 401#define SMC_CAN_USE_16BIT 1 402#define SMC_CAN_USE_32BIT 0 403#define SMC_IO_SHIFT 0 404#define SMC_NOWAIT 1 405 406#define SMC_inw(a, r) au_readw((unsigned long)((a) + (r))) 407#define SMC_insw(a, r, p, l) \ 408 do { \ 409 unsigned long _a = (unsigned long)((a) + (r)); \ 410 int _l = (l); \ 411 u16 *_p = (u16 *)(p); \ 412 while (_l-- > 0) \ 413 *_p++ = au_readw(_a); \ 414 } while(0) 415#define SMC_outw(v, a, r) au_writew(v, (unsigned long)((a) + (r))) 416#define SMC_outsw(a, r, p, l) \ 417 do { \ 418 unsigned long _a = (unsigned long)((a) + (r)); \ 419 int _l = (l); \ 420 const u16 *_p = (const u16 *)(p); \ 421 while (_l-- > 0) \ 422 au_writew(*_p++ , _a); \ 423 } while(0) 424 425#define SMC_IRQ_FLAGS (0) 426 427#elif defined(CONFIG_ARCH_VERSATILE) 428 429#define SMC_CAN_USE_8BIT 1 430#define SMC_CAN_USE_16BIT 1 431#define SMC_CAN_USE_32BIT 1 432#define SMC_NOWAIT 1 433 434#define SMC_inb(a, r) readb((a) + (r)) 435#define SMC_inw(a, r) readw((a) + (r)) 436#define SMC_inl(a, r) readl((a) + (r)) 437#define SMC_outb(v, a, r) writeb(v, (a) + (r)) 438#define SMC_outw(v, a, r) writew(v, (a) + (r)) 439#define SMC_outl(v, a, r) writel(v, (a) + (r)) 440#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) 441#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) 442 443#define SMC_IRQ_FLAGS (0) 444 445#else 446 447#define SMC_CAN_USE_8BIT 1 448#define SMC_CAN_USE_16BIT 1 449#define SMC_CAN_USE_32BIT 1 450#define SMC_NOWAIT 1 451 452#define SMC_inb(a, r) readb((a) + (r)) 453#define SMC_inw(a, r) readw((a) + (r)) 454#define SMC_inl(a, r) readl((a) + (r)) 455#define SMC_outb(v, a, r) writeb(v, (a) + (r)) 456#define SMC_outw(v, a, r) writew(v, (a) + (r)) 457#define SMC_outl(v, a, r) writel(v, (a) + (r)) 458#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) 459#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) 460 461#define RPC_LSA_DEFAULT RPC_LED_100_10 462#define RPC_LSB_DEFAULT RPC_LED_TX_RX 463 464#endif 465 466#ifdef SMC_USE_PXA_DMA 467/* 468 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is 469 * always happening in irq context so no need to worry about races. TX is 470 * different and probably not worth it for that reason, and not as critical 471 * as RX which can overrun memory and lose packets. 472 */ 473#include <linux/dma-mapping.h> 474#include <asm/dma.h> 475#include <asm/arch/pxa-regs.h> 476 477#ifdef SMC_insl 478#undef SMC_insl 479#define SMC_insl(a, r, p, l) \ 480 smc_pxa_dma_insl(a, lp->physaddr, r, dev->dma, p, l) 481static inline void 482smc_pxa_dma_insl(void __iomem *ioaddr, u_long physaddr, int reg, int dma, 483 u_char *buf, int len) 484{ 485 dma_addr_t dmabuf; 486 487 /* fallback if no DMA available */ 488 if (dma == (unsigned char)-1) { 489 readsl(ioaddr + reg, buf, len); 490 return; 491 } 492 493 /* 64 bit alignment is required for memory to memory DMA */ 494 if ((long)buf & 4) { 495 *((u32 *)buf) = SMC_inl(ioaddr, reg); 496 buf += 4; 497 len--; 498 } 499 500 len *= 4; 501 dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE); 502 DCSR(dma) = DCSR_NODESC; 503 DTADR(dma) = dmabuf; 504 DSADR(dma) = physaddr + reg; 505 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 | 506 DCMD_WIDTH4 | (DCMD_LENGTH & len)); 507 DCSR(dma) = DCSR_NODESC | DCSR_RUN; 508 while (!(DCSR(dma) & DCSR_STOPSTATE)) 509 cpu_relax(); 510 DCSR(dma) = 0; 511 dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE); 512} 513#endif 514 515#ifdef SMC_insw 516#undef SMC_insw 517#define SMC_insw(a, r, p, l) \ 518 smc_pxa_dma_insw(a, lp->physaddr, r, dev->dma, p, l) 519static inline void 520smc_pxa_dma_insw(void __iomem *ioaddr, u_long physaddr, int reg, int dma, 521 u_char *buf, int len) 522{ 523 dma_addr_t dmabuf; 524 525 /* fallback if no DMA available */ 526 if (dma == (unsigned char)-1) { 527 readsw(ioaddr + reg, buf, len); 528 return; 529 } 530 531 /* 64 bit alignment is required for memory to memory DMA */ 532 while ((long)buf & 6) { 533 *((u16 *)buf) = SMC_inw(ioaddr, reg); 534 buf += 2; 535 len--; 536 } 537 538 len *= 2; 539 dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE); 540 DCSR(dma) = DCSR_NODESC; 541 DTADR(dma) = dmabuf; 542 DSADR(dma) = physaddr + reg; 543 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 | 544 DCMD_WIDTH2 | (DCMD_LENGTH & len)); 545 DCSR(dma) = DCSR_NODESC | DCSR_RUN; 546 while (!(DCSR(dma) & DCSR_STOPSTATE)) 547 cpu_relax(); 548 DCSR(dma) = 0; 549 dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE); 550} 551#endif 552 553static void 554smc_pxa_dma_irq(int dma, void *dummy) 555{ 556 DCSR(dma) = 0; 557} 558#endif /* SMC_USE_PXA_DMA */ 559 560 561/* 562 * Everything a particular hardware setup needs should have been defined 563 * at this point. Add stubs for the undefined cases, mainly to avoid 564 * compilation warnings since they'll be optimized away, or to prevent buggy 565 * use of them. 566 */ 567 568#if ! SMC_CAN_USE_32BIT 569#define SMC_inl(ioaddr, reg) ({ BUG(); 0; }) 570#define SMC_outl(x, ioaddr, reg) BUG() 571#define SMC_insl(a, r, p, l) BUG() 572#define SMC_outsl(a, r, p, l) BUG() 573#endif 574 575#if !defined(SMC_insl) || !defined(SMC_outsl) 576#define SMC_insl(a, r, p, l) BUG() 577#define SMC_outsl(a, r, p, l) BUG() 578#endif 579 580#if ! SMC_CAN_USE_16BIT 581 582/* 583 * Any 16-bit access is performed with two 8-bit accesses if the hardware 584 * can't do it directly. Most registers are 16-bit so those are mandatory. 585 */ 586#define SMC_outw(x, ioaddr, reg) \ 587 do { \ 588 unsigned int __val16 = (x); \ 589 SMC_outb( __val16, ioaddr, reg ); \ 590 SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\ 591 } while (0) 592#define SMC_inw(ioaddr, reg) \ 593 ({ \ 594 unsigned int __val16; \ 595 __val16 = SMC_inb( ioaddr, reg ); \ 596 __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \ 597 __val16; \ 598 }) 599 600#define SMC_insw(a, r, p, l) BUG() 601#define SMC_outsw(a, r, p, l) BUG() 602 603#endif 604 605#if !defined(SMC_insw) || !defined(SMC_outsw) 606#define SMC_insw(a, r, p, l) BUG() 607#define SMC_outsw(a, r, p, l) BUG() 608#endif 609 610#if ! SMC_CAN_USE_8BIT 611#define SMC_inb(ioaddr, reg) ({ BUG(); 0; }) 612#define SMC_outb(x, ioaddr, reg) BUG() 613#define SMC_insb(a, r, p, l) BUG() 614#define SMC_outsb(a, r, p, l) BUG() 615#endif 616 617#if !defined(SMC_insb) || !defined(SMC_outsb) 618#define SMC_insb(a, r, p, l) BUG() 619#define SMC_outsb(a, r, p, l) BUG() 620#endif 621 622#ifndef SMC_CAN_USE_DATACS 623#define SMC_CAN_USE_DATACS 0 624#endif 625 626#ifndef SMC_IO_SHIFT 627#define SMC_IO_SHIFT 0 628#endif 629 630#ifndef SMC_IRQ_FLAGS 631#define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING 632#endif 633 634#ifndef SMC_INTERRUPT_PREAMBLE 635#define SMC_INTERRUPT_PREAMBLE 636#endif 637 638 639/* Because of bank switching, the LAN91x uses only 16 I/O ports */ 640#define SMC_IO_EXTENT (16 << SMC_IO_SHIFT) 641#define SMC_DATA_EXTENT (4) 642 643/* 644 . Bank Select Register: 645 . 646 . yyyy yyyy 0000 00xx 647 . xx = bank number 648 . yyyy yyyy = 0x33, for identification purposes. 649*/ 650#define BANK_SELECT (14 << SMC_IO_SHIFT) 651 652 653// Transmit Control Register 654/* BANK 0 */ 655#define TCR_REG SMC_REG(0x0000, 0) 656#define TCR_ENABLE 0x0001 // When 1 we can transmit 657#define TCR_LOOP 0x0002 // Controls output pin LBK 658#define TCR_FORCOL 0x0004 // When 1 will force a collision 659#define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0 660#define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames 661#define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier 662#define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation 663#define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error 664#define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback 665#define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode 666 667#define TCR_CLEAR 0 /* do NOTHING */ 668/* the default settings for the TCR register : */ 669#define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN) 670 671 672// EPH Status Register 673/* BANK 0 */ 674#define EPH_STATUS_REG SMC_REG(0x0002, 0) 675#define ES_TX_SUC 0x0001 // Last TX was successful 676#define ES_SNGL_COL 0x0002 // Single collision detected for last tx 677#define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx 678#define ES_LTX_MULT 0x0008 // Last tx was a multicast 679#define ES_16COL 0x0010 // 16 Collisions Reached 680#define ES_SQET 0x0020 // Signal Quality Error Test 681#define ES_LTXBRD 0x0040 // Last tx was a broadcast 682#define ES_TXDEFR 0x0080 // Transmit Deferred 683#define ES_LATCOL 0x0200 // Late collision detected on last tx 684#define ES_LOSTCARR 0x0400 // Lost Carrier Sense 685#define ES_EXC_DEF 0x0800 // Excessive Deferral 686#define ES_CTR_ROL 0x1000 // Counter Roll Over indication 687#define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin 688#define ES_TXUNRN 0x8000 // Tx Underrun 689 690 691// Receive Control Register 692/* BANK 0 */ 693#define RCR_REG SMC_REG(0x0004, 0) 694#define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted 695#define RCR_PRMS 0x0002 // Enable promiscuous mode 696#define RCR_ALMUL 0x0004 // When set accepts all multicast frames 697#define RCR_RXEN 0x0100 // IFF this is set, we can receive packets 698#define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets 699#define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision 700#define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier 701#define RCR_SOFTRST 0x8000 // resets the chip 702 703/* the normal settings for the RCR register : */ 704#define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN) 705#define RCR_CLEAR 0x0 // set it to a base state 706 707 708// Counter Register 709/* BANK 0 */ 710#define COUNTER_REG SMC_REG(0x0006, 0) 711 712 713// Memory Information Register 714/* BANK 0 */ 715#define MIR_REG SMC_REG(0x0008, 0) 716 717 718// Receive/Phy Control Register 719/* BANK 0 */ 720#define RPC_REG SMC_REG(0x000A, 0) 721#define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode. 722#define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode 723#define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode 724#define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb 725#define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb 726#define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect 727#define RPC_LED_RES (0x01) // LED = Reserved 728#define RPC_LED_10 (0x02) // LED = 10Mbps link detect 729#define RPC_LED_FD (0x03) // LED = Full Duplex Mode 730#define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred 731#define RPC_LED_100 (0x05) // LED = 100Mbps link dectect 732#define RPC_LED_TX (0x06) // LED = TX packet occurred 733#define RPC_LED_RX (0x07) // LED = RX packet occurred 734 735#ifndef RPC_LSA_DEFAULT 736#define RPC_LSA_DEFAULT RPC_LED_100 737#endif 738#ifndef RPC_LSB_DEFAULT 739#define RPC_LSB_DEFAULT RPC_LED_FD 740#endif 741 742#define RPC_DEFAULT (RPC_ANEG | (RPC_LSA_DEFAULT << RPC_LSXA_SHFT) | (RPC_LSB_DEFAULT << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX) 743 744 745/* Bank 0 0x0C is reserved */ 746 747// Bank Select Register 748/* All Banks */ 749#define BSR_REG 0x000E 750 751 752// Configuration Reg 753/* BANK 1 */ 754#define CONFIG_REG SMC_REG(0x0000, 1) 755#define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy 756#define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL 757#define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus 758#define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode. 759 760// Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low 761#define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN) 762 763 764// Base Address Register 765/* BANK 1 */ 766#define BASE_REG SMC_REG(0x0002, 1) 767 768 769// Individual Address Registers 770/* BANK 1 */ 771#define ADDR0_REG SMC_REG(0x0004, 1) 772#define ADDR1_REG SMC_REG(0x0006, 1) 773#define ADDR2_REG SMC_REG(0x0008, 1) 774 775 776// General Purpose Register 777/* BANK 1 */ 778#define GP_REG SMC_REG(0x000A, 1) 779 780 781// Control Register 782/* BANK 1 */ 783#define CTL_REG SMC_REG(0x000C, 1) 784#define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received 785#define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically 786#define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt 787#define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt 788#define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt 789#define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store 790#define CTL_RELOAD 0x0002 // When set reads EEPROM into registers 791#define CTL_STORE 0x0001 // When set stores registers into EEPROM 792 793 794// MMU Command Register 795/* BANK 2 */ 796#define MMU_CMD_REG SMC_REG(0x0000, 2) 797#define MC_BUSY 1 // When 1 the last release has not completed 798#define MC_NOP (0<<5) // No Op 799#define MC_ALLOC (1<<5) // OR with number of 256 byte packets 800#define MC_RESET (2<<5) // Reset MMU to initial state 801#define MC_REMOVE (3<<5) // Remove the current rx packet 802#define MC_RELEASE (4<<5) // Remove and release the current rx packet 803#define MC_FREEPKT (5<<5) // Release packet in PNR register 804#define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit 805#define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs 806 807 808// Packet Number Register 809/* BANK 2 */ 810#define PN_REG SMC_REG(0x0002, 2) 811 812 813// Allocation Result Register 814/* BANK 2 */ 815#define AR_REG SMC_REG(0x0003, 2) 816#define AR_FAILED 0x80 // Alocation Failed 817 818 819// TX FIFO Ports Register 820/* BANK 2 */ 821#define TXFIFO_REG SMC_REG(0x0004, 2) 822#define TXFIFO_TEMPTY 0x80 // TX FIFO Empty 823 824// RX FIFO Ports Register 825/* BANK 2 */ 826#define RXFIFO_REG SMC_REG(0x0005, 2) 827#define RXFIFO_REMPTY 0x80 // RX FIFO Empty 828 829#define FIFO_REG SMC_REG(0x0004, 2) 830 831// Pointer Register 832/* BANK 2 */ 833#define PTR_REG SMC_REG(0x0006, 2) 834#define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area 835#define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access 836#define PTR_READ 0x2000 // When 1 the operation is a read 837 838 839// Data Register 840/* BANK 2 */ 841#define DATA_REG SMC_REG(0x0008, 2) 842 843 844// Interrupt Status/Acknowledge Register 845/* BANK 2 */ 846#define INT_REG SMC_REG(0x000C, 2) 847 848 849// Interrupt Mask Register 850/* BANK 2 */ 851#define IM_REG SMC_REG(0x000D, 2) 852#define IM_MDINT 0x80 // PHY MI Register 18 Interrupt 853#define IM_ERCV_INT 0x40 // Early Receive Interrupt 854#define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section 855#define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns 856#define IM_ALLOC_INT 0x08 // Set when allocation request is completed 857#define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty 858#define IM_TX_INT 0x02 // Transmit Interrupt 859#define IM_RCV_INT 0x01 // Receive Interrupt 860 861 862// Multicast Table Registers 863/* BANK 3 */ 864#define MCAST_REG1 SMC_REG(0x0000, 3) 865#define MCAST_REG2 SMC_REG(0x0002, 3) 866#define MCAST_REG3 SMC_REG(0x0004, 3) 867#define MCAST_REG4 SMC_REG(0x0006, 3) 868 869 870// Management Interface Register (MII) 871/* BANK 3 */ 872#define MII_REG SMC_REG(0x0008, 3) 873#define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup 874#define MII_MDOE 0x0008 // MII Output Enable 875#define MII_MCLK 0x0004 // MII Clock, pin MDCLK 876#define MII_MDI 0x0002 // MII Input, pin MDI 877#define MII_MDO 0x0001 // MII Output, pin MDO 878 879 880// Revision Register 881/* BANK 3 */ 882/* ( hi: chip id low: rev # ) */ 883#define REV_REG SMC_REG(0x000A, 3) 884 885 886// Early RCV Register 887/* BANK 3 */ 888/* this is NOT on SMC9192 */ 889#define ERCV_REG SMC_REG(0x000C, 3) 890#define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received 891#define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask 892 893 894// External Register 895/* BANK 7 */ 896#define EXT_REG SMC_REG(0x0000, 7) 897 898 899#define CHIP_9192 3 900#define CHIP_9194 4 901#define CHIP_9195 5 902#define CHIP_9196 6 903#define CHIP_91100 7 904#define CHIP_91100FD 8 905#define CHIP_91111FD 9 906 907static const char * chip_ids[ 16 ] = { 908 NULL, NULL, NULL, 909 /* 3 */ "SMC91C90/91C92", 910 /* 4 */ "SMC91C94", 911 /* 5 */ "SMC91C95", 912 /* 6 */ "SMC91C96", 913 /* 7 */ "SMC91C100", 914 /* 8 */ "SMC91C100FD", 915 /* 9 */ "SMC91C11xFD", 916 NULL, NULL, NULL, 917 NULL, NULL, NULL}; 918 919 920/* 921 . Receive status bits 922*/ 923#define RS_ALGNERR 0x8000 924#define RS_BRODCAST 0x4000 925#define RS_BADCRC 0x2000 926#define RS_ODDFRAME 0x1000 927#define RS_TOOLONG 0x0800 928#define RS_TOOSHORT 0x0400 929#define RS_MULTICAST 0x0001 930#define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) 931 932 933/* 934 * PHY IDs 935 * LAN83C183 == LAN91C111 Internal PHY 936 */ 937#define PHY_LAN83C183 0x0016f840 938#define PHY_LAN83C180 0x02821c50 939 940/* 941 * PHY Register Addresses (LAN91C111 Internal PHY) 942 * 943 * Generic PHY registers can be found in <linux/mii.h> 944 * 945 * These phy registers are specific to our on-board phy. 946 */ 947 948// PHY Configuration Register 1 949#define PHY_CFG1_REG 0x10 950#define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled 951#define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled 952#define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down 953#define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler 954#define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable 955#define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled 956#define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm) 957#define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db 958#define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust 959#define PHY_CFG1_TLVL_MASK 0x003C 960#define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time 961 962 963// PHY Configuration Register 2 964#define PHY_CFG2_REG 0x11 965#define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled 966#define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled 967#define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt) 968#define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo 969 970// PHY Status Output (and Interrupt status) Register 971#define PHY_INT_REG 0x12 // Status Output (Interrupt Status) 972#define PHY_INT_INT 0x8000 // 1=bits have changed since last read 973#define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected 974#define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync 975#define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx 976#define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx 977#define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx 978#define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected 979#define PHY_INT_JAB 0x0100 // 1=Jabber detected 980#define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode 981#define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex 982 983// PHY Interrupt/Status Mask Register 984#define PHY_MASK_REG 0x13 // Interrupt Mask 985// Uses the same bit definitions as PHY_INT_REG 986 987 988/* 989 * SMC91C96 ethernet config and status registers. 990 * These are in the "attribute" space. 991 */ 992#define ECOR 0x8000 993#define ECOR_RESET 0x80 994#define ECOR_LEVEL_IRQ 0x40 995#define ECOR_WR_ATTRIB 0x04 996#define ECOR_ENABLE 0x01 997 998#define ECSR 0x8002 999#define ECSR_IOIS8 0x20 1000#define ECSR_PWRDWN 0x04 1001#define ECSR_INT 0x02 1002 1003#define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT) 1004 1005 1006/* 1007 * Macros to abstract register access according to the data bus 1008 * capabilities. Please use those and not the in/out primitives. 1009 * Note: the following macros do *not* select the bank -- this must 1010 * be done separately as needed in the main code. The SMC_REG() macro 1011 * only uses the bank argument for debugging purposes (when enabled). 1012 * 1013 * Note: despite inline functions being safer, everything leading to this 1014 * should preferably be macros to let BUG() display the line number in 1015 * the core source code since we're interested in the top call site 1016 * not in any inline function location. 1017 */ 1018 1019#if SMC_DEBUG > 0 1020#define SMC_REG(reg, bank) \ 1021 ({ \ 1022 int __b = SMC_CURRENT_BANK(); \ 1023 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \ 1024 printk( "%s: bank reg screwed (0x%04x)\n", \ 1025 CARDNAME, __b ); \ 1026 BUG(); \ 1027 } \ 1028 reg<<SMC_IO_SHIFT; \ 1029 }) 1030#else 1031#define SMC_REG(reg, bank) (reg<<SMC_IO_SHIFT) 1032#endif 1033 1034/* 1035 * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not 1036 * aligned to a 32 bit boundary. I tell you that does exist! 1037 * Fortunately the affected register accesses can be easily worked around 1038 * since we can write zeroes to the preceeding 16 bits without adverse 1039 * effects and use a 32-bit access. 1040 * 1041 * Enforce it on any 32-bit capable setup for now. 1042 */ 1043#define SMC_MUST_ALIGN_WRITE SMC_CAN_USE_32BIT 1044 1045#define SMC_GET_PN() \ 1046 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, PN_REG)) \ 1047 : (SMC_inw(ioaddr, PN_REG) & 0xFF) ) 1048 1049#define SMC_SET_PN(x) \ 1050 do { \ 1051 if (SMC_MUST_ALIGN_WRITE) \ 1052 SMC_outl((x)<<16, ioaddr, SMC_REG(0, 2)); \ 1053 else if (SMC_CAN_USE_8BIT) \ 1054 SMC_outb(x, ioaddr, PN_REG); \ 1055 else \ 1056 SMC_outw(x, ioaddr, PN_REG); \ 1057 } while (0) 1058 1059#define SMC_GET_AR() \ 1060 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, AR_REG)) \ 1061 : (SMC_inw(ioaddr, PN_REG) >> 8) ) 1062 1063#define SMC_GET_TXFIFO() \ 1064 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, TXFIFO_REG)) \ 1065 : (SMC_inw(ioaddr, TXFIFO_REG) & 0xFF) ) 1066 1067#define SMC_GET_RXFIFO() \ 1068 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, RXFIFO_REG)) \ 1069 : (SMC_inw(ioaddr, TXFIFO_REG) >> 8) ) 1070 1071#define SMC_GET_INT() \ 1072 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, INT_REG)) \ 1073 : (SMC_inw(ioaddr, INT_REG) & 0xFF) ) 1074 1075#define SMC_ACK_INT(x) \ 1076 do { \ 1077 if (SMC_CAN_USE_8BIT) \ 1078 SMC_outb(x, ioaddr, INT_REG); \ 1079 else { \ 1080 unsigned long __flags; \ 1081 int __mask; \ 1082 local_irq_save(__flags); \ 1083 __mask = SMC_inw( ioaddr, INT_REG ) & ~0xff; \ 1084 SMC_outw( __mask | (x), ioaddr, INT_REG ); \ 1085 local_irq_restore(__flags); \ 1086 } \ 1087 } while (0) 1088 1089#define SMC_GET_INT_MASK() \ 1090 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, IM_REG)) \ 1091 : (SMC_inw( ioaddr, INT_REG ) >> 8) ) 1092 1093#define SMC_SET_INT_MASK(x) \ 1094 do { \ 1095 if (SMC_CAN_USE_8BIT) \ 1096 SMC_outb(x, ioaddr, IM_REG); \ 1097 else \ 1098 SMC_outw((x) << 8, ioaddr, INT_REG); \ 1099 } while (0) 1100 1101#define SMC_CURRENT_BANK() SMC_inw(ioaddr, BANK_SELECT) 1102 1103#define SMC_SELECT_BANK(x) \ 1104 do { \ 1105 if (SMC_MUST_ALIGN_WRITE) \ 1106 SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \ 1107 else \ 1108 SMC_outw(x, ioaddr, BANK_SELECT); \ 1109 } while (0) 1110 1111#define SMC_GET_BASE() SMC_inw(ioaddr, BASE_REG) 1112 1113#define SMC_SET_BASE(x) SMC_outw(x, ioaddr, BASE_REG) 1114 1115#define SMC_GET_CONFIG() SMC_inw(ioaddr, CONFIG_REG) 1116 1117#define SMC_SET_CONFIG(x) SMC_outw(x, ioaddr, CONFIG_REG) 1118 1119#define SMC_GET_COUNTER() SMC_inw(ioaddr, COUNTER_REG) 1120 1121#define SMC_GET_CTL() SMC_inw(ioaddr, CTL_REG) 1122 1123#define SMC_SET_CTL(x) SMC_outw(x, ioaddr, CTL_REG) 1124 1125#define SMC_GET_MII() SMC_inw(ioaddr, MII_REG) 1126 1127#define SMC_SET_MII(x) SMC_outw(x, ioaddr, MII_REG) 1128 1129#define SMC_GET_MIR() SMC_inw(ioaddr, MIR_REG) 1130 1131#define SMC_SET_MIR(x) SMC_outw(x, ioaddr, MIR_REG) 1132 1133#define SMC_GET_MMU_CMD() SMC_inw(ioaddr, MMU_CMD_REG) 1134 1135#define SMC_SET_MMU_CMD(x) SMC_outw(x, ioaddr, MMU_CMD_REG) 1136 1137#define SMC_GET_FIFO() SMC_inw(ioaddr, FIFO_REG) 1138 1139#define SMC_GET_PTR() SMC_inw(ioaddr, PTR_REG) 1140 1141#define SMC_SET_PTR(x) \ 1142 do { \ 1143 if (SMC_MUST_ALIGN_WRITE) \ 1144 SMC_outl((x)<<16, ioaddr, SMC_REG(4, 2)); \ 1145 else \ 1146 SMC_outw(x, ioaddr, PTR_REG); \ 1147 } while (0) 1148 1149#define SMC_GET_EPH_STATUS() SMC_inw(ioaddr, EPH_STATUS_REG) 1150 1151#define SMC_GET_RCR() SMC_inw(ioaddr, RCR_REG) 1152 1153#define SMC_SET_RCR(x) SMC_outw(x, ioaddr, RCR_REG) 1154 1155#define SMC_GET_REV() SMC_inw(ioaddr, REV_REG) 1156 1157#define SMC_GET_RPC() SMC_inw(ioaddr, RPC_REG) 1158 1159#define SMC_SET_RPC(x) \ 1160 do { \ 1161 if (SMC_MUST_ALIGN_WRITE) \ 1162 SMC_outl((x)<<16, ioaddr, SMC_REG(8, 0)); \ 1163 else \ 1164 SMC_outw(x, ioaddr, RPC_REG); \ 1165 } while (0) 1166 1167#define SMC_GET_TCR() SMC_inw(ioaddr, TCR_REG) 1168 1169#define SMC_SET_TCR(x) SMC_outw(x, ioaddr, TCR_REG) 1170 1171#ifndef SMC_GET_MAC_ADDR 1172#define SMC_GET_MAC_ADDR(addr) \ 1173 do { \ 1174 unsigned int __v; \ 1175 __v = SMC_inw( ioaddr, ADDR0_REG ); \ 1176 addr[0] = __v; addr[1] = __v >> 8; \ 1177 __v = SMC_inw( ioaddr, ADDR1_REG ); \ 1178 addr[2] = __v; addr[3] = __v >> 8; \ 1179 __v = SMC_inw( ioaddr, ADDR2_REG ); \ 1180 addr[4] = __v; addr[5] = __v >> 8; \ 1181 } while (0) 1182#endif 1183 1184#define SMC_SET_MAC_ADDR(addr) \ 1185 do { \ 1186 SMC_outw( addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG ); \ 1187 SMC_outw( addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG ); \ 1188 SMC_outw( addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG ); \ 1189 } while (0) 1190 1191#define SMC_SET_MCAST(x) \ 1192 do { \ 1193 const unsigned char *mt = (x); \ 1194 SMC_outw( mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1 ); \ 1195 SMC_outw( mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2 ); \ 1196 SMC_outw( mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3 ); \ 1197 SMC_outw( mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4 ); \ 1198 } while (0) 1199 1200#define SMC_PUT_PKT_HDR(status, length) \ 1201 do { \ 1202 if (SMC_CAN_USE_32BIT) \ 1203 SMC_outl((status) | (length)<<16, ioaddr, DATA_REG); \ 1204 else { \ 1205 SMC_outw(status, ioaddr, DATA_REG); \ 1206 SMC_outw(length, ioaddr, DATA_REG); \ 1207 } \ 1208 } while (0) 1209 1210#define SMC_GET_PKT_HDR(status, length) \ 1211 do { \ 1212 if (SMC_CAN_USE_32BIT) { \ 1213 unsigned int __val = SMC_inl(ioaddr, DATA_REG); \ 1214 (status) = __val & 0xffff; \ 1215 (length) = __val >> 16; \ 1216 } else { \ 1217 (status) = SMC_inw(ioaddr, DATA_REG); \ 1218 (length) = SMC_inw(ioaddr, DATA_REG); \ 1219 } \ 1220 } while (0) 1221 1222#define SMC_PUSH_DATA(p, l) \ 1223 do { \ 1224 if (SMC_CAN_USE_32BIT) { \ 1225 void *__ptr = (p); \ 1226 int __len = (l); \ 1227 void __iomem *__ioaddr = ioaddr; \ 1228 if (__len >= 2 && (unsigned long)__ptr & 2) { \ 1229 __len -= 2; \ 1230 SMC_outw(*(u16 *)__ptr, ioaddr, DATA_REG); \ 1231 __ptr += 2; \ 1232 } \ 1233 if (SMC_CAN_USE_DATACS && lp->datacs) \ 1234 __ioaddr = lp->datacs; \ 1235 SMC_outsl(__ioaddr, DATA_REG, __ptr, __len>>2); \ 1236 if (__len & 2) { \ 1237 __ptr += (__len & ~3); \ 1238 SMC_outw(*((u16 *)__ptr), ioaddr, DATA_REG); \ 1239 } \ 1240 } else if (SMC_CAN_USE_16BIT) \ 1241 SMC_outsw(ioaddr, DATA_REG, p, (l) >> 1); \ 1242 else if (SMC_CAN_USE_8BIT) \ 1243 SMC_outsb(ioaddr, DATA_REG, p, l); \ 1244 } while (0) 1245 1246#define SMC_PULL_DATA(p, l) \ 1247 do { \ 1248 if (SMC_CAN_USE_32BIT) { \ 1249 void *__ptr = (p); \ 1250 int __len = (l); \ 1251 void __iomem *__ioaddr = ioaddr; \ 1252 if ((unsigned long)__ptr & 2) { \ 1253 /* \ 1254 * We want 32bit alignment here. \ 1255 * Since some buses perform a full \ 1256 * 32bit fetch even for 16bit data \ 1257 * we can't use SMC_inw() here. \ 1258 * Back both source (on-chip) and \ 1259 * destination pointers of 2 bytes. \ 1260 * This is possible since the call to \ 1261 * SMC_GET_PKT_HDR() already advanced \ 1262 * the source pointer of 4 bytes, and \ 1263 * the skb_reserve(skb, 2) advanced \ 1264 * the destination pointer of 2 bytes. \ 1265 */ \ 1266 __ptr -= 2; \ 1267 __len += 2; \ 1268 SMC_SET_PTR(2|PTR_READ|PTR_RCV|PTR_AUTOINC); \ 1269 } \ 1270 if (SMC_CAN_USE_DATACS && lp->datacs) \ 1271 __ioaddr = lp->datacs; \ 1272 __len += 2; \ 1273 SMC_insl(__ioaddr, DATA_REG, __ptr, __len>>2); \ 1274 } else if (SMC_CAN_USE_16BIT) \ 1275 SMC_insw(ioaddr, DATA_REG, p, (l) >> 1); \ 1276 else if (SMC_CAN_USE_8BIT) \ 1277 SMC_insb(ioaddr, DATA_REG, p, l); \ 1278 } while (0) 1279 1280#endif /* _SMC91X_H_ */ 1281