1 2 3#include <linux/types.h> 4#include <linux/module.h> 5#include <linux/kernel.h> 6#include <linux/delay.h> 7#include <linux/timer.h> 8#include <linux/mm.h> 9#include <linux/ioport.h> 10#include <linux/blkdev.h> 11#include <linux/hdreg.h> 12 13#include <linux/interrupt.h> 14#include <linux/pci.h> 15#include <linux/init.h> 16#include <linux/ide.h> 17 18#include <asm/uaccess.h> 19#include <asm/io.h> 20#include <asm/irq.h> 21 22/* various tuning parameters */ 23#define HPT_RESET_STATE_ENGINE 24#undef HPT_DELAY_INTERRUPT 25#define HPT_SERIALIZE_IO 0 26 27static const char *quirk_drives[] = { 28 "QUANTUM FIREBALLlct08 08", 29 "QUANTUM FIREBALLP KA6.4", 30 "QUANTUM FIREBALLP LM20.4", 31 "QUANTUM FIREBALLP LM20.5", 32 NULL 33}; 34 35static const char *bad_ata100_5[] = { 36 "IBM-DTLA-307075", 37 "IBM-DTLA-307060", 38 "IBM-DTLA-307045", 39 "IBM-DTLA-307030", 40 "IBM-DTLA-307020", 41 "IBM-DTLA-307015", 42 "IBM-DTLA-305040", 43 "IBM-DTLA-305030", 44 "IBM-DTLA-305020", 45 "IC35L010AVER07-0", 46 "IC35L020AVER07-0", 47 "IC35L030AVER07-0", 48 "IC35L040AVER07-0", 49 "IC35L060AVER07-0", 50 "WDC AC310200R", 51 NULL 52}; 53 54static const char *bad_ata66_4[] = { 55 "IBM-DTLA-307075", 56 "IBM-DTLA-307060", 57 "IBM-DTLA-307045", 58 "IBM-DTLA-307030", 59 "IBM-DTLA-307020", 60 "IBM-DTLA-307015", 61 "IBM-DTLA-305040", 62 "IBM-DTLA-305030", 63 "IBM-DTLA-305020", 64 "IC35L010AVER07-0", 65 "IC35L020AVER07-0", 66 "IC35L030AVER07-0", 67 "IC35L040AVER07-0", 68 "IC35L060AVER07-0", 69 "WDC AC310200R", 70 "MAXTOR STM3320620A", 71 NULL 72}; 73 74static const char *bad_ata66_3[] = { 75 "WDC AC310200R", 76 NULL 77}; 78 79static const char *bad_ata33[] = { 80 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2", 81 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2", 82 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4", 83 "Maxtor 90510D4", 84 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2", 85 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4", 86 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2", 87 NULL 88}; 89 90static u8 xfer_speeds[] = { 91 XFER_UDMA_6, 92 XFER_UDMA_5, 93 XFER_UDMA_4, 94 XFER_UDMA_3, 95 XFER_UDMA_2, 96 XFER_UDMA_1, 97 XFER_UDMA_0, 98 99 XFER_MW_DMA_2, 100 XFER_MW_DMA_1, 101 XFER_MW_DMA_0, 102 103 XFER_PIO_4, 104 XFER_PIO_3, 105 XFER_PIO_2, 106 XFER_PIO_1, 107 XFER_PIO_0 108}; 109 110/* Key for bus clock timings 111 * 36x 37x 112 * bits bits 113 * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA. 114 * cycles = value + 1 115 * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA. 116 * cycles = value + 1 117 * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file 118 * register access. 119 * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file 120 * register access. 121 * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer. 122 * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock. 123 * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and 124 * MW DMA xfer. 125 * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for 126 * task file register access. 127 * 28 28 UDMA enable. 128 * 29 29 DMA enable. 129 * 30 30 PIO MST enable. If set, the chip is in bus master mode during 130 * PIO xfer. 131 * 31 31 FIFO enable. 132 */ 133 134static u32 forty_base_hpt36x[] = { 135 /* XFER_UDMA_6 */ 0x900fd943, 136 /* XFER_UDMA_5 */ 0x900fd943, 137 /* XFER_UDMA_4 */ 0x900fd943, 138 /* XFER_UDMA_3 */ 0x900ad943, 139 /* XFER_UDMA_2 */ 0x900bd943, 140 /* XFER_UDMA_1 */ 0x9008d943, 141 /* XFER_UDMA_0 */ 0x9008d943, 142 143 /* XFER_MW_DMA_2 */ 0xa008d943, 144 /* XFER_MW_DMA_1 */ 0xa010d955, 145 /* XFER_MW_DMA_0 */ 0xa010d9fc, 146 147 /* XFER_PIO_4 */ 0xc008d963, 148 /* XFER_PIO_3 */ 0xc010d974, 149 /* XFER_PIO_2 */ 0xc010d997, 150 /* XFER_PIO_1 */ 0xc010d9c7, 151 /* XFER_PIO_0 */ 0xc018d9d9 152}; 153 154static u32 thirty_three_base_hpt36x[] = { 155 /* XFER_UDMA_6 */ 0x90c9a731, 156 /* XFER_UDMA_5 */ 0x90c9a731, 157 /* XFER_UDMA_4 */ 0x90c9a731, 158 /* XFER_UDMA_3 */ 0x90cfa731, 159 /* XFER_UDMA_2 */ 0x90caa731, 160 /* XFER_UDMA_1 */ 0x90cba731, 161 /* XFER_UDMA_0 */ 0x90c8a731, 162 163 /* XFER_MW_DMA_2 */ 0xa0c8a731, 164 /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */ 165 /* XFER_MW_DMA_0 */ 0xa0c8a797, 166 167 /* XFER_PIO_4 */ 0xc0c8a731, 168 /* XFER_PIO_3 */ 0xc0c8a742, 169 /* XFER_PIO_2 */ 0xc0d0a753, 170 /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */ 171 /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */ 172}; 173 174static u32 twenty_five_base_hpt36x[] = { 175 /* XFER_UDMA_6 */ 0x90c98521, 176 /* XFER_UDMA_5 */ 0x90c98521, 177 /* XFER_UDMA_4 */ 0x90c98521, 178 /* XFER_UDMA_3 */ 0x90cf8521, 179 /* XFER_UDMA_2 */ 0x90cf8521, 180 /* XFER_UDMA_1 */ 0x90cb8521, 181 /* XFER_UDMA_0 */ 0x90cb8521, 182 183 /* XFER_MW_DMA_2 */ 0xa0ca8521, 184 /* XFER_MW_DMA_1 */ 0xa0ca8532, 185 /* XFER_MW_DMA_0 */ 0xa0ca8575, 186 187 /* XFER_PIO_4 */ 0xc0ca8521, 188 /* XFER_PIO_3 */ 0xc0ca8532, 189 /* XFER_PIO_2 */ 0xc0ca8542, 190 /* XFER_PIO_1 */ 0xc0d08572, 191 /* XFER_PIO_0 */ 0xc0d08585 192}; 193 194static u32 thirty_three_base_hpt37x[] = { 195 /* XFER_UDMA_6 */ 0x12446231, /* 0x12646231 ?? */ 196 /* XFER_UDMA_5 */ 0x12446231, 197 /* XFER_UDMA_4 */ 0x12446231, 198 /* XFER_UDMA_3 */ 0x126c6231, 199 /* XFER_UDMA_2 */ 0x12486231, 200 /* XFER_UDMA_1 */ 0x124c6233, 201 /* XFER_UDMA_0 */ 0x12506297, 202 203 /* XFER_MW_DMA_2 */ 0x22406c31, 204 /* XFER_MW_DMA_1 */ 0x22406c33, 205 /* XFER_MW_DMA_0 */ 0x22406c97, 206 207 /* XFER_PIO_4 */ 0x06414e31, 208 /* XFER_PIO_3 */ 0x06414e42, 209 /* XFER_PIO_2 */ 0x06414e53, 210 /* XFER_PIO_1 */ 0x06814e93, 211 /* XFER_PIO_0 */ 0x06814ea7 212}; 213 214static u32 fifty_base_hpt37x[] = { 215 /* XFER_UDMA_6 */ 0x12848242, 216 /* XFER_UDMA_5 */ 0x12848242, 217 /* XFER_UDMA_4 */ 0x12ac8242, 218 /* XFER_UDMA_3 */ 0x128c8242, 219 /* XFER_UDMA_2 */ 0x120c8242, 220 /* XFER_UDMA_1 */ 0x12148254, 221 /* XFER_UDMA_0 */ 0x121882ea, 222 223 /* XFER_MW_DMA_2 */ 0x22808242, 224 /* XFER_MW_DMA_1 */ 0x22808254, 225 /* XFER_MW_DMA_0 */ 0x228082ea, 226 227 /* XFER_PIO_4 */ 0x0a81f442, 228 /* XFER_PIO_3 */ 0x0a81f443, 229 /* XFER_PIO_2 */ 0x0a81f454, 230 /* XFER_PIO_1 */ 0x0ac1f465, 231 /* XFER_PIO_0 */ 0x0ac1f48a 232}; 233 234static u32 sixty_six_base_hpt37x[] = { 235 /* XFER_UDMA_6 */ 0x1c869c62, 236 /* XFER_UDMA_5 */ 0x1cae9c62, /* 0x1c8a9c62 */ 237 /* XFER_UDMA_4 */ 0x1c8a9c62, 238 /* XFER_UDMA_3 */ 0x1c8e9c62, 239 /* XFER_UDMA_2 */ 0x1c929c62, 240 /* XFER_UDMA_1 */ 0x1c9a9c62, 241 /* XFER_UDMA_0 */ 0x1c829c62, 242 243 /* XFER_MW_DMA_2 */ 0x2c829c62, 244 /* XFER_MW_DMA_1 */ 0x2c829c66, 245 /* XFER_MW_DMA_0 */ 0x2c829d2e, 246 247 /* XFER_PIO_4 */ 0x0c829c62, 248 /* XFER_PIO_3 */ 0x0c829c84, 249 /* XFER_PIO_2 */ 0x0c829ca6, 250 /* XFER_PIO_1 */ 0x0d029d26, 251 /* XFER_PIO_0 */ 0x0d029d5e 252}; 253 254#define HPT366_DEBUG_DRIVE_INFO 0 255#define HPT371_ALLOW_ATA133_6 1 256#define HPT302_ALLOW_ATA133_6 1 257#define HPT372_ALLOW_ATA133_6 1 258#define HPT370_ALLOW_ATA100_5 0 259#define HPT366_ALLOW_ATA66_4 1 260#define HPT366_ALLOW_ATA66_3 1 261#define HPT366_MAX_DEVS 8 262 263/* Supported ATA clock frequencies */ 264enum ata_clock { 265 ATA_CLOCK_25MHZ, 266 ATA_CLOCK_33MHZ, 267 ATA_CLOCK_40MHZ, 268 ATA_CLOCK_50MHZ, 269 ATA_CLOCK_66MHZ, 270 NUM_ATA_CLOCKS 271}; 272 273/* 274 * Hold all the HighPoint chip information in one place. 275 */ 276 277struct hpt_info { 278 u8 chip_type; /* Chip type */ 279 u8 max_mode; /* Speeds allowed */ 280 u8 dpll_clk; /* DPLL clock in MHz */ 281 u8 pci_clk; /* PCI clock in MHz */ 282 u32 **settings; /* Chipset settings table */ 283}; 284 285/* Supported HighPoint chips */ 286enum { 287 HPT36x, 288 HPT370, 289 HPT370A, 290 HPT374, 291 HPT372, 292 HPT372A, 293 HPT302, 294 HPT371, 295 HPT372N, 296 HPT302N, 297 HPT371N 298}; 299 300static u32 *hpt36x_settings[NUM_ATA_CLOCKS] = { 301 twenty_five_base_hpt36x, 302 thirty_three_base_hpt36x, 303 forty_base_hpt36x, 304 NULL, 305 NULL 306}; 307 308static u32 *hpt37x_settings[NUM_ATA_CLOCKS] = { 309 NULL, 310 thirty_three_base_hpt37x, 311 NULL, 312 fifty_base_hpt37x, 313 sixty_six_base_hpt37x 314}; 315 316static struct hpt_info hpt36x __devinitdata = { 317 .chip_type = HPT36x, 318 .max_mode = (HPT366_ALLOW_ATA66_4 || HPT366_ALLOW_ATA66_3) ? 2 : 1, 319 .dpll_clk = 0, /* no DPLL */ 320 .settings = hpt36x_settings 321}; 322 323static struct hpt_info hpt370 __devinitdata = { 324 .chip_type = HPT370, 325 .max_mode = HPT370_ALLOW_ATA100_5 ? 3 : 2, 326 .dpll_clk = 48, 327 .settings = hpt37x_settings 328}; 329 330static struct hpt_info hpt370a __devinitdata = { 331 .chip_type = HPT370A, 332 .max_mode = HPT370_ALLOW_ATA100_5 ? 3 : 2, 333 .dpll_clk = 48, 334 .settings = hpt37x_settings 335}; 336 337static struct hpt_info hpt374 __devinitdata = { 338 .chip_type = HPT374, 339 .max_mode = 3, 340 .dpll_clk = 48, 341 .settings = hpt37x_settings 342}; 343 344static struct hpt_info hpt372 __devinitdata = { 345 .chip_type = HPT372, 346 .max_mode = HPT372_ALLOW_ATA133_6 ? 4 : 3, 347 .dpll_clk = 55, 348 .settings = hpt37x_settings 349}; 350 351static struct hpt_info hpt372a __devinitdata = { 352 .chip_type = HPT372A, 353 .max_mode = HPT372_ALLOW_ATA133_6 ? 4 : 3, 354 .dpll_clk = 66, 355 .settings = hpt37x_settings 356}; 357 358static struct hpt_info hpt302 __devinitdata = { 359 .chip_type = HPT302, 360 .max_mode = HPT302_ALLOW_ATA133_6 ? 4 : 3, 361 .dpll_clk = 66, 362 .settings = hpt37x_settings 363}; 364 365static struct hpt_info hpt371 __devinitdata = { 366 .chip_type = HPT371, 367 .max_mode = HPT371_ALLOW_ATA133_6 ? 4 : 3, 368 .dpll_clk = 66, 369 .settings = hpt37x_settings 370}; 371 372static struct hpt_info hpt372n __devinitdata = { 373 .chip_type = HPT372N, 374 .max_mode = HPT372_ALLOW_ATA133_6 ? 4 : 3, 375 .dpll_clk = 77, 376 .settings = hpt37x_settings 377}; 378 379static struct hpt_info hpt302n __devinitdata = { 380 .chip_type = HPT302N, 381 .max_mode = HPT302_ALLOW_ATA133_6 ? 4 : 3, 382 .dpll_clk = 77, 383 .settings = hpt37x_settings 384}; 385 386static struct hpt_info hpt371n __devinitdata = { 387 .chip_type = HPT371N, 388 .max_mode = HPT371_ALLOW_ATA133_6 ? 4 : 3, 389 .dpll_clk = 77, 390 .settings = hpt37x_settings 391}; 392 393static int check_in_drive_list(ide_drive_t *drive, const char **list) 394{ 395 struct hd_driveid *id = drive->id; 396 397 while (*list) 398 if (!strcmp(*list++,id->model)) 399 return 1; 400 return 0; 401} 402 403/* 404 * Note for the future; the SATA hpt37x we must set 405 * either PIO or UDMA modes 0,4,5 406 */ 407 408static u8 hpt3xx_udma_filter(ide_drive_t *drive) 409{ 410 struct hpt_info *info = pci_get_drvdata(HWIF(drive)->pci_dev); 411 u8 chip_type = info->chip_type; 412 u8 mode = info->max_mode; 413 u8 mask; 414 415 switch (mode) { 416 case 0x04: 417 mask = 0x7f; 418 break; 419 case 0x03: 420 mask = 0x3f; 421 if (chip_type >= HPT374) 422 break; 423 if (!check_in_drive_list(drive, bad_ata100_5)) 424 goto check_bad_ata33; 425 /* fall thru */ 426 case 0x02: 427 mask = 0x1f; 428 429 /* 430 * CHECK ME, Does this need to be changed to HPT374 ?? 431 */ 432 if (chip_type >= HPT370) 433 goto check_bad_ata33; 434 if (HPT366_ALLOW_ATA66_4 && 435 !check_in_drive_list(drive, bad_ata66_4)) 436 goto check_bad_ata33; 437 438 mask = 0x0f; 439 if (HPT366_ALLOW_ATA66_3 && 440 !check_in_drive_list(drive, bad_ata66_3)) 441 goto check_bad_ata33; 442 /* fall thru */ 443 case 0x01: 444 mask = 0x07; 445 446 check_bad_ata33: 447 if (chip_type >= HPT370A) 448 break; 449 if (!check_in_drive_list(drive, bad_ata33)) 450 break; 451 /* fall thru */ 452 case 0x00: 453 default: 454 mask = 0x00; 455 break; 456 } 457 return mask; 458} 459 460static u32 get_speed_setting(u8 speed, struct hpt_info *info) 461{ 462 int i; 463 464 /* 465 * Lookup the transfer mode table to get the index into 466 * the timing table. 467 * 468 * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used. 469 */ 470 for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++) 471 if (xfer_speeds[i] == speed) 472 break; 473 /* 474 * NOTE: info->settings only points to the pointer 475 * to the list of the actual register values 476 */ 477 return (*info->settings)[i]; 478} 479 480static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed) 481{ 482 ide_hwif_t *hwif = HWIF(drive); 483 struct pci_dev *dev = hwif->pci_dev; 484 struct hpt_info *info = pci_get_drvdata(dev); 485 u8 speed = ide_rate_filter(drive, xferspeed); 486 u8 itr_addr = drive->dn ? 0x44 : 0x40; 487 u32 old_itr = 0; 488 u32 itr_mask, new_itr; 489 490 /* TODO: move this to ide_rate_filter() [ check ->atapi_dma ] */ 491 if (drive->media != ide_disk) 492 speed = min_t(u8, speed, XFER_PIO_4); 493 494 itr_mask = speed < XFER_MW_DMA_0 ? 0x30070000 : 495 (speed < XFER_UDMA_0 ? 0xc0070000 : 0xc03800ff); 496 497 new_itr = get_speed_setting(speed, info); 498 499 /* 500 * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well) 501 * to avoid problems handling I/O errors later 502 */ 503 pci_read_config_dword(dev, itr_addr, &old_itr); 504 new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask); 505 new_itr &= ~0xc0000000; 506 507 pci_write_config_dword(dev, itr_addr, new_itr); 508 509 return ide_config_drive_speed(drive, speed); 510} 511 512static int hpt37x_tune_chipset(ide_drive_t *drive, u8 xferspeed) 513{ 514 ide_hwif_t *hwif = HWIF(drive); 515 struct pci_dev *dev = hwif->pci_dev; 516 struct hpt_info *info = pci_get_drvdata(dev); 517 u8 speed = ide_rate_filter(drive, xferspeed); 518 u8 itr_addr = 0x40 + (drive->dn * 4); 519 u32 old_itr = 0; 520 u32 itr_mask, new_itr; 521 522 /* TODO: move this to ide_rate_filter() [ check ->atapi_dma ] */ 523 if (drive->media != ide_disk) 524 speed = min_t(u8, speed, XFER_PIO_4); 525 526 itr_mask = speed < XFER_MW_DMA_0 ? 0x303c0000 : 527 (speed < XFER_UDMA_0 ? 0xc03c0000 : 0xc1c001ff); 528 529 new_itr = get_speed_setting(speed, info); 530 531 pci_read_config_dword(dev, itr_addr, &old_itr); 532 new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask); 533 534 if (speed < XFER_MW_DMA_0) 535 new_itr &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */ 536 pci_write_config_dword(dev, itr_addr, new_itr); 537 538 return ide_config_drive_speed(drive, speed); 539} 540 541static int hpt3xx_tune_chipset(ide_drive_t *drive, u8 speed) 542{ 543 ide_hwif_t *hwif = HWIF(drive); 544 struct hpt_info *info = pci_get_drvdata(hwif->pci_dev); 545 546 if (info->chip_type >= HPT370) 547 return hpt37x_tune_chipset(drive, speed); 548 else /* hpt368: hpt_minimum_revision(dev, 2) */ 549 return hpt36x_tune_chipset(drive, speed); 550} 551 552static void hpt3xx_tune_drive(ide_drive_t *drive, u8 pio) 553{ 554 pio = ide_get_best_pio_mode(drive, pio, 4, NULL); 555 (void) hpt3xx_tune_chipset (drive, XFER_PIO_0 + pio); 556} 557 558static int hpt3xx_quirkproc(ide_drive_t *drive) 559{ 560 struct hd_driveid *id = drive->id; 561 const char **list = quirk_drives; 562 563 while (*list) 564 if (strstr(id->model, *list++)) 565 return 1; 566 return 0; 567} 568 569static void hpt3xx_intrproc(ide_drive_t *drive) 570{ 571 ide_hwif_t *hwif = HWIF(drive); 572 573 if (drive->quirk_list) 574 return; 575 /* drives in the quirk_list may not like intr setups/cleanups */ 576 hwif->OUTB(drive->ctl | 2, IDE_CONTROL_REG); 577} 578 579static void hpt3xx_maskproc(ide_drive_t *drive, int mask) 580{ 581 ide_hwif_t *hwif = HWIF(drive); 582 struct pci_dev *dev = hwif->pci_dev; 583 struct hpt_info *info = pci_get_drvdata(dev); 584 585 if (drive->quirk_list) { 586 if (info->chip_type >= HPT370) { 587 u8 scr1 = 0; 588 589 pci_read_config_byte(dev, 0x5a, &scr1); 590 if (((scr1 & 0x10) >> 4) != mask) { 591 if (mask) 592 scr1 |= 0x10; 593 else 594 scr1 &= ~0x10; 595 pci_write_config_byte(dev, 0x5a, scr1); 596 } 597 } else { 598 if (mask) 599 disable_irq(hwif->irq); 600 else 601 enable_irq (hwif->irq); 602 } 603 } else 604 hwif->OUTB(mask ? (drive->ctl | 2) : (drive->ctl & ~2), 605 IDE_CONTROL_REG); 606} 607 608static int hpt366_config_drive_xfer_rate(ide_drive_t *drive) 609{ 610 drive->init_speed = 0; 611 612 if (ide_tune_dma(drive)) 613 return 0; 614 615 if (ide_use_fast_pio(drive)) 616 hpt3xx_tune_drive(drive, 255); 617 618 return -1; 619} 620 621/* 622 * This is specific to the HPT366 UDMA chipset 623 * by HighPoint|Triones Technologies, Inc. 624 */ 625static int hpt366_ide_dma_lostirq(ide_drive_t *drive) 626{ 627 struct pci_dev *dev = HWIF(drive)->pci_dev; 628 u8 mcr1 = 0, mcr3 = 0, scr1 = 0; 629 630 pci_read_config_byte(dev, 0x50, &mcr1); 631 pci_read_config_byte(dev, 0x52, &mcr3); 632 pci_read_config_byte(dev, 0x5a, &scr1); 633 printk("%s: (%s) mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n", 634 drive->name, __FUNCTION__, mcr1, mcr3, scr1); 635 if (scr1 & 0x10) 636 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10); 637 return __ide_dma_lostirq(drive); 638} 639 640static void hpt370_clear_engine(ide_drive_t *drive) 641{ 642 ide_hwif_t *hwif = HWIF(drive); 643 644 pci_write_config_byte(hwif->pci_dev, hwif->select_data, 0x37); 645 udelay(10); 646} 647 648static void hpt370_irq_timeout(ide_drive_t *drive) 649{ 650 ide_hwif_t *hwif = HWIF(drive); 651 u16 bfifo = 0; 652 u8 dma_cmd; 653 654 pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo); 655 printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff); 656 657 /* get DMA command mode */ 658 dma_cmd = hwif->INB(hwif->dma_command); 659 /* stop DMA */ 660 hwif->OUTB(dma_cmd & ~0x1, hwif->dma_command); 661 hpt370_clear_engine(drive); 662} 663 664static void hpt370_ide_dma_start(ide_drive_t *drive) 665{ 666#ifdef HPT_RESET_STATE_ENGINE 667 hpt370_clear_engine(drive); 668#endif 669 ide_dma_start(drive); 670} 671 672static int hpt370_ide_dma_end(ide_drive_t *drive) 673{ 674 ide_hwif_t *hwif = HWIF(drive); 675 u8 dma_stat = hwif->INB(hwif->dma_status); 676 677 if (dma_stat & 0x01) { 678 /* wait a little */ 679 udelay(20); 680 dma_stat = hwif->INB(hwif->dma_status); 681 if (dma_stat & 0x01) 682 hpt370_irq_timeout(drive); 683 } 684 return __ide_dma_end(drive); 685} 686 687static int hpt370_ide_dma_timeout(ide_drive_t *drive) 688{ 689 hpt370_irq_timeout(drive); 690 return __ide_dma_timeout(drive); 691} 692 693/* returns 1 if DMA IRQ issued, 0 otherwise */ 694static int hpt374_ide_dma_test_irq(ide_drive_t *drive) 695{ 696 ide_hwif_t *hwif = HWIF(drive); 697 u16 bfifo = 0; 698 u8 dma_stat; 699 700 pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo); 701 if (bfifo & 0x1FF) { 702// printk("%s: %d bytes in FIFO\n", drive->name, bfifo); 703 return 0; 704 } 705 706 dma_stat = inb(hwif->dma_status); 707 /* return 1 if INTR asserted */ 708 if (dma_stat & 4) 709 return 1; 710 711 if (!drive->waiting_for_dma) 712 printk(KERN_WARNING "%s: (%s) called while not waiting\n", 713 drive->name, __FUNCTION__); 714 return 0; 715} 716 717static int hpt374_ide_dma_end(ide_drive_t *drive) 718{ 719 ide_hwif_t *hwif = HWIF(drive); 720 struct pci_dev *dev = hwif->pci_dev; 721 u8 mcr = 0, mcr_addr = hwif->select_data; 722 u8 bwsr = 0, mask = hwif->channel ? 0x02 : 0x01; 723 724 pci_read_config_byte(dev, 0x6a, &bwsr); 725 pci_read_config_byte(dev, mcr_addr, &mcr); 726 if (bwsr & mask) 727 pci_write_config_byte(dev, mcr_addr, mcr | 0x30); 728 return __ide_dma_end(drive); 729} 730 731/** 732 * hpt3xxn_set_clock - perform clock switching dance 733 * @hwif: hwif to switch 734 * @mode: clocking mode (0x21 for write, 0x23 otherwise) 735 * 736 * Switch the DPLL clock on the HPT3xxN devices. This is a right mess. 737 */ 738 739static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode) 740{ 741 u8 scr2 = hwif->INB(hwif->dma_master + 0x7b); 742 743 if ((scr2 & 0x7f) == mode) 744 return; 745 746 /* Tristate the bus */ 747 hwif->OUTB(0x80, hwif->dma_master + 0x73); 748 hwif->OUTB(0x80, hwif->dma_master + 0x77); 749 750 /* Switch clock and reset channels */ 751 hwif->OUTB(mode, hwif->dma_master + 0x7b); 752 hwif->OUTB(0xc0, hwif->dma_master + 0x79); 753 754 /* 755 * Reset the state machines. 756 * NOTE: avoid accidentally enabling the disabled channels. 757 */ 758 hwif->OUTB(hwif->INB(hwif->dma_master + 0x70) | 0x32, 759 hwif->dma_master + 0x70); 760 hwif->OUTB(hwif->INB(hwif->dma_master + 0x74) | 0x32, 761 hwif->dma_master + 0x74); 762 763 /* Complete reset */ 764 hwif->OUTB(0x00, hwif->dma_master + 0x79); 765 766 /* Reconnect channels to bus */ 767 hwif->OUTB(0x00, hwif->dma_master + 0x73); 768 hwif->OUTB(0x00, hwif->dma_master + 0x77); 769} 770 771/** 772 * hpt3xxn_rw_disk - prepare for I/O 773 * @drive: drive for command 774 * @rq: block request structure 775 * 776 * This is called when a disk I/O is issued to HPT3xxN. 777 * We need it because of the clock switching. 778 */ 779 780static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq) 781{ 782 hpt3xxn_set_clock(HWIF(drive), rq_data_dir(rq) ? 0x23 : 0x21); 783} 784 785/* 786 * Set/get power state for a drive. 787 * NOTE: affects both drives on each channel. 788 * 789 * When we turn the power back on, we need to re-initialize things. 790 */ 791#define TRISTATE_BIT 0x8000 792 793static int hpt3xx_busproc(ide_drive_t *drive, int state) 794{ 795 ide_hwif_t *hwif = HWIF(drive); 796 struct pci_dev *dev = hwif->pci_dev; 797 u8 mcr_addr = hwif->select_data + 2; 798 u8 resetmask = hwif->channel ? 0x80 : 0x40; 799 u8 bsr2 = 0; 800 u16 mcr = 0; 801 802 hwif->bus_state = state; 803 804 /* Grab the status. */ 805 pci_read_config_word(dev, mcr_addr, &mcr); 806 pci_read_config_byte(dev, 0x59, &bsr2); 807 808 /* 809 * Set the state. We don't set it if we don't need to do so. 810 * Make sure that the drive knows that it has failed if it's off. 811 */ 812 switch (state) { 813 case BUSSTATE_ON: 814 if (!(bsr2 & resetmask)) 815 return 0; 816 hwif->drives[0].failures = hwif->drives[1].failures = 0; 817 818 pci_write_config_byte(dev, 0x59, bsr2 & ~resetmask); 819 pci_write_config_word(dev, mcr_addr, mcr & ~TRISTATE_BIT); 820 return 0; 821 case BUSSTATE_OFF: 822 if ((bsr2 & resetmask) && !(mcr & TRISTATE_BIT)) 823 return 0; 824 mcr &= ~TRISTATE_BIT; 825 break; 826 case BUSSTATE_TRISTATE: 827 if ((bsr2 & resetmask) && (mcr & TRISTATE_BIT)) 828 return 0; 829 mcr |= TRISTATE_BIT; 830 break; 831 default: 832 return -EINVAL; 833 } 834 835 hwif->drives[0].failures = hwif->drives[0].max_failures + 1; 836 hwif->drives[1].failures = hwif->drives[1].max_failures + 1; 837 838 pci_write_config_word(dev, mcr_addr, mcr); 839 pci_write_config_byte(dev, 0x59, bsr2 | resetmask); 840 return 0; 841} 842 843/** 844 * hpt37x_calibrate_dpll - calibrate the DPLL 845 * @dev: PCI device 846 * 847 * Perform a calibration cycle on the DPLL. 848 * Returns 1 if this succeeds 849 */ 850static int __devinit hpt37x_calibrate_dpll(struct pci_dev *dev, u16 f_low, u16 f_high) 851{ 852 u32 dpll = (f_high << 16) | f_low | 0x100; 853 u8 scr2; 854 int i; 855 856 pci_write_config_dword(dev, 0x5c, dpll); 857 858 /* Wait for oscillator ready */ 859 for(i = 0; i < 0x5000; ++i) { 860 udelay(50); 861 pci_read_config_byte(dev, 0x5b, &scr2); 862 if (scr2 & 0x80) 863 break; 864 } 865 /* See if it stays ready (we'll just bail out if it's not yet) */ 866 for(i = 0; i < 0x1000; ++i) { 867 pci_read_config_byte(dev, 0x5b, &scr2); 868 /* DPLL destabilized? */ 869 if(!(scr2 & 0x80)) 870 return 0; 871 } 872 /* Turn off tuning, we have the DPLL set */ 873 pci_read_config_dword (dev, 0x5c, &dpll); 874 pci_write_config_dword(dev, 0x5c, (dpll & ~0x100)); 875 return 1; 876} 877 878static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name) 879{ 880 struct hpt_info *info = kmalloc(sizeof(struct hpt_info), GFP_KERNEL); 881 unsigned long io_base = pci_resource_start(dev, 4); 882 u8 pci_clk, dpll_clk = 0; /* PCI and DPLL clock in MHz */ 883 enum ata_clock clock; 884 885 if (info == NULL) { 886 printk(KERN_ERR "%s: out of memory!\n", name); 887 return -ENOMEM; 888 } 889 890 /* 891 * Copy everything from a static "template" structure 892 * to just allocated per-chip hpt_info structure. 893 */ 894 *info = *(struct hpt_info *)pci_get_drvdata(dev); 895 896 if (dev->resource[PCI_ROM_RESOURCE].start) 897 pci_write_config_dword(dev, PCI_ROM_ADDRESS, 898 dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE); 899 900 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4)); 901 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78); 902 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08); 903 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08); 904 905 /* 906 * First, try to estimate the PCI clock frequency... 907 */ 908 if (info->chip_type >= HPT370) { 909 u8 scr1 = 0; 910 u16 f_cnt = 0; 911 u32 temp = 0; 912 913 /* Interrupt force enable. */ 914 pci_read_config_byte(dev, 0x5a, &scr1); 915 if (scr1 & 0x10) 916 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10); 917 918 /* 919 * HighPoint does this for HPT372A. 920 * NOTE: This register is only writeable via I/O space. 921 */ 922 if (info->chip_type == HPT372A) 923 outb(0x0e, io_base + 0x9c); 924 925 /* 926 * Default to PCI clock. Make sure MA15/16 are set to output 927 * to prevent drives having problems with 40-pin cables. 928 */ 929 pci_write_config_byte(dev, 0x5b, 0x23); 930 931 /* 932 * We'll have to read f_CNT value in order to determine 933 * the PCI clock frequency according to the following ratio: 934 * 935 * f_CNT = Fpci * 192 / Fdpll 936 * 937 * First try reading the register in which the HighPoint BIOS 938 * saves f_CNT value before reprogramming the DPLL from its 939 * default setting (which differs for the various chips). 940 * NOTE: This register is only accessible via I/O space. 941 * 942 * In case the signature check fails, we'll have to resort to 943 * reading the f_CNT register itself in hopes that nobody has 944 * touched the DPLL yet... 945 */ 946 temp = inl(io_base + 0x90); 947 if ((temp & 0xFFFFF000) != 0xABCDE000) { 948 int i; 949 950 printk(KERN_WARNING "%s: no clock data saved by BIOS\n", 951 name); 952 953 /* Calculate the average value of f_CNT. */ 954 for (temp = i = 0; i < 128; i++) { 955 pci_read_config_word(dev, 0x78, &f_cnt); 956 temp += f_cnt & 0x1ff; 957 mdelay(1); 958 } 959 f_cnt = temp / 128; 960 } else 961 f_cnt = temp & 0x1ff; 962 963 dpll_clk = info->dpll_clk; 964 pci_clk = (f_cnt * dpll_clk) / 192; 965 966 /* Clamp PCI clock to bands. */ 967 if (pci_clk < 40) 968 pci_clk = 33; 969 else if(pci_clk < 45) 970 pci_clk = 40; 971 else if(pci_clk < 55) 972 pci_clk = 50; 973 else 974 pci_clk = 66; 975 976 printk(KERN_INFO "%s: DPLL base: %d MHz, f_CNT: %d, " 977 "assuming %d MHz PCI\n", name, dpll_clk, f_cnt, pci_clk); 978 } else { 979 u32 itr1 = 0; 980 981 pci_read_config_dword(dev, 0x40, &itr1); 982 983 /* Detect PCI clock by looking at cmd_high_time. */ 984 switch((itr1 >> 8) & 0x07) { 985 case 0x09: 986 pci_clk = 40; 987 break; 988 case 0x05: 989 pci_clk = 25; 990 break; 991 case 0x07: 992 default: 993 pci_clk = 33; 994 break; 995 } 996 } 997 998 /* Let's assume we'll use PCI clock for the ATA clock... */ 999 switch (pci_clk) { 1000 case 25: 1001 clock = ATA_CLOCK_25MHZ; 1002 break; 1003 case 33: 1004 default: 1005 clock = ATA_CLOCK_33MHZ; 1006 break; 1007 case 40: 1008 clock = ATA_CLOCK_40MHZ; 1009 break; 1010 case 50: 1011 clock = ATA_CLOCK_50MHZ; 1012 break; 1013 case 66: 1014 clock = ATA_CLOCK_66MHZ; 1015 break; 1016 } 1017 1018 /* 1019 * Only try the DPLL if we don't have a table for the PCI clock that 1020 * we are running at for HPT370/A, always use it for anything newer... 1021 * 1022 * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI. 1023 * We also don't like using the DPLL because this causes glitches 1024 * on PRST-/SRST- when the state engine gets reset... 1025 */ 1026 if (info->chip_type >= HPT374 || info->settings[clock] == NULL) { 1027 u16 f_low, delta = pci_clk < 50 ? 2 : 4; 1028 int adjust; 1029 1030 /* 1031 * Select 66 MHz DPLL clock only if UltraATA/133 mode is 1032 * supported/enabled, use 50 MHz DPLL clock otherwise... 1033 */ 1034 if (info->max_mode == 0x04) { 1035 dpll_clk = 66; 1036 clock = ATA_CLOCK_66MHZ; 1037 } else if (dpll_clk) { /* HPT36x chips don't have DPLL */ 1038 dpll_clk = 50; 1039 clock = ATA_CLOCK_50MHZ; 1040 } 1041 1042 if (info->settings[clock] == NULL) { 1043 printk(KERN_ERR "%s: unknown bus timing!\n", name); 1044 kfree(info); 1045 return -EIO; 1046 } 1047 1048 /* Select the DPLL clock. */ 1049 pci_write_config_byte(dev, 0x5b, 0x21); 1050 1051 /* 1052 * Adjust the DPLL based upon PCI clock, enable it, 1053 * and wait for stabilization... 1054 */ 1055 f_low = (pci_clk * 48) / dpll_clk; 1056 1057 for (adjust = 0; adjust < 8; adjust++) { 1058 if(hpt37x_calibrate_dpll(dev, f_low, f_low + delta)) 1059 break; 1060 1061 /* 1062 * See if it'll settle at a fractionally different clock 1063 */ 1064 if (adjust & 1) 1065 f_low -= adjust >> 1; 1066 else 1067 f_low += adjust >> 1; 1068 } 1069 if (adjust == 8) { 1070 printk(KERN_ERR "%s: DPLL did not stabilize!\n", name); 1071 kfree(info); 1072 return -EIO; 1073 } 1074 1075 printk("%s: using %d MHz DPLL clock\n", name, dpll_clk); 1076 } else { 1077 /* Mark the fact that we're not using the DPLL. */ 1078 dpll_clk = 0; 1079 1080 printk("%s: using %d MHz PCI clock\n", name, pci_clk); 1081 } 1082 1083 /* 1084 * Advance the table pointer to a slot which points to the list 1085 * of the register values settings matching the clock being used. 1086 */ 1087 info->settings += clock; 1088 1089 /* Store the clock frequencies. */ 1090 info->dpll_clk = dpll_clk; 1091 info->pci_clk = pci_clk; 1092 1093 /* Point to this chip's own instance of the hpt_info structure. */ 1094 pci_set_drvdata(dev, info); 1095 1096 if (info->chip_type >= HPT370) { 1097 u8 mcr1, mcr4; 1098 1099 /* 1100 * Reset the state engines. 1101 * NOTE: Avoid accidentally enabling the disabled channels. 1102 */ 1103 pci_read_config_byte (dev, 0x50, &mcr1); 1104 pci_read_config_byte (dev, 0x54, &mcr4); 1105 pci_write_config_byte(dev, 0x50, (mcr1 | 0x32)); 1106 pci_write_config_byte(dev, 0x54, (mcr4 | 0x32)); 1107 udelay(100); 1108 } 1109 1110 /* 1111 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in 1112 * the MISC. register to stretch the UltraDMA Tss timing. 1113 * NOTE: This register is only writeable via I/O space. 1114 */ 1115 if (info->chip_type == HPT371N && clock == ATA_CLOCK_66MHZ) 1116 1117 outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c); 1118 1119 return dev->irq; 1120} 1121 1122static void __devinit init_hwif_hpt366(ide_hwif_t *hwif) 1123{ 1124 struct pci_dev *dev = hwif->pci_dev; 1125 struct hpt_info *info = pci_get_drvdata(dev); 1126 int serialize = HPT_SERIALIZE_IO; 1127 u8 scr1 = 0, ata66 = (hwif->channel) ? 0x01 : 0x02; 1128 u8 chip_type = info->chip_type; 1129 u8 new_mcr, old_mcr = 0; 1130 1131 /* Cache the channel's MISC. control registers' offset */ 1132 hwif->select_data = hwif->channel ? 0x54 : 0x50; 1133 1134 hwif->tuneproc = &hpt3xx_tune_drive; 1135 hwif->speedproc = &hpt3xx_tune_chipset; 1136 hwif->quirkproc = &hpt3xx_quirkproc; 1137 hwif->intrproc = &hpt3xx_intrproc; 1138 hwif->maskproc = &hpt3xx_maskproc; 1139 hwif->busproc = &hpt3xx_busproc; 1140 hwif->udma_filter = &hpt3xx_udma_filter; 1141 1142 /* 1143 * HPT3xxN chips have some complications: 1144 * 1145 * - on 33 MHz PCI we must clock switch 1146 * - on 66 MHz PCI we must NOT use the PCI clock 1147 */ 1148 if (chip_type >= HPT372N && info->dpll_clk && info->pci_clk < 66) { 1149 /* 1150 * Clock is shared between the channels, 1151 * so we'll have to serialize them... :-( 1152 */ 1153 serialize = 1; 1154 hwif->rw_disk = &hpt3xxn_rw_disk; 1155 } 1156 1157 /* Serialize access to this device if needed */ 1158 if (serialize && hwif->mate) 1159 hwif->serialized = hwif->mate->serialized = 1; 1160 1161 /* 1162 * Disable the "fast interrupt" prediction. Don't hold off 1163 * on interrupts. (== 0x01 despite what the docs say) 1164 */ 1165 pci_read_config_byte(dev, hwif->select_data + 1, &old_mcr); 1166 1167 if (info->chip_type >= HPT374) 1168 new_mcr = old_mcr & ~0x07; 1169 else if (info->chip_type >= HPT370) { 1170 new_mcr = old_mcr; 1171 new_mcr &= ~0x02; 1172 1173#ifdef HPT_DELAY_INTERRUPT 1174 new_mcr &= ~0x01; 1175#else 1176 new_mcr |= 0x01; 1177#endif 1178 } else /* HPT366 and HPT368 */ 1179 new_mcr = old_mcr & ~0x80; 1180 1181 if (new_mcr != old_mcr) 1182 pci_write_config_byte(dev, hwif->select_data + 1, new_mcr); 1183 1184 if (!hwif->dma_base) { 1185 hwif->drives[0].autotune = hwif->drives[1].autotune = 1; 1186 return; 1187 } 1188 1189 hwif->ultra_mask = 0x7f; 1190 hwif->mwdma_mask = 0x07; 1191 1192 /* 1193 * The HPT37x uses the CBLID pins as outputs for MA15/MA16 1194 * address lines to access an external EEPROM. To read valid 1195 * cable detect state the pins must be enabled as inputs. 1196 */ 1197 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) { 1198 /* 1199 * HPT374 PCI function 1 1200 * - set bit 15 of reg 0x52 to enable TCBLID as input 1201 * - set bit 15 of reg 0x56 to enable FCBLID as input 1202 */ 1203 u8 mcr_addr = hwif->select_data + 2; 1204 u16 mcr; 1205 1206 pci_read_config_word (dev, mcr_addr, &mcr); 1207 pci_write_config_word(dev, mcr_addr, (mcr | 0x8000)); 1208 /* now read cable id register */ 1209 pci_read_config_byte (dev, 0x5a, &scr1); 1210 pci_write_config_word(dev, mcr_addr, mcr); 1211 } else if (chip_type >= HPT370) { 1212 /* 1213 * HPT370/372 and 374 pcifn 0 1214 * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs 1215 */ 1216 u8 scr2 = 0; 1217 1218 pci_read_config_byte (dev, 0x5b, &scr2); 1219 pci_write_config_byte(dev, 0x5b, (scr2 & ~1)); 1220 /* now read cable id register */ 1221 pci_read_config_byte (dev, 0x5a, &scr1); 1222 pci_write_config_byte(dev, 0x5b, scr2); 1223 } else 1224 pci_read_config_byte (dev, 0x5a, &scr1); 1225 1226 if (!hwif->udma_four) 1227 hwif->udma_four = (scr1 & ata66) ? 0 : 1; 1228 1229 hwif->ide_dma_check = &hpt366_config_drive_xfer_rate; 1230 1231 if (chip_type >= HPT374) { 1232 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq; 1233 hwif->ide_dma_end = &hpt374_ide_dma_end; 1234 } else if (chip_type >= HPT370) { 1235 hwif->dma_start = &hpt370_ide_dma_start; 1236 hwif->ide_dma_end = &hpt370_ide_dma_end; 1237 hwif->ide_dma_timeout = &hpt370_ide_dma_timeout; 1238 } else 1239 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq; 1240 1241 if (!noautodma) 1242 hwif->autodma = 1; 1243 hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma; 1244} 1245 1246static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase) 1247{ 1248 struct pci_dev *dev = hwif->pci_dev; 1249 u8 masterdma = 0, slavedma = 0; 1250 u8 dma_new = 0, dma_old = 0; 1251 unsigned long flags; 1252 1253 dma_old = hwif->INB(dmabase + 2); 1254 1255 local_irq_save(flags); 1256 1257 dma_new = dma_old; 1258 pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma); 1259 pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47, &slavedma); 1260 1261 if (masterdma & 0x30) dma_new |= 0x20; 1262 if ( slavedma & 0x30) dma_new |= 0x40; 1263 if (dma_new != dma_old) 1264 hwif->OUTB(dma_new, dmabase + 2); 1265 1266 local_irq_restore(flags); 1267 1268 ide_setup_dma(hwif, dmabase, 8); 1269} 1270 1271static int __devinit init_setup_hpt374(struct pci_dev *dev, ide_pci_device_t *d) 1272{ 1273 struct pci_dev *dev2; 1274 1275 if (PCI_FUNC(dev->devfn) & 1) 1276 return -ENODEV; 1277 1278 pci_set_drvdata(dev, &hpt374); 1279 1280 if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) { 1281 int ret; 1282 1283 pci_set_drvdata(dev2, &hpt374); 1284 1285 if (dev2->irq != dev->irq) { 1286 dev2->irq = dev->irq; 1287 printk(KERN_WARNING "%s: PCI config space interrupt " 1288 "fixed.\n", d->name); 1289 } 1290 ret = ide_setup_pci_devices(dev, dev2, d); 1291 if (ret < 0) 1292 pci_dev_put(dev2); 1293 return ret; 1294 } 1295 return ide_setup_pci_device(dev, d); 1296} 1297 1298static int __devinit init_setup_hpt372n(struct pci_dev *dev, ide_pci_device_t *d) 1299{ 1300 pci_set_drvdata(dev, &hpt372n); 1301 1302 return ide_setup_pci_device(dev, d); 1303} 1304 1305static int __devinit init_setup_hpt371(struct pci_dev *dev, ide_pci_device_t *d) 1306{ 1307 struct hpt_info *info; 1308 u8 rev = 0, mcr1 = 0; 1309 1310 pci_read_config_byte(dev, PCI_REVISION_ID, &rev); 1311 1312 if (rev > 1) { 1313 d->name = "HPT371N"; 1314 1315 info = &hpt371n; 1316 } else 1317 info = &hpt371; 1318 1319 /* 1320 * HPT371 chips physically have only one channel, the secondary one, 1321 * but the primary channel registers do exist! Go figure... 1322 * So, we manually disable the non-existing channel here 1323 * (if the BIOS hasn't done this already). 1324 */ 1325 pci_read_config_byte(dev, 0x50, &mcr1); 1326 if (mcr1 & 0x04) 1327 pci_write_config_byte(dev, 0x50, mcr1 & ~0x04); 1328 1329 pci_set_drvdata(dev, info); 1330 1331 return ide_setup_pci_device(dev, d); 1332} 1333 1334static int __devinit init_setup_hpt372a(struct pci_dev *dev, ide_pci_device_t *d) 1335{ 1336 struct hpt_info *info; 1337 u8 rev = 0; 1338 1339 pci_read_config_byte(dev, PCI_REVISION_ID, &rev); 1340 1341 if (rev > 1) { 1342 d->name = "HPT372N"; 1343 1344 info = &hpt372n; 1345 } else 1346 info = &hpt372a; 1347 pci_set_drvdata(dev, info); 1348 1349 return ide_setup_pci_device(dev, d); 1350} 1351 1352static int __devinit init_setup_hpt302(struct pci_dev *dev, ide_pci_device_t *d) 1353{ 1354 struct hpt_info *info; 1355 u8 rev = 0; 1356 1357 pci_read_config_byte(dev, PCI_REVISION_ID, &rev); 1358 1359 if (rev > 1) { 1360 d->name = "HPT302N"; 1361 1362 info = &hpt302n; 1363 } else 1364 info = &hpt302; 1365 pci_set_drvdata(dev, info); 1366 1367 return ide_setup_pci_device(dev, d); 1368} 1369 1370static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d) 1371{ 1372 struct pci_dev *dev2; 1373 u8 rev = 0; 1374 static char *chipset_names[] = { "HPT366", "HPT366", "HPT368", 1375 "HPT370", "HPT370A", "HPT372", 1376 "HPT372N" }; 1377 static struct hpt_info *info[] = { &hpt36x, &hpt36x, &hpt36x, 1378 &hpt370, &hpt370a, &hpt372, 1379 &hpt372n }; 1380 1381 if (PCI_FUNC(dev->devfn) & 1) 1382 return -ENODEV; 1383 1384 pci_read_config_byte(dev, PCI_REVISION_ID, &rev); 1385 1386 if (rev > 6) 1387 rev = 6; 1388 1389 d->name = chipset_names[rev]; 1390 1391 pci_set_drvdata(dev, info[rev]); 1392 1393 if (rev > 2) 1394 goto init_single; 1395 1396 /* 1397 * HPT36x chips have one channel per function and have 1398 * both channel enable bits located differently and visible 1399 * to both functions -- really stupid design decision... :-( 1400 * Bit 4 is for the primary channel, bit 5 for the secondary. 1401 */ 1402 d->channels = 1; 1403 d->enablebits[0].mask = d->enablebits[0].val = 0x10; 1404 1405 if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) { 1406 u8 mcr1 = 0, pin1 = 0, pin2 = 0; 1407 int ret; 1408 1409 pci_set_drvdata(dev2, info[rev]); 1410 1411 /* 1412 * Now we'll have to force both channels enabled if 1413 * at least one of them has been enabled by BIOS... 1414 */ 1415 pci_read_config_byte(dev, 0x50, &mcr1); 1416 if (mcr1 & 0x30) 1417 pci_write_config_byte(dev, 0x50, mcr1 | 0x30); 1418 1419 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1); 1420 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2); 1421 if (pin1 != pin2 && dev->irq == dev2->irq) { 1422 d->bootable = ON_BOARD; 1423 printk("%s: onboard version of chipset, pin1=%d pin2=%d\n", 1424 d->name, pin1, pin2); 1425 } 1426 ret = ide_setup_pci_devices(dev, dev2, d); 1427 if (ret < 0) 1428 pci_dev_put(dev2); 1429 return ret; 1430 } 1431init_single: 1432 return ide_setup_pci_device(dev, d); 1433} 1434 1435static ide_pci_device_t hpt366_chipsets[] __devinitdata = { 1436 { /* 0 */ 1437 .name = "HPT366", 1438 .init_setup = init_setup_hpt366, 1439 .init_chipset = init_chipset_hpt366, 1440 .init_hwif = init_hwif_hpt366, 1441 .init_dma = init_dma_hpt366, 1442 .channels = 2, 1443 .autodma = AUTODMA, 1444 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, 1445 .bootable = OFF_BOARD, 1446 .extra = 240 1447 },{ /* 1 */ 1448 .name = "HPT372A", 1449 .init_setup = init_setup_hpt372a, 1450 .init_chipset = init_chipset_hpt366, 1451 .init_hwif = init_hwif_hpt366, 1452 .init_dma = init_dma_hpt366, 1453 .channels = 2, 1454 .autodma = AUTODMA, 1455 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, 1456 .bootable = OFF_BOARD, 1457 .extra = 240 1458 },{ /* 2 */ 1459 .name = "HPT302", 1460 .init_setup = init_setup_hpt302, 1461 .init_chipset = init_chipset_hpt366, 1462 .init_hwif = init_hwif_hpt366, 1463 .init_dma = init_dma_hpt366, 1464 .channels = 2, 1465 .autodma = AUTODMA, 1466 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, 1467 .bootable = OFF_BOARD, 1468 .extra = 240 1469 },{ /* 3 */ 1470 .name = "HPT371", 1471 .init_setup = init_setup_hpt371, 1472 .init_chipset = init_chipset_hpt366, 1473 .init_hwif = init_hwif_hpt366, 1474 .init_dma = init_dma_hpt366, 1475 .channels = 2, 1476 .autodma = AUTODMA, 1477 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, 1478 .bootable = OFF_BOARD, 1479 .extra = 240 1480 },{ /* 4 */ 1481 .name = "HPT374", 1482 .init_setup = init_setup_hpt374, 1483 .init_chipset = init_chipset_hpt366, 1484 .init_hwif = init_hwif_hpt366, 1485 .init_dma = init_dma_hpt366, 1486 .channels = 2, /* 4 */ 1487 .autodma = AUTODMA, 1488 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, 1489 .bootable = OFF_BOARD, 1490 .extra = 240 1491 },{ /* 5 */ 1492 .name = "HPT372N", 1493 .init_setup = init_setup_hpt372n, 1494 .init_chipset = init_chipset_hpt366, 1495 .init_hwif = init_hwif_hpt366, 1496 .init_dma = init_dma_hpt366, 1497 .channels = 2, /* 4 */ 1498 .autodma = AUTODMA, 1499 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}}, 1500 .bootable = OFF_BOARD, 1501 .extra = 240 1502 } 1503}; 1504 1505/** 1506 * hpt366_init_one - called when an HPT366 is found 1507 * @dev: the hpt366 device 1508 * @id: the matching pci id 1509 * 1510 * Called when the PCI registration layer (or the IDE initialization) 1511 * finds a device matching our IDE device tables. 1512 * 1513 * NOTE: since we'll have to modify some fields of the ide_pci_device_t 1514 * structure depending on the chip's revision, we'd better pass a local 1515 * copy down the call chain... 1516 */ 1517static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id) 1518{ 1519 ide_pci_device_t d = hpt366_chipsets[id->driver_data]; 1520 1521 return d.init_setup(dev, &d); 1522} 1523 1524static struct pci_device_id hpt366_pci_tbl[] = { 1525 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 1526 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1}, 1527 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2}, 1528 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3}, 1529 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT374, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4}, 1530 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372N, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5}, 1531 { 0, }, 1532}; 1533MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl); 1534 1535static struct pci_driver driver = { 1536 .name = "HPT366_IDE", 1537 .id_table = hpt366_pci_tbl, 1538 .probe = hpt366_init_one, 1539}; 1540 1541static int __init hpt366_ide_init(void) 1542{ 1543 return ide_pci_register_driver(&driver); 1544} 1545 1546module_init(hpt366_ide_init); 1547 1548MODULE_AUTHOR("Andre Hedrick"); 1549MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE"); 1550MODULE_LICENSE("GPL"); 1551