1/* 2 * linux/drivers/ide/pci/cs5535.c 3 * 4 * Copyright (C) 2004-2005 Advanced Micro Devices, Inc. 5 * 6 * History: 7 * 09/20/2005 - Jaya Kumar <jayakumar.ide@gmail.com> 8 * - Reworked tuneproc, set_drive, misc mods to prep for mainline 9 * - Work was sponsored by CIS (M) Sdn Bhd. 10 * Ported to Kernel 2.6.11 on June 26, 2005 by 11 * Wolfgang Zuleger <wolfgang.zuleger@gmx.de> 12 * Alexander Kiausch <alex.kiausch@t-online.de> 13 * Originally developed by AMD for 2.4/2.6 14 * 15 * Development of this chipset driver was funded 16 * by the nice folks at National Semiconductor/AMD. 17 * 18 * This program is free software; you can redistribute it and/or modify it 19 * under the terms of the GNU General Public License version 2 as published by 20 * the Free Software Foundation. 21 * 22 * Documentation: 23 * CS5535 documentation available from AMD 24 */ 25 26#include <linux/module.h> 27#include <linux/pci.h> 28#include <linux/ide.h> 29 30#include "ide-timing.h" 31 32#define MSR_ATAC_BASE 0x51300000 33#define ATAC_GLD_MSR_CAP (MSR_ATAC_BASE+0) 34#define ATAC_GLD_MSR_CONFIG (MSR_ATAC_BASE+0x01) 35#define ATAC_GLD_MSR_SMI (MSR_ATAC_BASE+0x02) 36#define ATAC_GLD_MSR_ERROR (MSR_ATAC_BASE+0x03) 37#define ATAC_GLD_MSR_PM (MSR_ATAC_BASE+0x04) 38#define ATAC_GLD_MSR_DIAG (MSR_ATAC_BASE+0x05) 39#define ATAC_IO_BAR (MSR_ATAC_BASE+0x08) 40#define ATAC_RESET (MSR_ATAC_BASE+0x10) 41#define ATAC_CH0D0_PIO (MSR_ATAC_BASE+0x20) 42#define ATAC_CH0D0_DMA (MSR_ATAC_BASE+0x21) 43#define ATAC_CH0D1_PIO (MSR_ATAC_BASE+0x22) 44#define ATAC_CH0D1_DMA (MSR_ATAC_BASE+0x23) 45#define ATAC_PCI_ABRTERR (MSR_ATAC_BASE+0x24) 46#define ATAC_BM0_CMD_PRIM 0x00 47#define ATAC_BM0_STS_PRIM 0x02 48#define ATAC_BM0_PRD 0x04 49#define CS5535_CABLE_DETECT 0x48 50 51/* Format I PIO settings. We seperate out cmd and data for safer timings */ 52 53static unsigned int cs5535_pio_cmd_timings[5] = 54{ 0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131 }; 55static unsigned int cs5535_pio_dta_timings[5] = 56{ 0xF7F4, 0xF173, 0x8141, 0x5131, 0x1131 }; 57 58static unsigned int cs5535_mwdma_timings[3] = 59{ 0x7F0FFFF3, 0x7F035352, 0x7f024241 }; 60 61static unsigned int cs5535_udma_timings[5] = 62{ 0x7F7436A1, 0x7F733481, 0x7F723261, 0x7F713161, 0x7F703061 }; 63 64/* Macros to check if the register is the reset value - reset value is an 65 invalid timing and indicates the register has not been set previously */ 66 67#define CS5535_BAD_PIO(timings) ( (timings&~0x80000000UL) == 0x00009172 ) 68#define CS5535_BAD_DMA(timings) ( (timings & 0x000FFFFF) == 0x00077771 ) 69 70/**** 71 * cs5535_set_speed - Configure the chipset to the new speed 72 * @drive: Drive to set up 73 * @speed: desired speed 74 * 75 * cs5535_set_speed() configures the chipset to a new speed. 76 */ 77static void cs5535_set_speed(ide_drive_t *drive, u8 speed) 78{ 79 80 u32 reg = 0, dummy; 81 int unit = drive->select.b.unit; 82 83 84 /* Set the PIO timings */ 85 if ((speed & XFER_MODE) == XFER_PIO) { 86 u8 pioa; 87 u8 piob; 88 u8 cmd; 89 90 pioa = speed - XFER_PIO_0; 91 piob = ide_get_best_pio_mode(&(drive->hwif->drives[!unit]), 92 255, 4, NULL); 93 cmd = pioa < piob ? pioa : piob; 94 95 /* Write the speed of the current drive */ 96 reg = (cs5535_pio_cmd_timings[cmd] << 16) | 97 cs5535_pio_dta_timings[pioa]; 98 wrmsr(unit ? ATAC_CH0D1_PIO : ATAC_CH0D0_PIO, reg, 0); 99 100 /* And if nessesary - change the speed of the other drive */ 101 rdmsr(unit ? ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, dummy); 102 103 if (((reg >> 16) & cs5535_pio_cmd_timings[cmd]) != 104 cs5535_pio_cmd_timings[cmd]) { 105 reg &= 0x0000FFFF; 106 reg |= cs5535_pio_cmd_timings[cmd] << 16; 107 wrmsr(unit ? ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, 0); 108 } 109 110 /* Set bit 31 of the DMA register for PIO format 1 timings */ 111 rdmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy); 112 wrmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, 113 reg | 0x80000000UL, 0); 114 } else { 115 rdmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy); 116 117 reg &= 0x80000000UL; /* Preserve the PIO format bit */ 118 119 if (speed >= XFER_UDMA_0 && speed <= XFER_UDMA_7) 120 reg |= cs5535_udma_timings[speed - XFER_UDMA_0]; 121 else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2) 122 reg |= cs5535_mwdma_timings[speed - XFER_MW_DMA_0]; 123 else 124 return; 125 126 wrmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, 0); 127 } 128} 129 130/**** 131 * cs5535_set_drive - Configure the drive to the new speed 132 * @drive: Drive to set up 133 * @speed: desired speed 134 * 135 * cs5535_set_drive() configures the drive and the chipset to a 136 * new speed. It also can be called by upper layers. 137 */ 138static int cs5535_set_drive(ide_drive_t *drive, u8 speed) 139{ 140 speed = ide_rate_filter(drive, speed); 141 ide_config_drive_speed(drive, speed); 142 cs5535_set_speed(drive, speed); 143 144 return 0; 145} 146 147/**** 148 * cs5535_tuneproc - PIO setup 149 * @drive: drive to set up 150 * @pio: mode to use (255 for 'best possible') 151 * 152 * A callback from the upper layers for PIO-only tuning. 153 */ 154static void cs5535_tuneproc(ide_drive_t *drive, u8 xferspeed) 155{ 156 u8 modes[] = { XFER_PIO_0, XFER_PIO_1, XFER_PIO_2, XFER_PIO_3, 157 XFER_PIO_4 }; 158 159 /* cs5535 max pio is pio 4, best_pio will check the blacklist. 160 i think we don't need to rate_filter the incoming xferspeed 161 since we know we're only going to choose pio */ 162 xferspeed = ide_get_best_pio_mode(drive, xferspeed, 4, NULL); 163 ide_config_drive_speed(drive, modes[xferspeed]); 164 cs5535_set_speed(drive, xferspeed); 165} 166 167static int cs5535_dma_check(ide_drive_t *drive) 168{ 169 u8 speed; 170 171 drive->init_speed = 0; 172 173 if (ide_tune_dma(drive)) 174 return 0; 175 176 if (ide_use_fast_pio(drive)) { 177 speed = ide_get_best_pio_mode(drive, 255, 4, NULL); 178 cs5535_set_drive(drive, speed); 179 } 180 181 return -1; 182} 183 184static u8 __devinit cs5535_cable_detect(struct pci_dev *dev) 185{ 186 u8 bit; 187 188 /* if a 80 wire cable was detected */ 189 pci_read_config_byte(dev, CS5535_CABLE_DETECT, &bit); 190 return (bit & 1); 191} 192 193/**** 194 * init_hwif_cs5535 - Initialize one ide cannel 195 * @hwif: Channel descriptor 196 * 197 * This gets invoked by the IDE driver once for each channel. It 198 * performs channel-specific pre-initialization before drive probing. 199 * 200 */ 201static void __devinit init_hwif_cs5535(ide_hwif_t *hwif) 202{ 203 int i; 204 205 hwif->autodma = 0; 206 207 hwif->tuneproc = &cs5535_tuneproc; 208 hwif->speedproc = &cs5535_set_drive; 209 hwif->ide_dma_check = &cs5535_dma_check; 210 211 hwif->atapi_dma = 1; 212 hwif->ultra_mask = 0x1F; 213 hwif->mwdma_mask = 0x07; 214 215 216 hwif->udma_four = cs5535_cable_detect(hwif->pci_dev); 217 218 if (!noautodma) 219 hwif->autodma = 1; 220 221 /* just setting autotune and not worrying about bios timings */ 222 for (i = 0; i < 2; i++) { 223 hwif->drives[i].autotune = 1; 224 hwif->drives[i].autodma = hwif->autodma; 225 } 226} 227 228static ide_pci_device_t cs5535_chipset __devinitdata = { 229 .name = "CS5535", 230 .init_hwif = init_hwif_cs5535, 231 .channels = 1, 232 .autodma = AUTODMA, 233 .bootable = ON_BOARD, 234}; 235 236static int __devinit cs5535_init_one(struct pci_dev *dev, 237 const struct pci_device_id *id) 238{ 239 return ide_setup_pci_device(dev, &cs5535_chipset); 240} 241 242static struct pci_device_id cs5535_pci_tbl[] = 243{ 244 { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_CS5535_IDE, PCI_ANY_ID, 245 PCI_ANY_ID, 0, 0, 0}, 246 { 0, }, 247}; 248 249MODULE_DEVICE_TABLE(pci, cs5535_pci_tbl); 250 251static struct pci_driver driver = { 252 .name = "CS5535_IDE", 253 .id_table = cs5535_pci_tbl, 254 .probe = cs5535_init_one, 255}; 256 257static int __init cs5535_ide_init(void) 258{ 259 return ide_pci_register_driver(&driver); 260} 261 262module_init(cs5535_ide_init); 263 264MODULE_AUTHOR("AMD"); 265MODULE_DESCRIPTION("PCI driver module for AMD/NS CS5535 IDE"); 266MODULE_LICENSE("GPL"); 267