1/* 2 * linux/drivers/ide/pci/alim15x3.c Version 0.21 2007/02/03 3 * 4 * Copyright (C) 1998-2000 Michel Aubry, Maintainer 5 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz, Maintainer 6 * Copyright (C) 1999-2000 CJ, cjtsai@ali.com.tw, Maintainer 7 * 8 * Copyright (C) 1998-2000 Andre Hedrick (andre@linux-ide.org) 9 * May be copied or modified under the terms of the GNU General Public License 10 * Copyright (C) 2002 Alan Cox <alan@redhat.com> 11 * ALi (now ULi M5228) support by Clear Zhang <Clear.Zhang@ali.com.tw> 12 * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com> 13 * 14 * (U)DMA capable version of ali 1533/1543(C), 1535(D) 15 * 16 ********************************************************************** 17 * 9/7/99 --Parts from the above author are included and need to be 18 * converted into standard interface, once I finish the thought. 19 * 20 * Recent changes 21 * Don't use LBA48 mode on ALi <= 0xC4 22 * Don't poke 0x79 with a non ALi northbridge 23 * Don't flip undefined bits on newer chipsets (fix Fujitsu laptop hang) 24 * Allow UDMA6 on revisions > 0xC4 25 * 26 * Documentation 27 * Chipset documentation available under NDA only 28 * 29 */ 30 31#include <linux/module.h> 32#include <linux/types.h> 33#include <linux/kernel.h> 34#include <linux/pci.h> 35#include <linux/delay.h> 36#include <linux/hdreg.h> 37#include <linux/ide.h> 38#include <linux/init.h> 39 40#include <asm/io.h> 41 42#define DISPLAY_ALI_TIMINGS 43 44/* 45 * ALi devices are not plug in. Otherwise these static values would 46 * need to go. They ought to go away anyway 47 */ 48 49static u8 m5229_revision; 50static u8 chip_is_1543c_e; 51static struct pci_dev *isa_dev; 52 53#if defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_IDE_PROC_FS) 54#include <linux/stat.h> 55#include <linux/proc_fs.h> 56 57static u8 ali_proc = 0; 58 59static struct pci_dev *bmide_dev; 60 61static char *fifo[4] = { 62 "FIFO Off", 63 "FIFO On ", 64 "DMA mode", 65 "PIO mode" }; 66 67static char *udmaT[8] = { 68 "1.5T", 69 " 2T", 70 "2.5T", 71 " 3T", 72 "3.5T", 73 " 4T", 74 " 6T", 75 " 8T" 76}; 77 78static char *channel_status[8] = { 79 "OK ", 80 "busy ", 81 "DRQ ", 82 "DRQ busy ", 83 "error ", 84 "error busy ", 85 "error DRQ ", 86 "error DRQ busy" 87}; 88 89/** 90 * ali_get_info - generate proc file for ALi IDE 91 * @buffer: buffer to fill 92 * @addr: address of user start in buffer 93 * @offset: offset into 'file' 94 * @count: buffer count 95 * 96 * Walks the Ali devices and outputs summary data on the tuning and 97 * anything else that will help with debugging 98 */ 99 100static int ali_get_info (char *buffer, char **addr, off_t offset, int count) 101{ 102 unsigned long bibma; 103 u8 reg53h, reg5xh, reg5yh, reg5xh1, reg5yh1, c0, c1, rev, tmp; 104 char *q, *p = buffer; 105 106 /* fetch rev. */ 107 pci_read_config_byte(bmide_dev, 0x08, &rev); 108 if (rev >= 0xc1) /* M1543C or newer */ 109 udmaT[7] = " ???"; 110 else 111 fifo[3] = " ??? "; 112 113 /* first fetch bibma: */ 114 115 bibma = pci_resource_start(bmide_dev, 4); 116 117 /* 118 * at that point bibma+0x2 et bibma+0xa are byte 119 * registers to investigate: 120 */ 121 c0 = inb(bibma + 0x02); 122 c1 = inb(bibma + 0x0a); 123 124 p += sprintf(p, 125 "\n Ali M15x3 Chipset.\n"); 126 p += sprintf(p, 127 " ------------------\n"); 128 pci_read_config_byte(bmide_dev, 0x78, ®53h); 129 p += sprintf(p, "PCI Clock: %d.\n", reg53h); 130 131 pci_read_config_byte(bmide_dev, 0x53, ®53h); 132 p += sprintf(p, 133 "CD_ROM FIFO:%s, CD_ROM DMA:%s\n", 134 (reg53h & 0x02) ? "Yes" : "No ", 135 (reg53h & 0x01) ? "Yes" : "No " ); 136 pci_read_config_byte(bmide_dev, 0x74, ®53h); 137 p += sprintf(p, 138 "FIFO Status: contains %d Words, runs%s%s\n\n", 139 (reg53h & 0x3f), 140 (reg53h & 0x40) ? " OVERWR" : "", 141 (reg53h & 0x80) ? " OVERRD." : "." ); 142 143 p += sprintf(p, 144 "-------------------primary channel" 145 "-------------------secondary channel" 146 "---------\n\n"); 147 148 pci_read_config_byte(bmide_dev, 0x09, ®53h); 149 p += sprintf(p, 150 "channel status: %s" 151 " %s\n", 152 (reg53h & 0x20) ? "On " : "Off", 153 (reg53h & 0x10) ? "On " : "Off" ); 154 155 p += sprintf(p, 156 "both channels togth: %s" 157 " %s\n", 158 (c0&0x80) ? "No " : "Yes", 159 (c1&0x80) ? "No " : "Yes" ); 160 161 pci_read_config_byte(bmide_dev, 0x76, ®53h); 162 p += sprintf(p, 163 "Channel state: %s %s\n", 164 channel_status[reg53h & 0x07], 165 channel_status[(reg53h & 0x70) >> 4] ); 166 167 pci_read_config_byte(bmide_dev, 0x58, ®5xh); 168 pci_read_config_byte(bmide_dev, 0x5c, ®5yh); 169 p += sprintf(p, 170 "Add. Setup Timing: %dT" 171 " %dT\n", 172 (reg5xh & 0x07) ? (reg5xh & 0x07) : 8, 173 (reg5yh & 0x07) ? (reg5yh & 0x07) : 8 ); 174 175 pci_read_config_byte(bmide_dev, 0x59, ®5xh); 176 pci_read_config_byte(bmide_dev, 0x5d, ®5yh); 177 p += sprintf(p, 178 "Command Act. Count: %dT" 179 " %dT\n" 180 "Command Rec. Count: %dT" 181 " %dT\n\n", 182 (reg5xh & 0x70) ? ((reg5xh & 0x70) >> 4) : 8, 183 (reg5yh & 0x70) ? ((reg5yh & 0x70) >> 4) : 8, 184 (reg5xh & 0x0f) ? (reg5xh & 0x0f) : 16, 185 (reg5yh & 0x0f) ? (reg5yh & 0x0f) : 16 ); 186 187 p += sprintf(p, 188 "----------------drive0-----------drive1" 189 "------------drive0-----------drive1------\n\n"); 190 p += sprintf(p, 191 "DMA enabled: %s %s" 192 " %s %s\n", 193 (c0&0x20) ? "Yes" : "No ", 194 (c0&0x40) ? "Yes" : "No ", 195 (c1&0x20) ? "Yes" : "No ", 196 (c1&0x40) ? "Yes" : "No " ); 197 198 pci_read_config_byte(bmide_dev, 0x54, ®5xh); 199 pci_read_config_byte(bmide_dev, 0x55, ®5yh); 200 q = "FIFO threshold: %2d Words %2d Words" 201 " %2d Words %2d Words\n"; 202 if (rev < 0xc1) { 203 if ((rev == 0x20) && 204 (pci_read_config_byte(bmide_dev, 0x4f, &tmp), (tmp &= 0x20))) { 205 p += sprintf(p, q, 8, 8, 8, 8); 206 } else { 207 p += sprintf(p, q, 208 (reg5xh & 0x03) + 12, 209 ((reg5xh & 0x30)>>4) + 12, 210 (reg5yh & 0x03) + 12, 211 ((reg5yh & 0x30)>>4) + 12 ); 212 } 213 } else { 214 int t1 = (tmp = (reg5xh & 0x03)) ? (tmp << 3) : 4; 215 int t2 = (tmp = ((reg5xh & 0x30)>>4)) ? (tmp << 3) : 4; 216 int t3 = (tmp = (reg5yh & 0x03)) ? (tmp << 3) : 4; 217 int t4 = (tmp = ((reg5yh & 0x30)>>4)) ? (tmp << 3) : 4; 218 p += sprintf(p, q, t1, t2, t3, t4); 219 } 220 221 222 p += sprintf(p, 223 "FIFO mode: %s %s %s %s\n", 224 fifo[((reg5xh & 0x0c) >> 2)], 225 fifo[((reg5xh & 0xc0) >> 6)], 226 fifo[((reg5yh & 0x0c) >> 2)], 227 fifo[((reg5yh & 0xc0) >> 6)] ); 228 229 pci_read_config_byte(bmide_dev, 0x5a, ®5xh); 230 pci_read_config_byte(bmide_dev, 0x5b, ®5xh1); 231 pci_read_config_byte(bmide_dev, 0x5e, ®5yh); 232 pci_read_config_byte(bmide_dev, 0x5f, ®5yh1); 233 234 p += sprintf(p,/* 235 "------------------drive0-----------drive1" 236 "------------drive0-----------drive1------\n")*/ 237 "Dt RW act. Cnt %2dT %2dT" 238 " %2dT %2dT\n" 239 "Dt RW rec. Cnt %2dT %2dT" 240 " %2dT %2dT\n\n", 241 (reg5xh & 0x70) ? ((reg5xh & 0x70) >> 4) : 8, 242 (reg5xh1 & 0x70) ? ((reg5xh1 & 0x70) >> 4) : 8, 243 (reg5yh & 0x70) ? ((reg5yh & 0x70) >> 4) : 8, 244 (reg5yh1 & 0x70) ? ((reg5yh1 & 0x70) >> 4) : 8, 245 (reg5xh & 0x0f) ? (reg5xh & 0x0f) : 16, 246 (reg5xh1 & 0x0f) ? (reg5xh1 & 0x0f) : 16, 247 (reg5yh & 0x0f) ? (reg5yh & 0x0f) : 16, 248 (reg5yh1 & 0x0f) ? (reg5yh1 & 0x0f) : 16 ); 249 250 p += sprintf(p, 251 "-----------------------------------UDMA Timings" 252 "--------------------------------\n\n"); 253 254 pci_read_config_byte(bmide_dev, 0x56, ®5xh); 255 pci_read_config_byte(bmide_dev, 0x57, ®5yh); 256 p += sprintf(p, 257 "UDMA: %s %s" 258 " %s %s\n" 259 "UDMA timings: %s %s" 260 " %s %s\n\n", 261 (reg5xh & 0x08) ? "OK" : "No", 262 (reg5xh & 0x80) ? "OK" : "No", 263 (reg5yh & 0x08) ? "OK" : "No", 264 (reg5yh & 0x80) ? "OK" : "No", 265 udmaT[(reg5xh & 0x07)], 266 udmaT[(reg5xh & 0x70) >> 4], 267 udmaT[reg5yh & 0x07], 268 udmaT[(reg5yh & 0x70) >> 4] ); 269 270 return p-buffer; /* => must be less than 4k! */ 271} 272#endif /* defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_IDE_PROC_FS) */ 273 274/** 275 * ali15x3_tune_pio - set up chipset for PIO mode 276 * @drive: drive to tune 277 * @pio: desired mode 278 * 279 * Select the best PIO mode for the drive in question. 280 * Then program the controller for this mode. 281 * 282 * Returns the PIO mode programmed. 283 */ 284 285static u8 ali15x3_tune_pio (ide_drive_t *drive, u8 pio) 286{ 287 ide_pio_data_t d; 288 ide_hwif_t *hwif = HWIF(drive); 289 struct pci_dev *dev = hwif->pci_dev; 290 int s_time, a_time, c_time; 291 u8 s_clc, a_clc, r_clc; 292 unsigned long flags; 293 int bus_speed = system_bus_clock(); 294 int port = hwif->channel ? 0x5c : 0x58; 295 int portFIFO = hwif->channel ? 0x55 : 0x54; 296 u8 cd_dma_fifo = 0; 297 int unit = drive->select.b.unit & 1; 298 299 pio = ide_get_best_pio_mode(drive, pio, 5, &d); 300 s_time = ide_pio_timings[pio].setup_time; 301 a_time = ide_pio_timings[pio].active_time; 302 if ((s_clc = (s_time * bus_speed + 999) / 1000) >= 8) 303 s_clc = 0; 304 if ((a_clc = (a_time * bus_speed + 999) / 1000) >= 8) 305 a_clc = 0; 306 c_time = ide_pio_timings[pio].cycle_time; 307 308 309 if (!(r_clc = (c_time * bus_speed + 999) / 1000 - a_clc - s_clc)) { 310 r_clc = 1; 311 } else { 312 if (r_clc >= 16) 313 r_clc = 0; 314 } 315 local_irq_save(flags); 316 317 /* 318 * PIO mode => ATA FIFO on, ATAPI FIFO off 319 */ 320 pci_read_config_byte(dev, portFIFO, &cd_dma_fifo); 321 if (drive->media==ide_disk) { 322 if (unit) { 323 pci_write_config_byte(dev, portFIFO, (cd_dma_fifo & 0x0F) | 0x50); 324 } else { 325 pci_write_config_byte(dev, portFIFO, (cd_dma_fifo & 0xF0) | 0x05); 326 } 327 } else { 328 if (unit) { 329 pci_write_config_byte(dev, portFIFO, cd_dma_fifo & 0x0F); 330 } else { 331 pci_write_config_byte(dev, portFIFO, cd_dma_fifo & 0xF0); 332 } 333 } 334 335 pci_write_config_byte(dev, port, s_clc); 336 pci_write_config_byte(dev, port+drive->select.b.unit+2, (a_clc << 4) | r_clc); 337 local_irq_restore(flags); 338 339 /* 340 * setup active rec 341 * { 70, 165, 365 }, PIO Mode 0 342 * { 50, 125, 208 }, PIO Mode 1 343 * { 30, 100, 110 }, PIO Mode 2 344 * { 30, 80, 70 }, PIO Mode 3 with IORDY 345 * { 25, 70, 25 }, PIO Mode 4 with IORDY ns 346 * { 20, 50, 30 } PIO Mode 5 with IORDY (nonstandard) 347 */ 348 349 return pio; 350} 351 352/** 353 * ali15x3_tune_drive - set up drive for PIO mode 354 * @drive: drive to tune 355 * @pio: desired mode 356 * 357 * Program the controller with the best PIO timing for the given drive. 358 * Then set up the drive itself. 359 */ 360 361static void ali15x3_tune_drive (ide_drive_t *drive, u8 pio) 362{ 363 pio = ali15x3_tune_pio(drive, pio); 364 (void) ide_config_drive_speed(drive, XFER_PIO_0 + pio); 365} 366 367 368static u8 ali_udma_filter(ide_drive_t *drive) 369{ 370 if (m5229_revision > 0x20 && m5229_revision < 0xC2) { 371 if (drive->media != ide_disk) 372 return 0; 373#ifndef CONFIG_WDC_ALI15X3 374 if (chip_is_1543c_e && strstr(drive->id->model, "WDC ")) 375 return 0; 376#endif 377 } 378 379 return drive->hwif->ultra_mask; 380} 381 382/** 383 * ali15x3_tune_chipset - set up chipset/drive for new speed 384 * @drive: drive to configure for 385 * @xferspeed: desired speed 386 * 387 * Configure the hardware for the desired IDE transfer mode. 388 * We also do the needed drive configuration through helpers 389 */ 390 391static int ali15x3_tune_chipset (ide_drive_t *drive, u8 xferspeed) 392{ 393 ide_hwif_t *hwif = HWIF(drive); 394 struct pci_dev *dev = hwif->pci_dev; 395 u8 speed = ide_rate_filter(drive, xferspeed); 396 u8 speed1 = speed; 397 u8 unit = (drive->select.b.unit & 0x01); 398 u8 tmpbyte = 0x00; 399 int m5229_udma = (hwif->channel) ? 0x57 : 0x56; 400 401 if (speed == XFER_UDMA_6) 402 speed1 = 0x47; 403 404 if (speed < XFER_UDMA_0) { 405 u8 ultra_enable = (unit) ? 0x7f : 0xf7; 406 /* 407 * clear "ultra enable" bit 408 */ 409 pci_read_config_byte(dev, m5229_udma, &tmpbyte); 410 tmpbyte &= ultra_enable; 411 pci_write_config_byte(dev, m5229_udma, tmpbyte); 412 413 if (speed < XFER_SW_DMA_0) 414 (void) ali15x3_tune_pio(drive, speed - XFER_PIO_0); 415 } else { 416 pci_read_config_byte(dev, m5229_udma, &tmpbyte); 417 tmpbyte &= (0x0f << ((1-unit) << 2)); 418 /* 419 * enable ultra dma and set timing 420 */ 421 tmpbyte |= ((0x08 | ((4-speed1)&0x07)) << (unit << 2)); 422 pci_write_config_byte(dev, m5229_udma, tmpbyte); 423 if (speed >= XFER_UDMA_3) { 424 pci_read_config_byte(dev, 0x4b, &tmpbyte); 425 tmpbyte |= 1; 426 pci_write_config_byte(dev, 0x4b, tmpbyte); 427 } 428 } 429 return (ide_config_drive_speed(drive, speed)); 430} 431 432/** 433 * ali15x3_config_drive_for_dma - configure for DMA 434 * @drive: drive to configure 435 * 436 * Configure a drive for DMA operation. If DMA is not possible we 437 * drop the drive into PIO mode instead. 438 */ 439 440static int ali15x3_config_drive_for_dma(ide_drive_t *drive) 441{ 442 drive->init_speed = 0; 443 444 if (ide_tune_dma(drive)) 445 return 0; 446 447 ali15x3_tune_drive(drive, 255); 448 449 return -1; 450} 451 452/** 453 * ali15x3_dma_setup - begin a DMA phase 454 * @drive: target device 455 * 456 * Returns 1 if the DMA cannot be performed, zero on success. 457 */ 458 459static int ali15x3_dma_setup(ide_drive_t *drive) 460{ 461 if (m5229_revision < 0xC2 && drive->media != ide_disk) { 462 if (rq_data_dir(drive->hwif->hwgroup->rq)) 463 return 1; /* try PIO instead of DMA */ 464 } 465 return ide_dma_setup(drive); 466} 467 468/** 469 * init_chipset_ali15x3 - Initialise an ALi IDE controller 470 * @dev: PCI device 471 * @name: Name of the controller 472 * 473 * This function initializes the ALI IDE controller and where 474 * appropriate also sets up the 1533 southbridge. 475 */ 476 477static unsigned int __devinit init_chipset_ali15x3 (struct pci_dev *dev, const char *name) 478{ 479 unsigned long flags; 480 u8 tmpbyte; 481 struct pci_dev *north = pci_get_slot(dev->bus, PCI_DEVFN(0,0)); 482 483 pci_read_config_byte(dev, PCI_REVISION_ID, &m5229_revision); 484 485 isa_dev = pci_get_device(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, NULL); 486 487#if defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_IDE_PROC_FS) 488 if (!ali_proc) { 489 ali_proc = 1; 490 bmide_dev = dev; 491 ide_pci_create_host_proc("ali", ali_get_info); 492 } 493#endif /* defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_IDE_PROC_FS) */ 494 495 local_irq_save(flags); 496 497 if (m5229_revision < 0xC2) { 498 /* 499 * revision 0x20 (1543-E, 1543-F) 500 * revision 0xC0, 0xC1 (1543C-C, 1543C-D, 1543C-E) 501 * clear CD-ROM DMA write bit, m5229, 0x4b, bit 7 502 */ 503 pci_read_config_byte(dev, 0x4b, &tmpbyte); 504 /* 505 * clear bit 7 506 */ 507 pci_write_config_byte(dev, 0x4b, tmpbyte & 0x7F); 508 goto out; 509 } 510 511 /* 512 * 1543C-B?, 1535, 1535D, 1553 513 * Note 1: not all "motherboard" support this detection 514 * Note 2: if no udma 66 device, the detection may "error". 515 * but in this case, we will not set the device to 516 * ultra 66, the detection result is not important 517 */ 518 519 /* 520 * enable "Cable Detection", m5229, 0x4b, bit3 521 */ 522 pci_read_config_byte(dev, 0x4b, &tmpbyte); 523 pci_write_config_byte(dev, 0x4b, tmpbyte | 0x08); 524 525 /* 526 * We should only tune the 1533 enable if we are using an ALi 527 * North bridge. We might have no north found on some zany 528 * box without a device at 0:0.0. The ALi bridge will be at 529 * 0:0.0 so if we didn't find one we know what is cooking. 530 */ 531 if (north && north->vendor != PCI_VENDOR_ID_AL) 532 goto out; 533 534 if (m5229_revision < 0xC5 && isa_dev) 535 { 536 /* 537 * set south-bridge's enable bit, m1533, 0x79 538 */ 539 540 pci_read_config_byte(isa_dev, 0x79, &tmpbyte); 541 if (m5229_revision == 0xC2) { 542 /* 543 * 1543C-B0 (m1533, 0x79, bit 2) 544 */ 545 pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x04); 546 } else if (m5229_revision >= 0xC3) { 547 /* 548 * 1553/1535 (m1533, 0x79, bit 1) 549 */ 550 pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x02); 551 } 552 } 553out: 554 pci_dev_put(north); 555 pci_dev_put(isa_dev); 556 local_irq_restore(flags); 557 return 0; 558} 559 560 561static unsigned int __devinit ata66_ali15x3 (ide_hwif_t *hwif) 562{ 563 struct pci_dev *dev = hwif->pci_dev; 564 unsigned int ata66 = 0; 565 u8 cable_80_pin[2] = { 0, 0 }; 566 567 unsigned long flags; 568 u8 tmpbyte; 569 570 local_irq_save(flags); 571 572 if (m5229_revision >= 0xC2) { 573 /* 574 * Ultra66 cable detection (from Host View) 575 * m5229, 0x4a, bit0: primary, bit1: secondary 80 pin 576 */ 577 pci_read_config_byte(dev, 0x4a, &tmpbyte); 578 /* 579 * 0x4a, bit0 is 0 => primary channel 580 * has 80-pin (from host view) 581 */ 582 if (!(tmpbyte & 0x01)) cable_80_pin[0] = 1; 583 /* 584 * 0x4a, bit1 is 0 => secondary channel 585 * has 80-pin (from host view) 586 */ 587 if (!(tmpbyte & 0x02)) cable_80_pin[1] = 1; 588 /* 589 * Allow ata66 if cable of current channel has 80 pins 590 */ 591 ata66 = (hwif->channel)?cable_80_pin[1]:cable_80_pin[0]; 592 } else { 593 /* 594 * check m1533, 0x5e, bit 1~4 == 1001 => & 00011110 = 00010010 595 */ 596 pci_read_config_byte(isa_dev, 0x5e, &tmpbyte); 597 chip_is_1543c_e = ((tmpbyte & 0x1e) == 0x12) ? 1: 0; 598 } 599 600 /* 601 * CD_ROM DMA on (m5229, 0x53, bit0) 602 * Enable this bit even if we want to use PIO 603 * PIO FIFO off (m5229, 0x53, bit1) 604 * The hardware will use 0x54h and 0x55h to control PIO FIFO 605 * (Not on later devices it seems) 606 * 607 * 0x53 changes meaning on later revs - we must no touch 608 * bit 1 on them. Need to check if 0x20 is the right break 609 */ 610 611 pci_read_config_byte(dev, 0x53, &tmpbyte); 612 613 if(m5229_revision <= 0x20) 614 tmpbyte = (tmpbyte & (~0x02)) | 0x01; 615 else if (m5229_revision == 0xc7 || m5229_revision == 0xc8) 616 tmpbyte |= 0x03; 617 else 618 tmpbyte |= 0x01; 619 620 pci_write_config_byte(dev, 0x53, tmpbyte); 621 622 local_irq_restore(flags); 623 624 return(ata66); 625} 626 627/** 628 * init_hwif_common_ali15x3 - Set up ALI IDE hardware 629 * @hwif: IDE interface 630 * 631 * Initialize the IDE structure side of the ALi 15x3 driver. 632 */ 633 634static void __devinit init_hwif_common_ali15x3 (ide_hwif_t *hwif) 635{ 636 hwif->autodma = 0; 637 hwif->tuneproc = &ali15x3_tune_drive; 638 hwif->speedproc = &ali15x3_tune_chipset; 639 hwif->udma_filter = &ali_udma_filter; 640 641 /* don't use LBA48 DMA on ALi devices before rev 0xC5 */ 642 hwif->no_lba48_dma = (m5229_revision <= 0xC4) ? 1 : 0; 643 644 if (!hwif->dma_base) { 645 hwif->drives[0].autotune = 1; 646 hwif->drives[1].autotune = 1; 647 return; 648 } 649 650 if (m5229_revision > 0x20) 651 hwif->atapi_dma = 1; 652 653 if (m5229_revision <= 0x20) 654 hwif->ultra_mask = 0x00; /* no udma */ 655 else if (m5229_revision < 0xC2) 656 hwif->ultra_mask = 0x07; /* udma0-2 */ 657 else if (m5229_revision == 0xC2 || m5229_revision == 0xC3) 658 hwif->ultra_mask = 0x1f; /* udma0-4 */ 659 else if (m5229_revision == 0xC4) 660 hwif->ultra_mask = 0x3f; /* udma0-5 */ 661 else 662 hwif->ultra_mask = 0x7f; /* udma0-6 */ 663 664 hwif->mwdma_mask = 0x07; 665 hwif->swdma_mask = 0x07; 666 667 if (m5229_revision >= 0x20) { 668 /* 669 * M1543C or newer for DMAing 670 */ 671 hwif->ide_dma_check = &ali15x3_config_drive_for_dma; 672 hwif->dma_setup = &ali15x3_dma_setup; 673 if (!noautodma) 674 hwif->autodma = 1; 675 if (!(hwif->udma_four)) 676 hwif->udma_four = ata66_ali15x3(hwif); 677 } 678 hwif->drives[0].autodma = hwif->autodma; 679 hwif->drives[1].autodma = hwif->autodma; 680} 681 682/** 683 * init_hwif_ali15x3 - Initialize the ALI IDE x86 stuff 684 * @hwif: interface to configure 685 * 686 * Obtain the IRQ tables for an ALi based IDE solution on the PC 687 * class platforms. This part of the code isn't applicable to the 688 * Sparc systems 689 */ 690 691static void __devinit init_hwif_ali15x3 (ide_hwif_t *hwif) 692{ 693 u8 ideic, inmir; 694 s8 irq_routing_table[] = { -1, 9, 3, 10, 4, 5, 7, 6, 695 1, 11, 0, 12, 0, 14, 0, 15 }; 696 int irq = -1; 697 698 if (hwif->pci_dev->device == PCI_DEVICE_ID_AL_M5229) 699 hwif->irq = hwif->channel ? 15 : 14; 700 701 if (isa_dev) { 702 /* 703 * read IDE interface control 704 */ 705 pci_read_config_byte(isa_dev, 0x58, &ideic); 706 707 /* bit0, bit1 */ 708 ideic = ideic & 0x03; 709 710 /* get IRQ for IDE Controller */ 711 if ((hwif->channel && ideic == 0x03) || 712 (!hwif->channel && !ideic)) { 713 /* 714 * get SIRQ1 routing table 715 */ 716 pci_read_config_byte(isa_dev, 0x44, &inmir); 717 inmir = inmir & 0x0f; 718 irq = irq_routing_table[inmir]; 719 } else if (hwif->channel && !(ideic & 0x01)) { 720 /* 721 * get SIRQ2 routing table 722 */ 723 pci_read_config_byte(isa_dev, 0x75, &inmir); 724 inmir = inmir & 0x0f; 725 irq = irq_routing_table[inmir]; 726 } 727 if(irq >= 0) 728 hwif->irq = irq; 729 } 730 731 init_hwif_common_ali15x3(hwif); 732} 733 734/** 735 * init_dma_ali15x3 - set up DMA on ALi15x3 736 * @hwif: IDE interface 737 * @dmabase: DMA interface base PCI address 738 * 739 * Set up the DMA functionality on the ALi 15x3. For the ALi 740 * controllers this is generic so we can let the generic code do 741 * the actual work. 742 */ 743 744static void __devinit init_dma_ali15x3 (ide_hwif_t *hwif, unsigned long dmabase) 745{ 746 if (m5229_revision < 0x20) 747 return; 748 if (!hwif->channel) 749 outb(inb(dmabase + 2) & 0x60, dmabase + 2); 750 ide_setup_dma(hwif, dmabase, 8); 751} 752 753static ide_pci_device_t ali15x3_chipset __devinitdata = { 754 .name = "ALI15X3", 755 .init_chipset = init_chipset_ali15x3, 756 .init_hwif = init_hwif_ali15x3, 757 .init_dma = init_dma_ali15x3, 758 .channels = 2, 759 .autodma = AUTODMA, 760 .bootable = ON_BOARD, 761}; 762 763/** 764 * alim15x3_init_one - set up an ALi15x3 IDE controller 765 * @dev: PCI device to set up 766 * 767 * Perform the actual set up for an ALi15x3 that has been found by the 768 * hot plug layer. 769 */ 770 771static int __devinit alim15x3_init_one(struct pci_dev *dev, const struct pci_device_id *id) 772{ 773 static struct pci_device_id ati_rs100[] = { 774 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100) }, 775 { }, 776 }; 777 778 ide_pci_device_t *d = &ali15x3_chipset; 779 780 if (pci_dev_present(ati_rs100)) 781 printk(KERN_WARNING "alim15x3: ATI Radeon IGP Northbridge is not yet fully tested.\n"); 782 783#if defined(CONFIG_SPARC64) 784 d->init_hwif = init_hwif_common_ali15x3; 785#endif /* CONFIG_SPARC64 */ 786 return ide_setup_pci_device(dev, d); 787} 788 789 790static struct pci_device_id alim15x3_pci_tbl[] = { 791 { PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M5229, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 792 { PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M5228, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 793 { 0, }, 794}; 795MODULE_DEVICE_TABLE(pci, alim15x3_pci_tbl); 796 797static struct pci_driver driver = { 798 .name = "ALI15x3_IDE", 799 .id_table = alim15x3_pci_tbl, 800 .probe = alim15x3_init_one, 801}; 802 803static int __init ali15x3_ide_init(void) 804{ 805 return ide_pci_register_driver(&driver); 806} 807 808module_init(ali15x3_ide_init); 809 810MODULE_AUTHOR("Michael Aubry, Andrzej Krzysztofowicz, CJ, Andre Hedrick, Alan Cox"); 811MODULE_DESCRIPTION("PCI driver module for ALi 15x3 IDE"); 812MODULE_LICENSE("GPL"); 813