1/* 2 * linux/drivers/ide/pci/aec62xx.c Version 0.21 Apr 21, 2007 3 * 4 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org> 5 * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com> 6 * 7 */ 8 9#include <linux/module.h> 10#include <linux/types.h> 11#include <linux/pci.h> 12#include <linux/delay.h> 13#include <linux/hdreg.h> 14#include <linux/ide.h> 15#include <linux/init.h> 16 17#include <asm/io.h> 18 19struct chipset_bus_clock_list_entry { 20 u8 xfer_speed; 21 u8 chipset_settings; 22 u8 ultra_settings; 23}; 24 25static const struct chipset_bus_clock_list_entry aec6xxx_33_base [] = { 26 { XFER_UDMA_6, 0x31, 0x07 }, 27 { XFER_UDMA_5, 0x31, 0x06 }, 28 { XFER_UDMA_4, 0x31, 0x05 }, 29 { XFER_UDMA_3, 0x31, 0x04 }, 30 { XFER_UDMA_2, 0x31, 0x03 }, 31 { XFER_UDMA_1, 0x31, 0x02 }, 32 { XFER_UDMA_0, 0x31, 0x01 }, 33 34 { XFER_MW_DMA_2, 0x31, 0x00 }, 35 { XFER_MW_DMA_1, 0x31, 0x00 }, 36 { XFER_MW_DMA_0, 0x0a, 0x00 }, 37 { XFER_PIO_4, 0x31, 0x00 }, 38 { XFER_PIO_3, 0x33, 0x00 }, 39 { XFER_PIO_2, 0x08, 0x00 }, 40 { XFER_PIO_1, 0x0a, 0x00 }, 41 { XFER_PIO_0, 0x00, 0x00 }, 42 { 0, 0x00, 0x00 } 43}; 44 45static const struct chipset_bus_clock_list_entry aec6xxx_34_base [] = { 46 { XFER_UDMA_6, 0x41, 0x06 }, 47 { XFER_UDMA_5, 0x41, 0x05 }, 48 { XFER_UDMA_4, 0x41, 0x04 }, 49 { XFER_UDMA_3, 0x41, 0x03 }, 50 { XFER_UDMA_2, 0x41, 0x02 }, 51 { XFER_UDMA_1, 0x41, 0x01 }, 52 { XFER_UDMA_0, 0x41, 0x01 }, 53 54 { XFER_MW_DMA_2, 0x41, 0x00 }, 55 { XFER_MW_DMA_1, 0x42, 0x00 }, 56 { XFER_MW_DMA_0, 0x7a, 0x00 }, 57 { XFER_PIO_4, 0x41, 0x00 }, 58 { XFER_PIO_3, 0x43, 0x00 }, 59 { XFER_PIO_2, 0x78, 0x00 }, 60 { XFER_PIO_1, 0x7a, 0x00 }, 61 { XFER_PIO_0, 0x70, 0x00 }, 62 { 0, 0x00, 0x00 } 63}; 64 65#define BUSCLOCK(D) \ 66 ((struct chipset_bus_clock_list_entry *) pci_get_drvdata((D))) 67 68 69/* 70 * TO DO: active tuning and correction of cards without a bios. 71 */ 72static u8 pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table) 73{ 74 for ( ; chipset_table->xfer_speed ; chipset_table++) 75 if (chipset_table->xfer_speed == speed) { 76 return chipset_table->chipset_settings; 77 } 78 return chipset_table->chipset_settings; 79} 80 81static u8 pci_bus_clock_list_ultra (u8 speed, struct chipset_bus_clock_list_entry * chipset_table) 82{ 83 for ( ; chipset_table->xfer_speed ; chipset_table++) 84 if (chipset_table->xfer_speed == speed) { 85 return chipset_table->ultra_settings; 86 } 87 return chipset_table->ultra_settings; 88} 89 90static int aec6210_tune_chipset (ide_drive_t *drive, u8 xferspeed) 91{ 92 ide_hwif_t *hwif = HWIF(drive); 93 struct pci_dev *dev = hwif->pci_dev; 94 u16 d_conf = 0; 95 u8 speed = ide_rate_filter(drive, xferspeed); 96 u8 ultra = 0, ultra_conf = 0; 97 u8 tmp0 = 0, tmp1 = 0, tmp2 = 0; 98 unsigned long flags; 99 100 local_irq_save(flags); 101 /* 0x40|(2*drive->dn): Active, 0x41|(2*drive->dn): Recovery */ 102 pci_read_config_word(dev, 0x40|(2*drive->dn), &d_conf); 103 tmp0 = pci_bus_clock_list(speed, BUSCLOCK(dev)); 104 d_conf = ((tmp0 & 0xf0) << 4) | (tmp0 & 0xf); 105 pci_write_config_word(dev, 0x40|(2*drive->dn), d_conf); 106 107 tmp1 = 0x00; 108 tmp2 = 0x00; 109 pci_read_config_byte(dev, 0x54, &ultra); 110 tmp1 = ((0x00 << (2*drive->dn)) | (ultra & ~(3 << (2*drive->dn)))); 111 ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev)); 112 tmp2 = ((ultra_conf << (2*drive->dn)) | (tmp1 & ~(3 << (2*drive->dn)))); 113 pci_write_config_byte(dev, 0x54, tmp2); 114 local_irq_restore(flags); 115 return(ide_config_drive_speed(drive, speed)); 116} 117 118static int aec6260_tune_chipset (ide_drive_t *drive, u8 xferspeed) 119{ 120 ide_hwif_t *hwif = HWIF(drive); 121 struct pci_dev *dev = hwif->pci_dev; 122 u8 speed = ide_rate_filter(drive, xferspeed); 123 u8 unit = (drive->select.b.unit & 0x01); 124 u8 tmp1 = 0, tmp2 = 0; 125 u8 ultra = 0, drive_conf = 0, ultra_conf = 0; 126 unsigned long flags; 127 128 local_irq_save(flags); 129 /* high 4-bits: Active, low 4-bits: Recovery */ 130 pci_read_config_byte(dev, 0x40|drive->dn, &drive_conf); 131 drive_conf = pci_bus_clock_list(speed, BUSCLOCK(dev)); 132 pci_write_config_byte(dev, 0x40|drive->dn, drive_conf); 133 134 pci_read_config_byte(dev, (0x44|hwif->channel), &ultra); 135 tmp1 = ((0x00 << (4*unit)) | (ultra & ~(7 << (4*unit)))); 136 ultra_conf = pci_bus_clock_list_ultra(speed, BUSCLOCK(dev)); 137 tmp2 = ((ultra_conf << (4*unit)) | (tmp1 & ~(7 << (4*unit)))); 138 pci_write_config_byte(dev, (0x44|hwif->channel), tmp2); 139 local_irq_restore(flags); 140 return(ide_config_drive_speed(drive, speed)); 141} 142 143static int aec62xx_tune_chipset (ide_drive_t *drive, u8 speed) 144{ 145 switch (HWIF(drive)->pci_dev->device) { 146 case PCI_DEVICE_ID_ARTOP_ATP865: 147 case PCI_DEVICE_ID_ARTOP_ATP865R: 148 case PCI_DEVICE_ID_ARTOP_ATP860: 149 case PCI_DEVICE_ID_ARTOP_ATP860R: 150 return ((int) aec6260_tune_chipset(drive, speed)); 151 case PCI_DEVICE_ID_ARTOP_ATP850UF: 152 return ((int) aec6210_tune_chipset(drive, speed)); 153 default: 154 return -1; 155 } 156} 157 158static void aec62xx_tune_drive (ide_drive_t *drive, u8 pio) 159{ 160 pio = ide_get_best_pio_mode(drive, pio, 4, NULL); 161 (void) aec62xx_tune_chipset(drive, pio + XFER_PIO_0); 162} 163 164static int aec62xx_config_drive_xfer_rate (ide_drive_t *drive) 165{ 166 if (ide_tune_dma(drive)) 167 return 0; 168 169 if (ide_use_fast_pio(drive)) 170 aec62xx_tune_drive(drive, 255); 171 172 return -1; 173} 174 175static int aec62xx_irq_timeout (ide_drive_t *drive) 176{ 177 ide_hwif_t *hwif = HWIF(drive); 178 struct pci_dev *dev = hwif->pci_dev; 179 180 switch(dev->device) { 181 case PCI_DEVICE_ID_ARTOP_ATP860: 182 case PCI_DEVICE_ID_ARTOP_ATP860R: 183 case PCI_DEVICE_ID_ARTOP_ATP865: 184 case PCI_DEVICE_ID_ARTOP_ATP865R: 185 printk(" AEC62XX time out "); 186 default: 187 break; 188 } 189 return 0; 190} 191 192static unsigned int __devinit init_chipset_aec62xx(struct pci_dev *dev, const char *name) 193{ 194 int bus_speed = system_bus_clock(); 195 196 if (dev->resource[PCI_ROM_RESOURCE].start) { 197 pci_write_config_dword(dev, PCI_ROM_ADDRESS, dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE); 198 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name, 199 (unsigned long)dev->resource[PCI_ROM_RESOURCE].start); 200 } 201 202 if (bus_speed <= 33) 203 pci_set_drvdata(dev, (void *) aec6xxx_33_base); 204 else 205 pci_set_drvdata(dev, (void *) aec6xxx_34_base); 206 207 /* These are necessary to get AEC6280 Macintosh cards to work */ 208 if ((dev->device == PCI_DEVICE_ID_ARTOP_ATP865) || 209 (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)) { 210 u8 reg49h = 0, reg4ah = 0; 211 /* Clear reset and test bits. */ 212 pci_read_config_byte(dev, 0x49, ®49h); 213 pci_write_config_byte(dev, 0x49, reg49h & ~0x30); 214 /* Enable chip interrupt output. */ 215 pci_read_config_byte(dev, 0x4a, ®4ah); 216 pci_write_config_byte(dev, 0x4a, reg4ah & ~0x01); 217 /* Enable burst mode. */ 218 pci_read_config_byte(dev, 0x4a, ®4ah); 219 pci_write_config_byte(dev, 0x4a, reg4ah | 0x80); 220 } 221 222 return dev->irq; 223} 224 225static void __devinit init_hwif_aec62xx(ide_hwif_t *hwif) 226{ 227 struct pci_dev *dev = hwif->pci_dev; 228 229 hwif->autodma = 0; 230 hwif->tuneproc = &aec62xx_tune_drive; 231 hwif->speedproc = &aec62xx_tune_chipset; 232 233 if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) 234 hwif->serialized = hwif->channel; 235 236 if (hwif->mate) 237 hwif->mate->serialized = hwif->serialized; 238 239 if (!hwif->dma_base) { 240 hwif->drives[0].autotune = 1; 241 hwif->drives[1].autotune = 1; 242 return; 243 } 244 245 hwif->ultra_mask = hwif->cds->udma_mask; 246 247 /* atp865 and atp865r */ 248 if (hwif->ultra_mask == 0x3f) { 249 /* check bit 0x10 of DMA status register */ 250 if (inb(pci_resource_start(dev, 4) + 2) & 0x10) 251 hwif->ultra_mask = 0x7f; /* udma0-6 */ 252 } 253 254 hwif->mwdma_mask = 0x07; 255 256 hwif->ide_dma_check = &aec62xx_config_drive_xfer_rate; 257 hwif->ide_dma_lostirq = &aec62xx_irq_timeout; 258 259 if (!noautodma) 260 hwif->autodma = 1; 261 hwif->drives[0].autodma = hwif->autodma; 262 hwif->drives[1].autodma = hwif->autodma; 263} 264 265static void __devinit init_dma_aec62xx(ide_hwif_t *hwif, unsigned long dmabase) 266{ 267 struct pci_dev *dev = hwif->pci_dev; 268 269 if (dev->device == PCI_DEVICE_ID_ARTOP_ATP850UF) { 270 u8 reg54h = 0; 271 unsigned long flags; 272 273 spin_lock_irqsave(&ide_lock, flags); 274 pci_read_config_byte(dev, 0x54, ®54h); 275 pci_write_config_byte(dev, 0x54, reg54h & ~(hwif->channel ? 0xF0 : 0x0F)); 276 spin_unlock_irqrestore(&ide_lock, flags); 277 } else { 278 u8 ata66 = 0; 279 pci_read_config_byte(hwif->pci_dev, 0x49, &ata66); 280 if (!(hwif->udma_four)) 281 hwif->udma_four = (ata66&(hwif->channel?0x02:0x01))?0:1; 282 } 283 284 ide_setup_dma(hwif, dmabase, 8); 285} 286 287static int __devinit init_setup_aec62xx(struct pci_dev *dev, ide_pci_device_t *d) 288{ 289 return ide_setup_pci_device(dev, d); 290} 291 292static int __devinit init_setup_aec6x80(struct pci_dev *dev, ide_pci_device_t *d) 293{ 294 unsigned long bar4reg = pci_resource_start(dev, 4); 295 296 if (inb(bar4reg+2) & 0x10) { 297 strcpy(d->name, "AEC6880"); 298 if (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R) 299 strcpy(d->name, "AEC6880R"); 300 } else { 301 strcpy(d->name, "AEC6280"); 302 if (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R) 303 strcpy(d->name, "AEC6280R"); 304 } 305 306 return ide_setup_pci_device(dev, d); 307} 308 309static ide_pci_device_t aec62xx_chipsets[] __devinitdata = { 310 { /* 0 */ 311 .name = "AEC6210", 312 .init_setup = init_setup_aec62xx, 313 .init_chipset = init_chipset_aec62xx, 314 .init_hwif = init_hwif_aec62xx, 315 .init_dma = init_dma_aec62xx, 316 .channels = 2, 317 .autodma = AUTODMA, 318 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, 319 .bootable = OFF_BOARD, 320 .udma_mask = 0x07, /* udma0-2 */ 321 },{ /* 1 */ 322 .name = "AEC6260", 323 .init_setup = init_setup_aec62xx, 324 .init_chipset = init_chipset_aec62xx, 325 .init_hwif = init_hwif_aec62xx, 326 .init_dma = init_dma_aec62xx, 327 .channels = 2, 328 .autodma = NOAUTODMA, 329 .bootable = OFF_BOARD, 330 .udma_mask = 0x1f, /* udma0-4 */ 331 },{ /* 2 */ 332 .name = "AEC6260R", 333 .init_setup = init_setup_aec62xx, 334 .init_chipset = init_chipset_aec62xx, 335 .init_hwif = init_hwif_aec62xx, 336 .init_dma = init_dma_aec62xx, 337 .channels = 2, 338 .autodma = AUTODMA, 339 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, 340 .bootable = NEVER_BOARD, 341 .udma_mask = 0x1f, /* udma0-4 */ 342 },{ /* 3 */ 343 .name = "AEC6X80", 344 .init_setup = init_setup_aec6x80, 345 .init_chipset = init_chipset_aec62xx, 346 .init_hwif = init_hwif_aec62xx, 347 .init_dma = init_dma_aec62xx, 348 .channels = 2, 349 .autodma = AUTODMA, 350 .bootable = OFF_BOARD, 351 .udma_mask = 0x3f, /* udma0-5 */ 352 },{ /* 4 */ 353 .name = "AEC6X80R", 354 .init_setup = init_setup_aec6x80, 355 .init_chipset = init_chipset_aec62xx, 356 .init_hwif = init_hwif_aec62xx, 357 .init_dma = init_dma_aec62xx, 358 .channels = 2, 359 .autodma = AUTODMA, 360 .enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}}, 361 .bootable = OFF_BOARD, 362 .udma_mask = 0x3f, /* udma0-5 */ 363 } 364}; 365 366/** 367 * aec62xx_init_one - called when a AEC is found 368 * @dev: the aec62xx device 369 * @id: the matching pci id 370 * 371 * Called when the PCI registration layer (or the IDE initialization) 372 * finds a device matching our IDE device tables. 373 */ 374 375static int __devinit aec62xx_init_one(struct pci_dev *dev, const struct pci_device_id *id) 376{ 377 ide_pci_device_t *d = &aec62xx_chipsets[id->driver_data]; 378 379 return d->init_setup(dev, d); 380} 381 382static struct pci_device_id aec62xx_pci_tbl[] = { 383 { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 384 { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 }, 385 { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP860R, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 }, 386 { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP865, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 }, 387 { PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_ATP865R, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 }, 388 { 0, }, 389}; 390MODULE_DEVICE_TABLE(pci, aec62xx_pci_tbl); 391 392static struct pci_driver driver = { 393 .name = "AEC62xx_IDE", 394 .id_table = aec62xx_pci_tbl, 395 .probe = aec62xx_init_one, 396}; 397 398static int __init aec62xx_ide_init(void) 399{ 400 return ide_pci_register_driver(&driver); 401} 402 403module_init(aec62xx_ide_init); 404 405MODULE_AUTHOR("Andre Hedrick"); 406MODULE_DESCRIPTION("PCI driver module for ARTOP AEC62xx IDE"); 407MODULE_LICENSE("GPL"); 408