1/* 2 * CHRP pci routines. 3 */ 4 5#include <linux/kernel.h> 6#include <linux/pci.h> 7#include <linux/delay.h> 8#include <linux/string.h> 9#include <linux/init.h> 10 11#include <asm/io.h> 12#include <asm/pgtable.h> 13#include <asm/irq.h> 14#include <asm/hydra.h> 15#include <asm/prom.h> 16#include <asm/gg2.h> 17#include <asm/machdep.h> 18#include <asm/sections.h> 19#include <asm/pci-bridge.h> 20#include <asm/grackle.h> 21#include <asm/rtas.h> 22 23#include "chrp.h" 24 25/* LongTrail */ 26void __iomem *gg2_pci_config_base; 27 28/* 29 * The VLSI Golden Gate II has only 512K of PCI configuration space, so we 30 * limit the bus number to 3 bits 31 */ 32 33int gg2_read_config(struct pci_bus *bus, unsigned int devfn, int off, 34 int len, u32 *val) 35{ 36 volatile void __iomem *cfg_data; 37 struct pci_controller *hose = bus->sysdata; 38 39 if (bus->number > 7) 40 return PCIBIOS_DEVICE_NOT_FOUND; 41 /* 42 * Note: the caller has already checked that off is 43 * suitably aligned and that len is 1, 2 or 4. 44 */ 45 cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off); 46 switch (len) { 47 case 1: 48 *val = in_8(cfg_data); 49 break; 50 case 2: 51 *val = in_le16(cfg_data); 52 break; 53 default: 54 *val = in_le32(cfg_data); 55 break; 56 } 57 return PCIBIOS_SUCCESSFUL; 58} 59 60int gg2_write_config(struct pci_bus *bus, unsigned int devfn, int off, 61 int len, u32 val) 62{ 63 volatile void __iomem *cfg_data; 64 struct pci_controller *hose = bus->sysdata; 65 66 if (bus->number > 7) 67 return PCIBIOS_DEVICE_NOT_FOUND; 68 /* 69 * Note: the caller has already checked that off is 70 * suitably aligned and that len is 1, 2 or 4. 71 */ 72 cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off); 73 switch (len) { 74 case 1: 75 out_8(cfg_data, val); 76 break; 77 case 2: 78 out_le16(cfg_data, val); 79 break; 80 default: 81 out_le32(cfg_data, val); 82 break; 83 } 84 return PCIBIOS_SUCCESSFUL; 85} 86 87static struct pci_ops gg2_pci_ops = 88{ 89 gg2_read_config, 90 gg2_write_config 91}; 92 93/* 94 * Access functions for PCI config space using RTAS calls. 95 */ 96int rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset, 97 int len, u32 *val) 98{ 99 struct pci_controller *hose = bus->sysdata; 100 unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8) 101 | (((bus->number - hose->first_busno) & 0xff) << 16) 102 | (hose->index << 24); 103 int ret = -1; 104 int rval; 105 106 rval = rtas_call(rtas_token("read-pci-config"), 2, 2, &ret, addr, len); 107 *val = ret; 108 return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL; 109} 110 111int rtas_write_config(struct pci_bus *bus, unsigned int devfn, int offset, 112 int len, u32 val) 113{ 114 struct pci_controller *hose = bus->sysdata; 115 unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8) 116 | (((bus->number - hose->first_busno) & 0xff) << 16) 117 | (hose->index << 24); 118 int rval; 119 120 rval = rtas_call(rtas_token("write-pci-config"), 3, 1, NULL, 121 addr, len, val); 122 return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL; 123} 124 125static struct pci_ops rtas_pci_ops = 126{ 127 rtas_read_config, 128 rtas_write_config 129}; 130 131volatile struct Hydra __iomem *Hydra = NULL; 132 133int __init 134hydra_init(void) 135{ 136 struct device_node *np; 137 struct resource r; 138 139 np = of_find_node_by_name(NULL, "mac-io"); 140 if (np == NULL || of_address_to_resource(np, 0, &r)) { 141 of_node_put(np); 142 return 0; 143 } 144 Hydra = ioremap(r.start, r.end-r.start); 145 printk("Hydra Mac I/O at %llx\n", (unsigned long long)r.start); 146 printk("Hydra Feature_Control was %x", 147 in_le32(&Hydra->Feature_Control)); 148 out_le32(&Hydra->Feature_Control, (HYDRA_FC_SCC_CELL_EN | 149 HYDRA_FC_SCSI_CELL_EN | 150 HYDRA_FC_SCCA_ENABLE | 151 HYDRA_FC_SCCB_ENABLE | 152 HYDRA_FC_ARB_BYPASS | 153 HYDRA_FC_MPIC_ENABLE | 154 HYDRA_FC_SLOW_SCC_PCLK | 155 HYDRA_FC_MPIC_IS_MASTER)); 156 printk(", now %x\n", in_le32(&Hydra->Feature_Control)); 157 return 1; 158} 159 160#define PRG_CL_RESET_VALID 0x00010000 161 162static void __init 163setup_python(struct pci_controller *hose, struct device_node *dev) 164{ 165 u32 __iomem *reg; 166 u32 val; 167 struct resource r; 168 169 if (of_address_to_resource(dev, 0, &r)) { 170 printk(KERN_ERR "No address for Python PCI controller\n"); 171 return; 172 } 173 174 /* Clear the magic go-slow bit */ 175 reg = ioremap(r.start + 0xf6000, 0x40); 176 BUG_ON(!reg); 177 val = in_be32(®[12]); 178 if (val & PRG_CL_RESET_VALID) { 179 out_be32(®[12], val & ~PRG_CL_RESET_VALID); 180 in_be32(®[12]); 181 } 182 iounmap(reg); 183 184 setup_indirect_pci(hose, r.start + 0xf8000, r.start + 0xf8010); 185} 186 187/* Marvell Discovery II based Pegasos 2 */ 188static void __init setup_peg2(struct pci_controller *hose, struct device_node *dev) 189{ 190 struct device_node *root = of_find_node_by_path("/"); 191 struct device_node *rtas; 192 193 rtas = of_find_node_by_name (root, "rtas"); 194 if (rtas) { 195 hose->ops = &rtas_pci_ops; 196 of_node_put(rtas); 197 } else { 198 printk ("RTAS supporting Pegasos OF not found, please upgrade" 199 " your firmware\n"); 200 } 201 pci_assign_all_buses = 1; 202 /* keep the reference to the root node */ 203} 204 205void __init 206chrp_find_bridges(void) 207{ 208 struct device_node *dev; 209 const int *bus_range; 210 int len, index = -1; 211 struct pci_controller *hose; 212 const unsigned int *dma; 213 const char *model, *machine; 214 int is_longtrail = 0, is_mot = 0, is_pegasos = 0; 215 struct device_node *root = of_find_node_by_path("/"); 216 struct resource r; 217 /* 218 * The PCI host bridge nodes on some machines don't have 219 * properties to adequately identify them, so we have to 220 * look at what sort of machine this is as well. 221 */ 222 machine = of_get_property(root, "model", NULL); 223 if (machine != NULL) { 224 is_longtrail = strncmp(machine, "IBM,LongTrail", 13) == 0; 225 is_mot = strncmp(machine, "MOT", 3) == 0; 226 if (strncmp(machine, "Pegasos2", 8) == 0) 227 is_pegasos = 2; 228 else if (strncmp(machine, "Pegasos", 7) == 0) 229 is_pegasos = 1; 230 } 231 for (dev = root->child; dev != NULL; dev = dev->sibling) { 232 if (dev->type == NULL || strcmp(dev->type, "pci") != 0) 233 continue; 234 ++index; 235 /* The GG2 bridge on the LongTrail doesn't have an address */ 236 if (of_address_to_resource(dev, 0, &r) && !is_longtrail) { 237 printk(KERN_WARNING "Can't use %s: no address\n", 238 dev->full_name); 239 continue; 240 } 241 bus_range = of_get_property(dev, "bus-range", &len); 242 if (bus_range == NULL || len < 2 * sizeof(int)) { 243 printk(KERN_WARNING "Can't get bus-range for %s\n", 244 dev->full_name); 245 continue; 246 } 247 if (bus_range[1] == bus_range[0]) 248 printk(KERN_INFO "PCI bus %d", bus_range[0]); 249 else 250 printk(KERN_INFO "PCI buses %d..%d", 251 bus_range[0], bus_range[1]); 252 printk(" controlled by %s", dev->full_name); 253 if (!is_longtrail) 254 printk(" at %llx", (unsigned long long)r.start); 255 printk("\n"); 256 257 hose = pcibios_alloc_controller(); 258 if (!hose) { 259 printk("Can't allocate PCI controller structure for %s\n", 260 dev->full_name); 261 continue; 262 } 263 hose->arch_data = dev; 264 hose->first_busno = bus_range[0]; 265 hose->last_busno = bus_range[1]; 266 267 model = of_get_property(dev, "model", NULL); 268 if (model == NULL) 269 model = "<none>"; 270 if (of_device_is_compatible(dev, "IBM,python")) { 271 setup_python(hose, dev); 272 } else if (is_mot 273 || strncmp(model, "Motorola, Grackle", 17) == 0) { 274 setup_grackle(hose); 275 } else if (is_longtrail) { 276 void __iomem *p = ioremap(GG2_PCI_CONFIG_BASE, 0x80000); 277 hose->ops = &gg2_pci_ops; 278 hose->cfg_data = p; 279 gg2_pci_config_base = p; 280 } else if (is_pegasos == 1) { 281 setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc); 282 } else if (is_pegasos == 2) { 283 setup_peg2(hose, dev); 284 } else if (!strncmp(model, "IBM,CPC710", 10)) { 285 setup_indirect_pci(hose, 286 r.start + 0x000f8000, 287 r.start + 0x000f8010); 288 if (index == 0) { 289 dma = of_get_property(dev, "system-dma-base", 290 &len); 291 if (dma && len >= sizeof(*dma)) { 292 dma = (unsigned int *) 293 (((unsigned long)dma) + 294 len - sizeof(*dma)); 295 pci_dram_offset = *dma; 296 } 297 } 298 } else { 299 printk("No methods for %s (model %s), using RTAS\n", 300 dev->full_name, model); 301 hose->ops = &rtas_pci_ops; 302 } 303 304 pci_process_bridge_OF_ranges(hose, dev, index == 0); 305 306 /* check the first bridge for a property that we can 307 use to set pci_dram_offset */ 308 dma = of_get_property(dev, "ibm,dma-ranges", &len); 309 if (index == 0 && dma != NULL && len >= 6 * sizeof(*dma)) { 310 pci_dram_offset = dma[2] - dma[3]; 311 printk("pci_dram_offset = %lx\n", pci_dram_offset); 312 } 313 } 314 of_node_put(root); 315} 316 317/* SL82C105 IDE Control/Status Register */ 318#define SL82C105_IDECSR 0x40 319 320/* Fixup for Winbond ATA quirk, required for briq */ 321void chrp_pci_fixup_winbond_ata(struct pci_dev *sl82c105) 322{ 323 u8 progif; 324 325 /* If non-briq machines need that fixup too, please speak up */ 326 if (!machine_is(chrp) || _chrp_type != _CHRP_briq) 327 return; 328 329 if ((sl82c105->class & 5) != 5) { 330 printk("W83C553: Switching SL82C105 IDE to PCI native mode\n"); 331 /* Enable SL82C105 PCI native IDE mode */ 332 pci_read_config_byte(sl82c105, PCI_CLASS_PROG, &progif); 333 pci_write_config_byte(sl82c105, PCI_CLASS_PROG, progif | 0x05); 334 sl82c105->class |= 0x05; 335 /* Disable SL82C105 second port */ 336 pci_write_config_word(sl82c105, SL82C105_IDECSR, 0x0003); 337 } 338} 339DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105, 340 chrp_pci_fixup_winbond_ata); 341