1/*
2 * Cobalt Qube/Raq PCI support
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License.  See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1995, 1996, 1997, 2002, 2003 by Ralf Baechle
9 * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv)
10 */
11#include <linux/types.h>
12#include <linux/pci.h>
13#include <linux/kernel.h>
14#include <linux/init.h>
15
16#include <asm/pci.h>
17#include <asm/io.h>
18#include <asm/gt64120.h>
19
20#include <cobalt.h>
21
22static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
23{
24	if (dev->devfn == PCI_DEVFN(0, 0) &&
25		(dev->class >> 8) == PCI_CLASS_MEMORY_OTHER) {
26
27		dev->class = (PCI_CLASS_BRIDGE_HOST << 8) | (dev->class & 0xff);
28
29		printk(KERN_INFO "Galileo: fixed bridge class\n");
30	}
31}
32
33DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
34	 qube_raq_galileo_early_fixup);
35
36static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
37{
38	unsigned short cfgword;
39	unsigned char lt;
40
41	/* Enable Bus Mastering and fast back to back. */
42	pci_read_config_word(dev, PCI_COMMAND, &cfgword);
43	cfgword |= (PCI_COMMAND_FAST_BACK | PCI_COMMAND_MASTER);
44	pci_write_config_word(dev, PCI_COMMAND, cfgword);
45
46	/* Enable both ide interfaces. ROM only enables primary one.  */
47	pci_write_config_byte(dev, 0x40, 0xb);
48
49	/* Set latency timer to reasonable value. */
50	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lt);
51	if (lt < 64)
52		pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
53	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
54}
55
56DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
57	 qube_raq_via_bmIDE_fixup);
58
59static void qube_raq_galileo_fixup(struct pci_dev *dev)
60{
61	unsigned short galileo_id;
62
63	if (dev->devfn != PCI_DEVFN(0, 0))
64		return;
65
66	/* Fix PCI latency-timer and cache-line-size values in Galileo
67	 * host bridge.
68	 */
69	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
70	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
71
72	/*
73	 * The code described by the comment below has been removed
74	 * as it causes bus mastering by the Ethernet controllers
75	 * to break under any kind of network load. We always set
76	 * the retry timeouts to their maximum.
77	 *
78	 * --x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--
79	 *
80	 * On all machines prior to Q2, we had the STOP line disconnected
81	 * from Galileo to VIA on PCI.  The new Galileo does not function
82	 * correctly unless we have it connected.
83	 *
84	 * Therefore we must set the disconnect/retry cycle values to
85	 * something sensible when using the new Galileo.
86	 */
87	pci_read_config_word(dev, PCI_REVISION_ID, &galileo_id);
88	galileo_id &= 0xff;	/* mask off class info */
89
90 	printk(KERN_INFO "Galileo: revision %u\n", galileo_id);
91
92	{
93		signed int timeo;
94		timeo = GT_READ(GT_PCI0_TOR_OFS);
95		/* Old Galileo, assumes PCI STOP line to VIA is disconnected. */
96		GT_WRITE(GT_PCI0_TOR_OFS,
97			(0xff << 16) |		/* retry count */
98			(0xff << 8) |		/* timeout 1   */
99			0xff);			/* timeout 0   */
100
101		/* enable PCI retry exceeded interrupt */
102		GT_WRITE(GT_INTRMASK_OFS, GT_INTR_RETRYCTR0_MSK | GT_READ(GT_INTRMASK_OFS));
103	}
104}
105
106DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
107	 qube_raq_galileo_fixup);
108
109int cobalt_board_id;
110
111static void qube_raq_via_board_id_fixup(struct pci_dev *dev)
112{
113	u8 id;
114	int retval;
115
116	retval = pci_read_config_byte(dev, VIA_COBALT_BRD_ID_REG, &id);
117	if (retval) {
118		panic("Cannot read board ID");
119		return;
120	}
121
122	cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(id);
123
124	printk(KERN_INFO "Cobalt board ID: %d\n", cobalt_board_id);
125}
126
127DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0,
128	 qube_raq_via_board_id_fixup);
129
130static char irq_tab_qube1[] __initdata = {
131  [COBALT_PCICONF_CPU]     = 0,
132  [COBALT_PCICONF_ETH0]    = COBALT_QUBE1_ETH0_IRQ,
133  [COBALT_PCICONF_RAQSCSI] = COBALT_SCSI_IRQ,
134  [COBALT_PCICONF_VIA]     = 0,
135  [COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ,
136  [COBALT_PCICONF_ETH1]    = 0
137};
138
139static char irq_tab_cobalt[] __initdata = {
140  [COBALT_PCICONF_CPU]     = 0,
141  [COBALT_PCICONF_ETH0]    = COBALT_ETH0_IRQ,
142  [COBALT_PCICONF_RAQSCSI] = COBALT_SCSI_IRQ,
143  [COBALT_PCICONF_VIA]     = 0,
144  [COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ,
145  [COBALT_PCICONF_ETH1]    = COBALT_ETH1_IRQ
146};
147
148static char irq_tab_raq2[] __initdata = {
149  [COBALT_PCICONF_CPU]     = 0,
150  [COBALT_PCICONF_ETH0]    = COBALT_ETH0_IRQ,
151  [COBALT_PCICONF_RAQSCSI] = COBALT_RAQ_SCSI_IRQ,
152  [COBALT_PCICONF_VIA]     = 0,
153  [COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ,
154  [COBALT_PCICONF_ETH1]    = COBALT_ETH1_IRQ
155};
156
157int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
158{
159	if (cobalt_board_id < COBALT_BRD_ID_QUBE2)
160		return irq_tab_qube1[slot];
161
162	if (cobalt_board_id == COBALT_BRD_ID_RAQ2)
163		return irq_tab_raq2[slot];
164
165	return irq_tab_cobalt[slot];
166}
167
168/* Do platform specific device initialization at pci_enable_device() time */
169int pcibios_plat_dev_init(struct pci_dev *dev)
170{
171	return 0;
172}
173