1/*
2 * BRIEF MODULE DESCRIPTION
3 *	Alchemy/AMD Au1x00 pci support.
4 *
5 * Copyright 2001,2002,2003 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc.
7 *         	ppopov@mvista.com or source@mvista.com
8 *
9 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
10 *
11 *  Support for all devices (greater than 16) added by David Gathright.
12 *
13 *  This program is free software; you can redistribute  it and/or modify it
14 *  under  the terms of  the GNU General  Public License as published by the
15 *  Free Software Foundation;  either version 2 of the  License, or (at your
16 *  option) any later version.
17 *
18 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
19 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
20 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
21 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
22 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
24 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
25 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
26 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 *  You should have received a copy of the  GNU General Public License along
30 *  with this program; if not, write  to the Free Software Foundation, Inc.,
31 *  675 Mass Ave, Cambridge, MA 02139, USA.
32 */
33#include <linux/types.h>
34#include <linux/pci.h>
35#include <linux/kernel.h>
36#include <linux/init.h>
37
38#include <asm/mach-au1x00/au1000.h>
39
40/* TBD */
41static struct resource pci_io_resource = {
42	.start	= (resource_size_t)PCI_IO_START,
43	.end	= (resource_size_t)PCI_IO_END,
44	.name	= "PCI IO space",
45	.flags	= IORESOURCE_IO
46};
47
48static struct resource pci_mem_resource = {
49	.start	= (resource_size_t)PCI_MEM_START,
50	.end	= (resource_size_t)PCI_MEM_END,
51	.name	= "PCI memory space",
52	.flags	= IORESOURCE_MEM
53};
54
55extern struct pci_ops au1x_pci_ops;
56
57static struct pci_controller au1x_controller = {
58	.pci_ops	= &au1x_pci_ops,
59	.io_resource	= &pci_io_resource,
60	.mem_resource	= &pci_mem_resource,
61};
62
63#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
64static unsigned long virt_io_addr;
65#endif
66
67static int __init au1x_pci_setup(void)
68{
69#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
70	virt_io_addr = (unsigned long)ioremap(Au1500_PCI_IO_START,
71			Au1500_PCI_IO_END - Au1500_PCI_IO_START + 1);
72
73	if (!virt_io_addr) {
74		printk(KERN_ERR "Unable to ioremap pci space\n");
75		return 1;
76	}
77
78#ifdef CONFIG_DMA_NONCOHERENT
79	{
80		/*
81		 *  Set the NC bit in controller for Au1500 pre-AC silicon
82		 */
83		u32 prid = read_c0_prid();
84
85		if ((prid & 0xFF000000) == 0x01000000 && prid < 0x01030202) {
86		       au_writel((1 << 16) | au_readl(Au1500_PCI_CFG),
87			         Au1500_PCI_CFG);
88		       printk("Non-coherent PCI accesses enabled\n");
89		}
90	}
91#endif
92
93	set_io_port_base(virt_io_addr);
94#endif
95
96	register_pci_controller(&au1x_controller);
97	return 0;
98}
99
100arch_initcall(au1x_pci_setup);
101