1//Original:/proj/frio/dv/testcases/seq/se_misaligned_fetch/se_misaligned_fetch.dsp 2// Description: attempt to fetch code from misaligned address 3# mach: bfin 4# sim: --environment operating 5 6#include "test.h" 7.include "testutils.inc" 8start 9 10// 11// Constants and Defines 12// 13 14include(gen_int.inc) 15include(selfcheck.inc) 16include(std.inc) 17include(symtable.inc) 18 19#ifndef STACKSIZE 20#define STACKSIZE 0x10 21#endif 22#ifndef EVT 23#define EVT 0xFFE02000 24#endif 25#ifndef EVT15 26#define EVT15 0xFFE0203C 27#endif 28#ifndef EVT_OVERRIDE 29#define EVT_OVERRIDE 0xFFE02100 30#endif 31#ifndef ITABLE 32#define ITABLE 0xF0000000 33#endif 34 35GEN_INT_INIT(ITABLE) // set location for interrupt table 36 37// 38// Reset/Bootstrap Code 39// (Here we should set the processor operating modes, initialize registers, 40// etc.) 41// 42 43BOOT: 44INIT_R_REGS(0); // initialize general purpose regs 45 46INIT_P_REGS(0); // initialize the pointers 47 48INIT_I_REGS(0); // initialize the dsp address regs 49INIT_M_REGS(0); 50INIT_L_REGS(0); 51INIT_B_REGS(0); 52 53LD32_LABEL(sp, KSTACK); // setup the stack pointer 54FP = SP; // and frame pointer 55 56LD32(p0, EVT); // Setup Event Vectors and Handlers 57 58CLI R0; // hold off nonmaskables while writing EVTs 59 60LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0) 61 62 [ P0 ++ ] = R0; 63 64LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1) 65 [ P0 ++ ] = R0; 66 67LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2) 68 [ P0 ++ ] = R0; 69 70LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3) 71 [ P0 ++ ] = R0; 72 73 [ P0 ++ ] = R0; // IVT4 not used 74 75LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5) 76 [ P0 ++ ] = R0; 77 78LD32_LABEL(r0, THANDLE); // Timer Handler (Int6) 79 [ P0 ++ ] = R0; 80 81LD32_LABEL(r0, I7HANDLE); // IVG7 Handler 82 [ P0 ++ ] = R0; 83 84LD32_LABEL(r0, I8HANDLE); // IVG8 Handler 85 [ P0 ++ ] = R0; 86 87LD32_LABEL(r0, I9HANDLE); // IVG9 Handler 88 [ P0 ++ ] = R0; 89 90LD32_LABEL(r0, I10HANDLE);// IVG10 Handler 91 [ P0 ++ ] = R0; 92 93LD32_LABEL(r0, I11HANDLE);// IVG11 Handler 94 [ P0 ++ ] = R0; 95 96LD32_LABEL(r0, I12HANDLE);// IVG12 Handler 97 [ P0 ++ ] = R0; 98 99LD32_LABEL(r0, I13HANDLE);// IVG13 Handler 100 [ P0 ++ ] = R0; 101 102LD32_LABEL(r0, I14HANDLE);// IVG14 Handler 103 [ P0 ++ ] = R0; 104 105LD32_LABEL(r0, I15HANDLE);// IVG15 Handler 106 [ P0 ++ ] = R0; 107 108LD32(p0, EVT_OVERRIDE); 109 R0 = 0; 110 [ P0 ++ ] = R0; 111 R0 = -1; // Change this to mask interrupts (*) 112 [ P0 ] = R0; // IMASK 113CSYNC; // wait for MMR writes 114STI R0; // reenable events 115 116DUMMY: 117 118 R0 = 0 (Z); 119 120LT0 = r0; // set loop counters to something deterministic 121LB0 = r0; 122LC0 = r0; 123LT1 = r0; 124LB1 = r0; 125LC1 = r0; 126 127ASTAT = r0; // reset other internal regs 128 129// The following code sets up the test for running in USER mode 130 131LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a 132 // ReturnFromInterrupt (RTI) 133RETI = r0; // We need to load the return address 134 135// Comment the following line for a USER Mode test 136 137// JUMP STARTSUP; // jump to code start for SUPERVISOR mode 138 139RTI; 140 141STARTSUP: 142LD32_LABEL(p1, BEGIN); 143 144LD32(p0, EVT15); 145 [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start 146 147RAISE 15; // after we RTI, INT 15 should be taken 148 149RTI; 150 151// 152// The Main Program 153// 154 155STARTUSER: 156LD32_LABEL(sp, USTACK); // setup the stack pointer 157FP = SP; // set frame pointer 158JUMP BEGIN; 159 160//********************************************************************* 161 162BEGIN: 163 164 // COMMENT the following line for USER MODE tests 165// [--sp] = RETI; // enable interrupts in supervisor mode 166 167 // **** YOUR CODE GOES HERE **** 168CHECK_INIT_DEF(p0); //CHECK_INIT(p0, 0xFF7FFFFC); 169 170LD32_LABEL(p1, TARGET); 171 172 P1 += 1; // cause access to be misaligned 173 174JUMP ( P1 ); // should cause misaligned 175 176 R1 += 1; 177 R1 += 1; 178 R1 += 1; 179 R1 += 1; 180 R1 += 1; 181 R1 += 1; 182 R1 += 1; 183 R1 += 1; 184 185TARGET: 186NOP; 187NOP; 188NOP; 189 190 // PUT YOUR TEST HERE! 191 192 193END: 194CHECKREG(r5, 0xFFFFFFFF); // handler sets this if reached 195 196dbg_pass; // End the test 197 198//********************************************************************* 199 200// 201// Handlers for Events 202// 203 204EHANDLE: // Emulation Handler 0 205RTE; 206 207RHANDLE: // Reset Handler 1 208RTI; 209 210NHANDLE: // NMI Handler 2 211RTN; 212 213XHANDLE: // Exception Handler 3 214 [ -- SP ] = ASTAT; // save what we damage 215 [ -- SP ] = ( R7:6 ); 216 R7 = SEQSTAT; 217 R7 <<= 26; 218 R7 >>= 26; // only want EXCAUSE 219 R6 = 0x2A; // EXCAUSE 0x2A means I-Fetch Misaligned Access 220CC = r7 == r6; 221IF CC JUMP IFETCHMISALIGNED; // If EXCAUSE != 0x2A then leave 222 223dbg_pass; // if the EXCAUSE is wrong the test will infinite loop 224 225IFETCHMISALIGNED: 226 R7 = P1; // Fix up return address 227BITCLR(r7, 0); // Strip off errant LSB 228RETX = r7; // and put back in RETX 229 230 R5 = -1; // set flag to indicate success 231 232OUT: 233 ( R7:6 ) = [ SP ++ ]; 234ASTAT = [sp++]; 235RTX; 236 237HWHANDLE: // HW Error Handler 5 238RTI; 239 240THANDLE: // Timer Handler 6 241RTI; 242 243I7HANDLE: // IVG 7 Handler 244RTI; 245 246I8HANDLE: // IVG 8 Handler 247RTI; 248 249I9HANDLE: // IVG 9 Handler 250RTI; 251 252I10HANDLE: // IVG 10 Handler 253RTI; 254 255I11HANDLE: // IVG 11 Handler 256RTI; 257 258I12HANDLE: // IVG 12 Handler 259RTI; 260 261I13HANDLE: // IVG 13 Handler 262RTI; 263 264I14HANDLE: // IVG 14 Handler 265RTI; 266 267I15HANDLE: // IVG 15 Handler 268RTI; 269 270NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug 271 272// 273// Data Segment 274// 275 276.data 277DATA: 278 .space (0x10); 279 280// Stack Segments (Both Kernel and User) 281 282 .space (STACKSIZE); 283KSTACK: 284 285 .space (STACKSIZE); 286USTACK: 287