1/* $NetBSD: pci_machdep.c,v 1.54 2012/02/15 16:30:29 tsutsui Exp $ */ 2 3/*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 35 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Charles M. Hannum. 48 * 4. The name of the author may not be used to endorse or promote products 49 * derived from this software without specific prior written permission. 50 * 51 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 52 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 53 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 54 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 55 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 56 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 60 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 61 */ 62 63/* 64 * Machine-specific functions for PCI autoconfiguration. 65 * 66 * On PCs, there are two methods of generating PCI configuration cycles. 67 * We try to detect the appropriate mechanism for this machine and set 68 * up a few function pointers to access the correct method directly. 69 * 70 * The configuration method can be hard-coded in the config file by 71 * using `options PCI_CONF_MODE=N', where `N' is the configuration mode 72 * as defined section 3.6.4.1, `Generating Configuration Cycles'. 73 */ 74 75#include <sys/cdefs.h> 76__KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.54 2012/02/15 16:30:29 tsutsui Exp $"); 77 78#include <sys/types.h> 79#include <sys/param.h> 80#include <sys/time.h> 81#include <sys/systm.h> 82#include <sys/errno.h> 83#include <sys/device.h> 84#include <sys/bus.h> 85#include <sys/cpu.h> 86#include <sys/kmem.h> 87 88#include <uvm/uvm_extern.h> 89 90#include <machine/bus_private.h> 91 92#include <machine/pio.h> 93#include <machine/lock.h> 94 95#include <dev/isa/isareg.h> 96#include <dev/isa/isavar.h> 97#include <dev/pci/pcivar.h> 98#include <dev/pci/pcireg.h> 99#include <dev/pci/pccbbreg.h> 100#include <dev/pci/pcidevs.h> 101#include <dev/pci/genfb_pcivar.h> 102 103#include <dev/wsfb/genfbvar.h> 104#include <arch/x86/include/genfb_machdep.h> 105#include <dev/ic/vgareg.h> 106 107#include "acpica.h" 108#include "genfb.h" 109#include "isa.h" 110#include "opt_acpi.h" 111#include "opt_ddb.h" 112#include "opt_mpbios.h" 113#include "opt_vga.h" 114#include "pci.h" 115#include "wsdisplay.h" 116 117#ifdef DDB 118#include <machine/db_machdep.h> 119#include <ddb/db_sym.h> 120#include <ddb/db_extern.h> 121#endif 122 123#ifdef VGA_POST 124#include <x86/vga_post.h> 125#endif 126 127#include <machine/autoconf.h> 128#include <machine/bootinfo.h> 129 130#ifdef MPBIOS 131#include <machine/mpbiosvar.h> 132#endif 133 134#if NACPICA > 0 135#include <machine/mpacpi.h> 136#endif 137 138#include <machine/mpconfig.h> 139 140#include "opt_pci_conf_mode.h" 141 142#ifdef PCI_CONF_MODE 143#if (PCI_CONF_MODE == 1) || (PCI_CONF_MODE == 2) 144static int pci_mode = PCI_CONF_MODE; 145#else 146#error Invalid PCI configuration mode. 147#endif 148#else 149static int pci_mode = -1; 150#endif 151 152struct pci_conf_lock { 153 uint32_t cl_cpuno; /* 0: unlocked 154 * 1 + n: locked by CPU n (0 <= n) 155 */ 156 uint32_t cl_sel; /* the address that's being read. */ 157}; 158 159static void pci_conf_unlock(struct pci_conf_lock *); 160static uint32_t pci_conf_selector(pcitag_t, int); 161static unsigned int pci_conf_port(pcitag_t, int); 162static void pci_conf_select(uint32_t); 163static void pci_conf_lock(struct pci_conf_lock *, uint32_t); 164static void pci_bridge_hook(pci_chipset_tag_t, pcitag_t, void *); 165struct pci_bridge_hook_arg { 166 void (*func)(pci_chipset_tag_t, pcitag_t, void *); 167 void *arg; 168}; 169 170#define PCI_MODE1_ENABLE 0x80000000UL 171#define PCI_MODE1_ADDRESS_REG 0x0cf8 172#define PCI_MODE1_DATA_REG 0x0cfc 173 174#define PCI_MODE2_ENABLE_REG 0x0cf8 175#define PCI_MODE2_FORWARD_REG 0x0cfa 176 177#define _m1tag(b, d, f) \ 178 (PCI_MODE1_ENABLE | ((b) << 16) | ((d) << 11) | ((f) << 8)) 179#define _qe(bus, dev, fcn, vend, prod) \ 180 {_m1tag(bus, dev, fcn), PCI_ID_CODE(vend, prod)} 181struct { 182 uint32_t tag; 183 pcireg_t id; 184} pcim1_quirk_tbl[] = { 185 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX1), 186 /* XXX Triflex2 not tested */ 187 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX2), 188 _qe(0, 0, 0, PCI_VENDOR_COMPAQ, PCI_PRODUCT_COMPAQ_TRIFLEX4), 189 /* Triton needed for Connectix Virtual PC */ 190 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82437FX), 191 /* Connectix Virtual PC 5 has a 440BX */ 192 _qe(0, 0, 0, PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82443BX_NOAGP), 193 /* Parallels Desktop for Mac */ 194 _qe(0, 2, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_VIDEO), 195 _qe(0, 3, 0, PCI_VENDOR_PARALLELS, PCI_PRODUCT_PARALLELS_TOOLS), 196 /* SIS 740 */ 197 _qe(0, 0, 0, PCI_VENDOR_SIS, PCI_PRODUCT_SIS_740), 198 /* SIS 741 */ 199 _qe(0, 0, 0, PCI_VENDOR_SIS, PCI_PRODUCT_SIS_741), 200 /* VIA Technologies VX900 */ 201 _qe(0, 0, 0, PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VX900_HB), 202 {0, 0xffffffff} /* patchable */ 203}; 204#undef _m1tag 205#undef _id 206#undef _qe 207 208/* 209 * PCI doesn't have any special needs; just use the generic versions 210 * of these functions. 211 */ 212struct x86_bus_dma_tag pci_bus_dma_tag = { 213 ._tag_needs_free = 0, 214#if defined(_LP64) || defined(PAE) 215 ._bounce_thresh = PCI32_DMA_BOUNCE_THRESHOLD, 216 ._bounce_alloc_lo = ISA_DMA_BOUNCE_THRESHOLD, 217 ._bounce_alloc_hi = PCI32_DMA_BOUNCE_THRESHOLD, 218#else 219 ._bounce_thresh = 0, 220 ._bounce_alloc_lo = 0, 221 ._bounce_alloc_hi = 0, 222#endif 223 ._may_bounce = NULL, 224}; 225 226#ifdef _LP64 227struct x86_bus_dma_tag pci_bus_dma64_tag = { 228 ._tag_needs_free = 0, 229 ._bounce_thresh = 0, 230 ._bounce_alloc_lo = 0, 231 ._bounce_alloc_hi = 0, 232 ._may_bounce = NULL, 233}; 234#endif 235 236static struct pci_conf_lock cl0 = { 237 .cl_cpuno = 0UL 238 , .cl_sel = 0UL 239}; 240 241static struct pci_conf_lock * const cl = &cl0; 242 243#if NGENFB > 0 && NACPICA > 0 && defined(VGA_POST) 244extern int acpi_md_vbios_reset; 245extern int acpi_md_vesa_modenum; 246#endif 247 248static struct genfb_colormap_callback gfb_cb; 249static struct genfb_pmf_callback pmf_cb; 250static struct genfb_mode_callback mode_cb; 251#ifdef VGA_POST 252static struct vga_post *vga_posth = NULL; 253#endif 254 255static void 256pci_conf_lock(struct pci_conf_lock *ocl, uint32_t sel) 257{ 258 uint32_t cpuno; 259 260 KASSERT(sel != 0); 261 262 kpreempt_disable(); 263 cpuno = cpu_number() + 1; 264 /* If the kernel enters pci_conf_lock() through an interrupt 265 * handler, then the CPU may already hold the lock. 266 * 267 * If the CPU does not already hold the lock, spin until 268 * we can acquire it. 269 */ 270 if (cpuno == cl->cl_cpuno) { 271 ocl->cl_cpuno = cpuno; 272 } else { 273 u_int spins; 274 275 ocl->cl_cpuno = 0; 276 277 spins = SPINLOCK_BACKOFF_MIN; 278 while (atomic_cas_32(&cl->cl_cpuno, 0, cpuno) != 0) { 279 SPINLOCK_BACKOFF(spins); 280#ifdef LOCKDEBUG 281 if (SPINLOCK_SPINOUT(spins)) { 282 panic("%s: cpu %" PRId32 283 " spun out waiting for cpu %" PRId32, 284 __func__, cpuno, cl->cl_cpuno); 285 } 286#endif /* LOCKDEBUG */ 287 } 288 } 289 290 /* Only one CPU can be here, so an interlocked atomic_swap(3) 291 * is not necessary. 292 * 293 * Evaluating atomic_cas_32_ni()'s argument, cl->cl_sel, 294 * and applying atomic_cas_32_ni() is not an atomic operation, 295 * however, any interrupt that, in the middle of the 296 * operation, modifies cl->cl_sel, will also restore 297 * cl->cl_sel. So cl->cl_sel will have the same value when 298 * we apply atomic_cas_32_ni() as when we evaluated it, 299 * before. 300 */ 301 ocl->cl_sel = atomic_cas_32_ni(&cl->cl_sel, cl->cl_sel, sel); 302 pci_conf_select(sel); 303} 304 305static void 306pci_conf_unlock(struct pci_conf_lock *ocl) 307{ 308 uint32_t sel; 309 310 sel = atomic_cas_32_ni(&cl->cl_sel, cl->cl_sel, ocl->cl_sel); 311 pci_conf_select(ocl->cl_sel); 312 if (ocl->cl_cpuno != cl->cl_cpuno) 313 atomic_cas_32(&cl->cl_cpuno, cl->cl_cpuno, ocl->cl_cpuno); 314 kpreempt_enable(); 315} 316 317static uint32_t 318pci_conf_selector(pcitag_t tag, int reg) 319{ 320 static const pcitag_t mode2_mask = { 321 .mode2 = { 322 .enable = 0xff 323 , .forward = 0xff 324 } 325 }; 326 327 switch (pci_mode) { 328 case 1: 329 return tag.mode1 | reg; 330 case 2: 331 return tag.mode1 & mode2_mask.mode1; 332 default: 333 panic("%s: mode not configured", __func__); 334 } 335} 336 337static unsigned int 338pci_conf_port(pcitag_t tag, int reg) 339{ 340 switch (pci_mode) { 341 case 1: 342 return PCI_MODE1_DATA_REG; 343 case 2: 344 return tag.mode2.port | reg; 345 default: 346 panic("%s: mode not configured", __func__); 347 } 348} 349 350static void 351pci_conf_select(uint32_t sel) 352{ 353 pcitag_t tag; 354 355 switch (pci_mode) { 356 case 1: 357 outl(PCI_MODE1_ADDRESS_REG, sel); 358 return; 359 case 2: 360 tag.mode1 = sel; 361 outb(PCI_MODE2_ENABLE_REG, tag.mode2.enable); 362 if (tag.mode2.enable != 0) 363 outb(PCI_MODE2_FORWARD_REG, tag.mode2.forward); 364 return; 365 default: 366 panic("%s: mode not configured", __func__); 367 } 368} 369 370void 371pci_attach_hook(device_t parent, device_t self, struct pcibus_attach_args *pba) 372{ 373 374 if (pba->pba_bus == 0) 375 aprint_normal(": configuration mode %d", pci_mode); 376#ifdef MPBIOS 377 mpbios_pci_attach_hook(parent, self, pba); 378#endif 379#if NACPICA > 0 380 mpacpi_pci_attach_hook(parent, self, pba); 381#endif 382} 383 384int 385pci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 386{ 387 /* 388 * Bus number is irrelevant. If Configuration Mechanism 2 is in 389 * use, can only have devices 0-15 on any bus. If Configuration 390 * Mechanism 1 is in use, can have devices 0-32 (i.e. the `normal' 391 * range). 392 */ 393 if (pci_mode == 2) 394 return (16); 395 else 396 return (32); 397} 398 399pcitag_t 400pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function) 401{ 402 pci_chipset_tag_t ipc; 403 pcitag_t tag; 404 405 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 406 if ((ipc->pc_present & PCI_OVERRIDE_MAKE_TAG) == 0) 407 continue; 408 return (*ipc->pc_ov->ov_make_tag)(ipc->pc_ctx, 409 pc, bus, device, function); 410 } 411 412 switch (pci_mode) { 413 case 1: 414 if (bus >= 256 || device >= 32 || function >= 8) 415 panic("%s: bad request", __func__); 416 417 tag.mode1 = PCI_MODE1_ENABLE | 418 (bus << 16) | (device << 11) | (function << 8); 419 return tag; 420 case 2: 421 if (bus >= 256 || device >= 16 || function >= 8) 422 panic("%s: bad request", __func__); 423 424 tag.mode2.port = 0xc000 | (device << 8); 425 tag.mode2.enable = 0xf0 | (function << 1); 426 tag.mode2.forward = bus; 427 return tag; 428 default: 429 panic("%s: mode not configured", __func__); 430 } 431} 432 433void 434pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, 435 int *bp, int *dp, int *fp) 436{ 437 pci_chipset_tag_t ipc; 438 439 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 440 if ((ipc->pc_present & PCI_OVERRIDE_DECOMPOSE_TAG) == 0) 441 continue; 442 (*ipc->pc_ov->ov_decompose_tag)(ipc->pc_ctx, 443 pc, tag, bp, dp, fp); 444 return; 445 } 446 447 switch (pci_mode) { 448 case 1: 449 if (bp != NULL) 450 *bp = (tag.mode1 >> 16) & 0xff; 451 if (dp != NULL) 452 *dp = (tag.mode1 >> 11) & 0x1f; 453 if (fp != NULL) 454 *fp = (tag.mode1 >> 8) & 0x7; 455 return; 456 case 2: 457 if (bp != NULL) 458 *bp = tag.mode2.forward & 0xff; 459 if (dp != NULL) 460 *dp = (tag.mode2.port >> 8) & 0xf; 461 if (fp != NULL) 462 *fp = (tag.mode2.enable >> 1) & 0x7; 463 return; 464 default: 465 panic("%s: mode not configured", __func__); 466 } 467} 468 469pcireg_t 470pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 471{ 472 pci_chipset_tag_t ipc; 473 pcireg_t data; 474 struct pci_conf_lock ocl; 475 476 KASSERT((reg & 0x3) == 0); 477 478 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 479 if ((ipc->pc_present & PCI_OVERRIDE_CONF_READ) == 0) 480 continue; 481 return (*ipc->pc_ov->ov_conf_read)(ipc->pc_ctx, pc, tag, reg); 482 } 483 484 pci_conf_lock(&ocl, pci_conf_selector(tag, reg)); 485 data = inl(pci_conf_port(tag, reg)); 486 pci_conf_unlock(&ocl); 487 return data; 488} 489 490void 491pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data) 492{ 493 pci_chipset_tag_t ipc; 494 struct pci_conf_lock ocl; 495 496 KASSERT((reg & 0x3) == 0); 497 498 for (ipc = pc; ipc != NULL; ipc = ipc->pc_super) { 499 if ((ipc->pc_present & PCI_OVERRIDE_CONF_WRITE) == 0) 500 continue; 501 (*ipc->pc_ov->ov_conf_write)(ipc->pc_ctx, pc, tag, reg, 502 data); 503 return; 504 } 505 506 pci_conf_lock(&ocl, pci_conf_selector(tag, reg)); 507 outl(pci_conf_port(tag, reg), data); 508 pci_conf_unlock(&ocl); 509} 510 511void 512pci_mode_set(int mode) 513{ 514 KASSERT(pci_mode == -1 || pci_mode == mode); 515 516 pci_mode = mode; 517} 518 519int 520pci_mode_detect(void) 521{ 522 uint32_t sav, val; 523 int i; 524 pcireg_t idreg; 525 extern char cpu_brand_string[]; 526 527 if (pci_mode != -1) 528 return pci_mode; 529 530 /* 531 * We try to divine which configuration mode the host bridge wants. 532 */ 533 534 sav = inl(PCI_MODE1_ADDRESS_REG); 535 536 pci_mode = 1; /* assume this for now */ 537 /* 538 * catch some known buggy implementations of mode 1 539 */ 540 for (i = 0; i < __arraycount(pcim1_quirk_tbl); i++) { 541 pcitag_t t; 542 543 if (!pcim1_quirk_tbl[i].tag) 544 break; 545 t.mode1 = pcim1_quirk_tbl[i].tag; 546 idreg = pci_conf_read(0, t, PCI_ID_REG); /* needs "pci_mode" */ 547 if (idreg == pcim1_quirk_tbl[i].id) { 548#ifdef DEBUG 549 printf("known mode 1 PCI chipset (%08x)\n", 550 idreg); 551#endif 552 return (pci_mode); 553 } 554 } 555 if (memcmp(cpu_brand_string, "QEMU", 4) == 0) { 556 /* PR 45671, https://bugs.launchpad.net/qemu/+bug/897771 */ 557#ifdef DEBUG 558 printf("forcing PCI mode 1 for QEMU\n"); 559#endif 560 return (pci_mode); 561 } 562 563 /* 564 * Strong check for standard compliant mode 1: 565 * 1. bit 31 ("enable") can be set 566 * 2. byte/word access does not affect register 567 */ 568 outl(PCI_MODE1_ADDRESS_REG, PCI_MODE1_ENABLE); 569 outb(PCI_MODE1_ADDRESS_REG + 3, 0); 570 outw(PCI_MODE1_ADDRESS_REG + 2, 0); 571 val = inl(PCI_MODE1_ADDRESS_REG); 572 if ((val & 0x80fffffc) != PCI_MODE1_ENABLE) { 573#ifdef DEBUG 574 printf("pci_mode_detect: mode 1 enable failed (%x)\n", 575 val); 576#endif 577 goto not1; 578 } 579 outl(PCI_MODE1_ADDRESS_REG, 0); 580 val = inl(PCI_MODE1_ADDRESS_REG); 581 if ((val & 0x80fffffc) != 0) 582 goto not1; 583 return (pci_mode); 584not1: 585 outl(PCI_MODE1_ADDRESS_REG, sav); 586 587 /* 588 * This mode 2 check is quite weak (and known to give false 589 * positives on some Compaq machines). 590 * However, this doesn't matter, because this is the 591 * last test, and simply no PCI devices will be found if 592 * this happens. 593 */ 594 outb(PCI_MODE2_ENABLE_REG, 0); 595 outb(PCI_MODE2_FORWARD_REG, 0); 596 if (inb(PCI_MODE2_ENABLE_REG) != 0 || 597 inb(PCI_MODE2_FORWARD_REG) != 0) 598 goto not2; 599 return (pci_mode = 2); 600not2: 601 602 return (pci_mode = 0); 603} 604 605/* 606 * Determine which flags should be passed to the primary PCI bus's 607 * autoconfiguration node. We use this to detect broken chipsets 608 * which cannot safely use memory-mapped device access. 609 */ 610int 611pci_bus_flags(void) 612{ 613 int rval = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY | 614 PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY; 615 int device, maxndevs; 616 pcitag_t tag; 617 pcireg_t id; 618 619 maxndevs = pci_bus_maxdevs(NULL, 0); 620 621 for (device = 0; device < maxndevs; device++) { 622 tag = pci_make_tag(NULL, 0, device, 0); 623 id = pci_conf_read(NULL, tag, PCI_ID_REG); 624 625 /* Invalid vendor ID value? */ 626 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 627 continue; 628 /* XXX Not invalid, but we've done this ~forever. */ 629 if (PCI_VENDOR(id) == 0) 630 continue; 631 632 switch (PCI_VENDOR(id)) { 633 case PCI_VENDOR_SIS: 634 switch (PCI_PRODUCT(id)) { 635 case PCI_PRODUCT_SIS_85C496: 636 goto disable_mem; 637 } 638 break; 639 } 640 } 641 642 return (rval); 643 644 disable_mem: 645 printf("Warning: broken PCI-Host bridge detected; " 646 "disabling memory-mapped access\n"); 647 rval &= ~(PCI_FLAGS_MEM_OKAY|PCI_FLAGS_MRL_OKAY|PCI_FLAGS_MRM_OKAY| 648 PCI_FLAGS_MWI_OKAY); 649 return (rval); 650} 651 652void 653pci_device_foreach(pci_chipset_tag_t pc, int maxbus, 654 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 655{ 656 pci_device_foreach_min(pc, 0, maxbus, func, context); 657} 658 659void 660pci_device_foreach_min(pci_chipset_tag_t pc, int minbus, int maxbus, 661 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *context) 662{ 663 const struct pci_quirkdata *qd; 664 int bus, device, function, maxdevs, nfuncs; 665 pcireg_t id, bhlcr; 666 pcitag_t tag; 667 668 for (bus = minbus; bus <= maxbus; bus++) { 669 maxdevs = pci_bus_maxdevs(pc, bus); 670 for (device = 0; device < maxdevs; device++) { 671 tag = pci_make_tag(pc, bus, device, 0); 672 id = pci_conf_read(pc, tag, PCI_ID_REG); 673 674 /* Invalid vendor ID value? */ 675 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 676 continue; 677 /* XXX Not invalid, but we've done this ~forever. */ 678 if (PCI_VENDOR(id) == 0) 679 continue; 680 681 qd = pci_lookup_quirkdata(PCI_VENDOR(id), 682 PCI_PRODUCT(id)); 683 684 bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG); 685 if (PCI_HDRTYPE_MULTIFN(bhlcr) || 686 (qd != NULL && 687 (qd->quirks & PCI_QUIRK_MULTIFUNCTION) != 0)) 688 nfuncs = 8; 689 else 690 nfuncs = 1; 691 692 for (function = 0; function < nfuncs; function++) { 693 tag = pci_make_tag(pc, bus, device, function); 694 id = pci_conf_read(pc, tag, PCI_ID_REG); 695 696 /* Invalid vendor ID value? */ 697 if (PCI_VENDOR(id) == PCI_VENDOR_INVALID) 698 continue; 699 /* 700 * XXX Not invalid, but we've done this 701 * ~forever. 702 */ 703 if (PCI_VENDOR(id) == 0) 704 continue; 705 (*func)(pc, tag, context); 706 } 707 } 708 } 709} 710 711void 712pci_bridge_foreach(pci_chipset_tag_t pc, int minbus, int maxbus, 713 void (*func)(pci_chipset_tag_t, pcitag_t, void *), void *ctx) 714{ 715 struct pci_bridge_hook_arg bridge_hook; 716 717 bridge_hook.func = func; 718 bridge_hook.arg = ctx; 719 720 pci_device_foreach_min(pc, minbus, maxbus, pci_bridge_hook, 721 &bridge_hook); 722} 723 724static void 725pci_bridge_hook(pci_chipset_tag_t pc, pcitag_t tag, void *ctx) 726{ 727 struct pci_bridge_hook_arg *bridge_hook = (void *)ctx; 728 pcireg_t reg; 729 730 reg = pci_conf_read(pc, tag, PCI_CLASS_REG); 731 if (PCI_CLASS(reg) == PCI_CLASS_BRIDGE && 732 (PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_PCI || 733 PCI_SUBCLASS(reg) == PCI_SUBCLASS_BRIDGE_CARDBUS)) { 734 (*bridge_hook->func)(pc, tag, bridge_hook->arg); 735 } 736} 737 738static const void * 739bit_to_function_pointer(const struct pci_overrides *ov, uint64_t bit) 740{ 741 switch (bit) { 742 case PCI_OVERRIDE_CONF_READ: 743 return ov->ov_conf_read; 744 case PCI_OVERRIDE_CONF_WRITE: 745 return ov->ov_conf_write; 746 case PCI_OVERRIDE_INTR_MAP: 747 return ov->ov_intr_map; 748 case PCI_OVERRIDE_INTR_STRING: 749 return ov->ov_intr_string; 750 case PCI_OVERRIDE_INTR_EVCNT: 751 return ov->ov_intr_evcnt; 752 case PCI_OVERRIDE_INTR_ESTABLISH: 753 return ov->ov_intr_establish; 754 case PCI_OVERRIDE_INTR_DISESTABLISH: 755 return ov->ov_intr_disestablish; 756 case PCI_OVERRIDE_MAKE_TAG: 757 return ov->ov_make_tag; 758 case PCI_OVERRIDE_DECOMPOSE_TAG: 759 return ov->ov_decompose_tag; 760 default: 761 return NULL; 762 } 763} 764 765void 766pci_chipset_tag_destroy(pci_chipset_tag_t pc) 767{ 768 kmem_free(pc, sizeof(struct pci_chipset_tag)); 769} 770 771int 772pci_chipset_tag_create(pci_chipset_tag_t opc, const uint64_t present, 773 const struct pci_overrides *ov, void *ctx, pci_chipset_tag_t *pcp) 774{ 775 uint64_t bit, bits, nbits; 776 pci_chipset_tag_t pc; 777 const void *fp; 778 779 if (ov == NULL || present == 0) 780 return EINVAL; 781 782 pc = kmem_alloc(sizeof(struct pci_chipset_tag), KM_SLEEP); 783 784 if (pc == NULL) 785 return ENOMEM; 786 787 pc->pc_super = opc; 788 789 for (bits = present; bits != 0; bits = nbits) { 790 nbits = bits & (bits - 1); 791 bit = nbits ^ bits; 792 if ((fp = bit_to_function_pointer(ov, bit)) == NULL) { 793#ifdef DEBUG 794 printf("%s: missing bit %" PRIx64 "\n", __func__, bit); 795#endif 796 goto einval; 797 } 798 } 799 800 pc->pc_ov = ov; 801 pc->pc_present = present; 802 pc->pc_ctx = ctx; 803 804 *pcp = pc; 805 806 return 0; 807einval: 808 kmem_free(pc, sizeof(struct pci_chipset_tag)); 809 return EINVAL; 810} 811 812static void 813x86_genfb_set_mapreg(void *opaque, int index, int r, int g, int b) 814{ 815 outb(0x3c0 + VGA_DAC_ADDRW, index); 816 outb(0x3c0 + VGA_DAC_PALETTE, (uint8_t)r >> 2); 817 outb(0x3c0 + VGA_DAC_PALETTE, (uint8_t)g >> 2); 818 outb(0x3c0 + VGA_DAC_PALETTE, (uint8_t)b >> 2); 819} 820 821static bool 822x86_genfb_setmode(struct genfb_softc *sc, int newmode) 823{ 824#if NGENFB > 0 825 static int curmode = WSDISPLAYIO_MODE_EMUL; 826 827 switch (newmode) { 828 case WSDISPLAYIO_MODE_EMUL: 829 x86_genfb_mtrr_init(sc->sc_fboffset, 830 sc->sc_height * sc->sc_stride); 831#if NACPICA > 0 && defined(VGA_POST) 832 if (curmode != newmode) { 833 if (vga_posth != NULL && acpi_md_vesa_modenum != 0) { 834 vga_post_set_vbe(vga_posth, 835 acpi_md_vesa_modenum); 836 } 837 } 838#endif 839 break; 840 } 841 842 curmode = newmode; 843#endif 844 return true; 845} 846 847static bool 848x86_genfb_suspend(device_t dev, const pmf_qual_t *qual) 849{ 850 return true; 851} 852 853static bool 854x86_genfb_resume(device_t dev, const pmf_qual_t *qual) 855{ 856#if NGENFB > 0 857 struct pci_genfb_softc *psc = device_private(dev); 858 859#if NACPICA > 0 && defined(VGA_POST) 860 if (vga_posth != NULL && acpi_md_vbios_reset == 2) { 861 vga_post_call(vga_posth); 862 if (acpi_md_vesa_modenum != 0) 863 vga_post_set_vbe(vga_posth, acpi_md_vesa_modenum); 864 } 865#endif 866 genfb_restore_palette(&psc->sc_gen); 867#endif 868 869 return true; 870} 871 872device_t 873device_pci_register(device_t dev, void *aux) 874{ 875 static bool found_console = false; 876 877 device_pci_props_register(dev, aux); 878 879 /* 880 * Handle network interfaces here, the attachment information is 881 * not available driver-independently later. 882 * 883 * For disks, there is nothing useful available at attach time. 884 */ 885 if (device_class(dev) == DV_IFNET) { 886 struct btinfo_netif *bin = lookup_bootinfo(BTINFO_NETIF); 887 if (bin == NULL) 888 return NULL; 889 890 /* 891 * We don't check the driver name against the device name 892 * passed by the boot ROM. The ROM should stay usable if 893 * the driver becomes obsolete. The physical attachment 894 * information (checked below) must be sufficient to 895 * idenfity the device. 896 */ 897 if (bin->bus == BI_BUS_PCI && 898 device_is_a(device_parent(dev), "pci")) { 899 struct pci_attach_args *paa = aux; 900 int b, d, f; 901 902 /* 903 * Calculate BIOS representation of: 904 * 905 * <bus,device,function> 906 * 907 * and compare. 908 */ 909 pci_decompose_tag(paa->pa_pc, paa->pa_tag, &b, &d, &f); 910 if (bin->addr.tag == ((b << 8) | (d << 3) | f)) 911 return dev; 912 } 913 } 914 if (device_parent(dev) && device_is_a(device_parent(dev), "pci") && 915 found_console == false) { 916 struct btinfo_framebuffer *fbinfo; 917 struct pci_attach_args *pa = aux; 918 prop_dictionary_t dict; 919 920 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_DISPLAY) { 921#if NWSDISPLAY > 0 && NGENFB > 0 922 extern struct vcons_screen x86_genfb_console_screen; 923 struct rasops_info *ri; 924 925 ri = &x86_genfb_console_screen.scr_ri; 926#endif 927 928 fbinfo = lookup_bootinfo(BTINFO_FRAMEBUFFER); 929 dict = device_properties(dev); 930 /* 931 * framebuffer drivers other than genfb can work 932 * without the address property 933 */ 934 if (fbinfo != NULL) { 935 if (fbinfo->physaddr != 0) { 936 prop_dictionary_set_uint32(dict, "width", 937 fbinfo->width); 938 prop_dictionary_set_uint32(dict, "height", 939 fbinfo->height); 940 prop_dictionary_set_uint8(dict, "depth", 941 fbinfo->depth); 942 prop_dictionary_set_uint16(dict, "linebytes", 943 fbinfo->stride); 944 945 prop_dictionary_set_uint64(dict, "address", 946 fbinfo->physaddr); 947#if NWSDISPLAY > 0 && NGENFB > 0 948 if (ri->ri_bits != NULL) { 949 prop_dictionary_set_uint64(dict, 950 "virtual_address", 951 (vaddr_t)ri->ri_bits); 952 } 953#endif 954 } 955#if notyet 956 prop_dictionary_set_bool(dict, "splash", 957 fbinfo->flags & BI_FB_SPLASH ? 958 true : false); 959#endif 960 if (fbinfo->depth == 8) { 961 gfb_cb.gcc_cookie = NULL; 962 gfb_cb.gcc_set_mapreg = 963 x86_genfb_set_mapreg; 964 prop_dictionary_set_uint64(dict, 965 "cmap_callback", 966 (uint64_t)(uintptr_t)&gfb_cb); 967 } 968 if (fbinfo->physaddr != 0) { 969 mode_cb.gmc_setmode = x86_genfb_setmode; 970 prop_dictionary_set_uint64(dict, 971 "mode_callback", 972 (uint64_t)(uintptr_t)&mode_cb); 973 } 974 975#if NWSDISPLAY > 0 && NGENFB > 0 976 if (device_is_a(dev, "genfb")) { 977 x86_genfb_set_console_dev(dev); 978#ifdef DDB 979 db_trap_callback = 980 x86_genfb_ddb_trap_callback; 981#endif 982 } 983#endif 984 } 985 prop_dictionary_set_bool(dict, "is_console", true); 986 prop_dictionary_set_bool(dict, "clear-screen", false); 987#if NWSDISPLAY > 0 && NGENFB > 0 988 prop_dictionary_set_uint16(dict, "cursor-row", 989 x86_genfb_console_screen.scr_ri.ri_crow); 990#endif 991#if notyet 992 prop_dictionary_set_bool(dict, "splash", 993 fbinfo->flags & BI_FB_SPLASH ? true : false); 994#endif 995 pmf_cb.gpc_suspend = x86_genfb_suspend; 996 pmf_cb.gpc_resume = x86_genfb_resume; 997 prop_dictionary_set_uint64(dict, 998 "pmf_callback", (uint64_t)(uintptr_t)&pmf_cb); 999#ifdef VGA_POST 1000 vga_posth = vga_post_init(pa->pa_bus, pa->pa_device, 1001 pa->pa_function); 1002#endif 1003 found_console = true; 1004 return NULL; 1005 } 1006 } 1007 return NULL; 1008} 1009