1/* $NetBSD$ */ 2/* 3 * Copyright (c) 2007, 2008, 2010 KIYOHARA Takashi 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27#include <sys/cdefs.h> 28__KERNEL_RCSID(0, "$NetBSD$"); 29 30#include "opt_evbarm_boardtype.h" 31#include "opt_ddb.h" 32#include "opt_pci.h" 33#include "opt_mvsoc.h" 34#include "com.h" 35#include "gtpci.h" 36#include "mvpex.h" 37 38#include <sys/param.h> 39#include <sys/kernel.h> 40#include <sys/reboot.h> 41#include <sys/systm.h> 42#include <sys/termios.h> 43 44#include <prop/proplib.h> 45 46#include <dev/cons.h> 47#include <dev/md.h> 48 49#include <dev/marvell/marvellreg.h> 50#include <dev/marvell/marvellvar.h> 51#include <dev/pci/pcireg.h> 52#include <dev/pci/pcivar.h> 53 54#include <machine/autoconf.h> 55#include <machine/bootconfig.h> 56#include <machine/pci_machdep.h> 57 58#include <uvm/uvm_extern.h> 59 60#include <arm/db_machdep.h> 61#include <arm/undefined.h> 62#include <arm/arm32/machdep.h> 63 64#include <arm/marvell/mvsocreg.h> 65#include <arm/marvell/mvsocvar.h> 66#include <arm/marvell/orionreg.h> 67#include <arm/marvell/kirkwoodreg.h> 68#include <arm/marvell/mvsocgppvar.h> 69 70#include <evbarm/marvell/marvellreg.h> 71#include <evbarm/marvell/marvellvar.h> 72 73#include <ddb/db_extern.h> 74#include <ddb/db_sym.h> 75 76#include "ksyms.h" 77 78 79/* Kernel text starts 2MB in from the bottom of the kernel address space. */ 80#define KERNEL_TEXT_BASE (KERNEL_BASE + 0x00000000) 81#define KERNEL_VM_BASE (KERNEL_BASE + 0x01000000) 82 83/* 84 * The range 0xc1000000 - 0xccffffff is available for kernel VM space 85 * Core-logic registers and I/O mappings occupy 0xfd000000 - 0xffffffff 86 */ 87#define KERNEL_VM_SIZE 0x0c000000 88 89/* 90 * Address to call from cpu_reset() to reset the machine. 91 * This is machine architecture dependent as it varies depending 92 * on where the ROM appears when you turn the MMU off. 93 */ 94 95u_int cpu_reset_address = 0xffff0000; 96 97/* Define various stack sizes in pages */ 98#define IRQ_STACK_SIZE 1 99#define ABT_STACK_SIZE 1 100#ifdef IPKDB 101#define UND_STACK_SIZE 2 102#else 103#define UND_STACK_SIZE 1 104#endif 105 106BootConfig bootconfig; /* Boot config storage */ 107static char bootargs[MAX_BOOT_STRING]; 108char *boot_args = NULL; 109 110vm_offset_t physical_start; 111vm_offset_t physical_freestart; 112vm_offset_t physical_freeend; 113vm_offset_t physical_end; 114u_int free_pages; 115int physmem = 0; 116 117/* Physical and virtual addresses for some global pages */ 118pv_addr_t systempage; 119pv_addr_t irqstack; 120pv_addr_t undstack; 121pv_addr_t abtstack; 122pv_addr_t kernelstack; 123 124vm_offset_t msgbufphys; 125 126extern u_int data_abort_handler_address; 127extern u_int prefetch_abort_handler_address; 128extern u_int undefined_handler_address; 129 130extern char _end[]; 131 132#define KERNEL_PT_SYS 0 /* Page table for mapping proc0 zero page */ 133#define KERNEL_PT_KERNEL 1 /* Page table for mapping kernel */ 134#define KERNEL_PT_KERNEL_NUM 4 135#define KERNEL_PT_VMDATA (KERNEL_PT_KERNEL + KERNEL_PT_KERNEL_NUM) 136/* Page tables for mapping kernel VM */ 137#define KERNEL_PT_VMDATA_NUM 4 /* start with 16MB of KVM */ 138#define NUM_KERNEL_PTS (KERNEL_PT_VMDATA + KERNEL_PT_VMDATA_NUM) 139 140pv_addr_t kernel_pt_table[NUM_KERNEL_PTS]; 141 142/* 143 * Macros to translate between physical and virtual for a subset of the 144 * kernel address space. *Not* for general use. 145 */ 146#define KERNEL_BASE_PHYS physical_start 147#define KERN_VTOPHYS(va) \ 148 ((paddr_t)((vaddr_t)va - KERNEL_BASE + KERNEL_BASE_PHYS)) 149#define KERN_PHYSTOV(pa) \ 150 ((vaddr_t)((paddr_t)pa - KERNEL_BASE_PHYS + KERNEL_BASE)) 151 152 153#include "com.h" 154#if NCOM > 0 155#include <dev/ic/comreg.h> 156#include <dev/ic/comvar.h> 157#endif 158 159#ifndef CONSPEED 160#define CONSPEED B115200 /* It's a setting of the default of u-boot */ 161#endif 162#ifndef CONMODE 163#define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */ 164 165int comcnspeed = CONSPEED; 166int comcnmode = CONMODE; 167#endif 168 169#include "opt_kgdb.h" 170#ifdef KGDB 171#include <sys/kgdb.h> 172#endif 173 174static void marvell_device_register(device_t, void *); 175#if NGTPCI > 0 || NMVPEX > 0 176static void marvell_startend_by_tag(int, uint64_t *, uint64_t *); 177#endif 178 179static void 180marvell_system_reset(void) 181{ 182 /* unmask soft reset */ 183 write_mlmbreg(MVSOC_MLMB_RSTOUTNMASKR, 184 MVSOC_MLMB_RSTOUTNMASKR_SOFTRSTOUTEN); 185 /* assert soft reset */ 186 write_mlmbreg(MVSOC_MLMB_SSRR, MVSOC_MLMB_SSRR_SYSTEMSOFTRST); 187 /* if we're still running, jump to the reset address */ 188 cpu_reset(); 189 /*NOTREACHED*/ 190} 191 192void 193cpu_reboot(int howto, char *bootstr) 194{ 195 196 /* 197 * If we are still cold then hit the air brakes 198 * and crash to earth fast 199 */ 200 if (cold) { 201 doshutdownhooks(); 202 printf("The operating system has halted.\r\n"); 203 printf("Please press any key to reboot.\r\n"); 204 cngetc(); 205 printf("rebooting...\r\n"); 206 marvell_system_reset(); 207 } 208 209 /* 210 * If RB_NOSYNC was not specified sync the discs. 211 * Note: Unless cold is set to 1 here, syslogd will die during the 212 * unmount. It looks like syslogd is getting woken up only to find 213 * that it cannot page part of the binary in as the filesystem has 214 * been unmounted. 215 */ 216 if (!(howto & RB_NOSYNC)) 217 bootsync(); 218 219 /* Say NO to interrupts */ 220 splhigh(); 221 222 /* Do a dump if requested. */ 223 if ((howto & (RB_DUMP | RB_HALT)) == RB_DUMP) 224 dumpsys(); 225 226 /* Run any shutdown hooks */ 227 doshutdownhooks(); 228 229 /* Make sure IRQ's are disabled */ 230 IRQdisable; 231 232 if (howto & RB_HALT) { 233 printf("The operating system has halted.\r\n"); 234 printf("Please press any key to reboot.\r\n"); 235 cngetc(); 236 } 237 238 printf("rebooting...\r\n"); 239 marvell_system_reset(); 240 241 /*NOTREACHED*/ 242} 243 244static inline 245pd_entry_t * 246read_ttb(void) 247{ 248 long ttb; 249 250 __asm volatile("mrc p15, 0, %0, c2, c0, 0" : "=r" (ttb)); 251 252 return (pd_entry_t *)(ttb & ~((1<<14)-1)); 253} 254 255/* 256 * Static device mappings. These peripheral registers are mapped at 257 * fixed virtual addresses very early in initarm() so that we can use 258 * them while booting the kernel, and stay at the same address 259 * throughout whole kernel's life time. 260 * 261 * We use this table twice; once with bootstrap page table, and once 262 * with kernel's page table which we build up in initarm(). 263 * 264 * Since we map these registers into the bootstrap page table using 265 * pmap_devmap_bootstrap() which calls pmap_map_chunk(), we map 266 * registers segment-aligned and segment-rounded in order to avoid 267 * using the 2nd page tables. 268 */ 269#define _A(a) ((a) & ~L1_S_OFFSET) 270#define _S(s) (((s) + L1_S_SIZE - 1) & ~(L1_S_SIZE-1)) 271 272static const struct pmap_devmap marvell_devmap[] = { 273 { 274 MARVELL_INTERREGS_VBASE, 275 _A(MARVELL_INTERREGS_PBASE), 276 _S(MARVELL_INTERREGS_SIZE), 277 VM_PROT_READ|VM_PROT_WRITE, 278 PTE_NOCACHE, 279 }, 280 281 { 0, 0, 0, 0, 0 } 282}; 283 284#undef _A 285#undef _S 286 287extern uint32_t *u_boot_args[]; 288 289/* 290 * u_int initarm(...) 291 * 292 * Initial entry point on startup. This gets called before main() is 293 * entered. 294 * It should be responsible for setting up everything that must be 295 * in place when main is called. 296 * This includes 297 * Taking a copy of the boot configuration structure. 298 * Initialising the physical console so characters can be printed. 299 * Setting up page tables for the kernel 300 * Relocating the kernel to the bottom of physical memory 301 */ 302u_int 303initarm(void *arg) 304{ 305 uint32_t target, attr, base, size; 306 u_int l1pagetable; 307 int loop, pt_index, cs, memtag = 0, iotag = 0, window; 308 309 /* map some peripheral registers */ 310 pmap_devmap_bootstrap((vaddr_t)read_ttb(), marvell_devmap); 311 312 mvsoc_bootstrap(MARVELL_INTERREGS_VBASE); 313 314 /* Get ready for splfoo() */ 315 switch (mvsoc_model()) { 316#ifdef ORION 317 case MARVELL_ORION_1_88F1181: 318 case MARVELL_ORION_1_88F5082: 319 case MARVELL_ORION_1_88F5180N: 320 case MARVELL_ORION_1_88F5181: 321 case MARVELL_ORION_1_88F5182: 322 case MARVELL_ORION_1_88F6082: 323 case MARVELL_ORION_1_88F6183: 324 case MARVELL_ORION_1_88W8660: 325 case MARVELL_ORION_2_88F1281: 326 case MARVELL_ORION_2_88F5281: 327 orion_intr_bootstrap(); 328 329 memtag = ORION_TAG_PEX0_MEM; 330 iotag = ORION_TAG_PEX0_IO; 331 nwindow = ORION_MLMB_NWINDOW; 332 nremap = ORION_MLMB_NREMAP; 333 334 orion_getclks(MARVELL_INTERREGS_VBASE); 335 break; 336#endif /* ORION */ 337 338#ifdef KIRKWOOD 339 case MARVELL_KIRKWOOD_88F6180: 340 case MARVELL_KIRKWOOD_88F6192: 341 case MARVELL_KIRKWOOD_88F6281: 342 kirkwood_intr_bootstrap(); 343 344 memtag = KIRKWOOD_TAG_PEX_MEM; 345 iotag = KIRKWOOD_TAG_PEX_IO; 346 nwindow = KIRKWOOD_MLMB_NWINDOW; 347 nremap = KIRKWOOD_MLMB_NREMAP; 348 349 kirkwood_getclks(MARVELL_INTERREGS_VBASE); 350 break; 351#endif /* KIRKWOOD */ 352 353#ifdef MV78XX0 354 case MARVELL_MV78XX0_MV78100: 355 case MARVELL_MV78XX0_MV78200: 356 mv78xx0_intr_bootstrap(); 357 358 memtag = MV78XX0_TAG_PEX_MEM; 359 iotag = MV78XX0_TAG_PEX_IO; 360 nwindow = MV78XX0_MLMB_NWINDOW; 361 nremap = MV78XX0_MLMB_NREMAP; 362 363 mv78xx0_getclks(MARVELL_INTERREGS_VBASE); 364 break; 365#endif /* MV78XX0 */ 366 367 default: 368 /* We can't output console here yet... */ 369 panic("unknown model...\n"); 370 371 /* NOTREACHED */ 372 } 373 374 /* Reset PCI-Express space to window register. */ 375 window = mvsoc_target(memtag, &target, &attr, NULL, NULL); 376 write_mlmbreg(MVSOC_MLMB_WCR(window), 377 MVSOC_MLMB_WCR_WINEN | 378 MVSOC_MLMB_WCR_TARGET(target) | 379 MVSOC_MLMB_WCR_ATTR(attr) | 380 MVSOC_MLMB_WCR_SIZE(MARVELL_PEXMEM_SIZE)); 381 write_mlmbreg(MVSOC_MLMB_WBR(window), 382 MARVELL_PEXMEM_PBASE & MVSOC_MLMB_WBR_BASE_MASK); 383#ifdef PCI_NETBSD_CONFIGURE 384 if (window < nremap) { 385 write_mlmbreg(MVSOC_MLMB_WRLR(window), 386 MARVELL_PEXMEM_PBASE & MVSOC_MLMB_WRLR_REMAP_MASK); 387 write_mlmbreg(MVSOC_MLMB_WRHR(window), 0); 388 } 389#endif 390 window = mvsoc_target(iotag, &target, &attr, NULL, NULL); 391 write_mlmbreg(MVSOC_MLMB_WCR(window), 392 MVSOC_MLMB_WCR_WINEN | 393 MVSOC_MLMB_WCR_TARGET(target) | 394 MVSOC_MLMB_WCR_ATTR(attr) | 395 MVSOC_MLMB_WCR_SIZE(MARVELL_PEXIO_SIZE)); 396 write_mlmbreg(MVSOC_MLMB_WBR(window), 397 MARVELL_PEXIO_PBASE & MVSOC_MLMB_WBR_BASE_MASK); 398#ifdef PCI_NETBSD_CONFIGURE 399 if (window < nremap) { 400 write_mlmbreg(MVSOC_MLMB_WRLR(window), 401 MARVELL_PEXIO_PBASE & MVSOC_MLMB_WRLR_REMAP_MASK); 402 write_mlmbreg(MVSOC_MLMB_WRHR(window), 0); 403 } 404#endif 405 406 /* 407 * Heads up ... Setup the CPU / MMU / TLB functions 408 */ 409 if (set_cpufuncs()) 410 panic("cpu not recognized!"); 411 412 /* 413 * U-Boot doesn't use the virtual memory. 414 * 415 * Physical Address Range Description 416 * ----------------------- ---------------------------------- 417 * 0x00000000 - 0x0fffffff SDRAM Bank 0 (max 256MB) 418 * 0x10000000 - 0x1fffffff SDRAM Bank 1 (max 256MB) 419 * 0x20000000 - 0x2fffffff SDRAM Bank 2 (max 256MB) 420 * 0x30000000 - 0x3fffffff SDRAM Bank 3 (max 256MB) 421 * 0xf1000000 - 0xf10fffff SoC Internal Registers 422 */ 423 424 cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT); 425 426 consinit(); 427 428 /* Talk to the user */ 429#define BDSTR(s) _BDSTR(s) 430#define _BDSTR(s) #s 431 printf("\nNetBSD/evbarm (" BDSTR(EVBARM_BOARDTYPE) ") booting ...\n"); 432 433 /* copy command line U-Boot gave us */ 434 strncpy(bootargs, (char *)u_boot_args[3], sizeof(bootargs)); 435 436#ifdef VERBOSE_INIT_ARM 437 printf("initarm: Configuring system ...\n"); 438#endif 439 440 bootconfig.dramblocks = 0; 441 physical_end = physmem = 0; 442 for (cs = MARVELL_TAG_SDRAM_CS0; cs <= MARVELL_TAG_SDRAM_CS3; cs++) { 443 mvsoc_target(cs, &target, &attr, &base, &size); 444 if (size == 0) 445 continue; 446 447 bootconfig.dram[bootconfig.dramblocks].address = base; 448 bootconfig.dram[bootconfig.dramblocks].pages = size / PAGE_SIZE; 449 450 if (base != physical_end) 451 panic("memory hole not support"); 452 453 physical_end += size; 454 physmem += size / PAGE_SIZE; 455 456 bootconfig.dramblocks++; 457 } 458 459 /* 460 * Set up the variables that define the availablilty of 461 * physical memory. For now, we're going to set 462 * physical_freestart to 0xa0008000 (where the kernel 463 * was loaded), and allocate the memory we need downwards. 464 * If we get too close to the L1 table that we set up, we 465 * will panic. We will update physical_freestart and 466 * physical_freeend later to reflect what pmap_bootstrap() 467 * wants to see. 468 * 469 * XXX pmap_bootstrap() needs an enema. 470 */ 471 physical_start = bootconfig.dram[0].address; 472 473 /* 474 * Our kernel is at the beginning of memory, so set our free space to 475 * all the memory after the kernel. 476 */ 477 physical_freestart = KERN_VTOPHYS(round_page((vaddr_t)_end)); 478 physical_freeend = physical_end; 479 480#ifdef VERBOSE_INIT_ARM 481 /* Tell the user about the memory */ 482 printf("physmemory: %d pages at 0x%08lx -> 0x%08lx\n", physmem, 483 physical_start, physical_end - 1); 484#endif 485 486 /* 487 * Okay, the kernel starts 8kB in from the bottom of physical 488 * memory. We are going to allocate our bootstrap pages upwards 489 * from physical_freestart. 490 * 491 * We need to allocate some fixed page tables to get the kernel 492 * going. We allocate one page directory and a number of page 493 * tables and store the physical addresses in the kernel_pt_table 494 * array. 495 * 496 * The kernel page directory must be on a 16K boundary. The page 497 * tables must be on 4K bounaries. What we do is allocate the 498 * page directory on the first 16K boundary that we encounter, and 499 * the page tables on 4K boundaries otherwise. Since we allocate 500 * at least 3 L2 page tables, we are guaranteed to encounter at 501 * least one 16K aligned region. 502 */ 503 504#ifdef VERBOSE_INIT_ARM 505 printf("Allocating page tables\n"); 506#endif 507 508 free_pages = (physical_freeend - physical_freestart) / PAGE_SIZE; 509 510#ifdef VERBOSE_INIT_ARM 511 printf("freestart = 0x%08lx, free_pages = %d (0x%08x)\n", 512 physical_freestart, free_pages, free_pages); 513#endif 514 515 /* 516 * Define a macro to simplify memory allocation. As we allocate the 517 * memory, make sure that we don't walk over our temporary first level 518 * translation table. 519 */ 520#define valloc_pages(var, np) \ 521 (var).pv_pa = physical_freestart; \ 522 physical_freestart += ((np) * PAGE_SIZE); \ 523 if (physical_freestart > (physical_freeend - L1_TABLE_SIZE)) \ 524 panic("initarm: out of memory"); \ 525 free_pages -= (np); \ 526 (var).pv_va = KERN_PHYSTOV((var).pv_pa); \ 527 memset((char *)(var).pv_va, 0, ((np) * PAGE_SIZE)); 528 529 pt_index = 0; 530 kernel_l1pt.pv_pa = 0; 531 kernel_l1pt.pv_va = 0; 532 for (loop = 0; loop <= NUM_KERNEL_PTS; ++loop) { 533 /* Are we 16KB aligned for an L1 ? */ 534 if ((physical_freestart & (L1_TABLE_SIZE - 1)) == 0 && 535 kernel_l1pt.pv_pa == 0) { 536 valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE); 537 } else { 538 valloc_pages(kernel_pt_table[pt_index], 539 L2_TABLE_SIZE / PAGE_SIZE); 540 ++pt_index; 541 } 542 } 543 544 /* This should never be able to happen but better confirm that. */ 545 if (!kernel_l1pt.pv_pa || 546 (kernel_l1pt.pv_pa & (L1_TABLE_SIZE - 1)) != 0) 547 panic("initarm: Failed to align the kernel page directory"); 548 549 /* 550 * Allocate a page for the system page mapped to V0x00000000 551 * This page will just contain the system vectors and can be 552 * shared by all processes. 553 */ 554 valloc_pages(systempage, 1); 555 systempage.pv_va = ARM_VECTORS_HIGH; 556 557 /* Allocate stacks for all modes */ 558 valloc_pages(irqstack, IRQ_STACK_SIZE); 559 valloc_pages(abtstack, ABT_STACK_SIZE); 560 valloc_pages(undstack, UND_STACK_SIZE); 561 valloc_pages(kernelstack, UPAGES); 562 563#ifdef VERBOSE_INIT_ARM 564 printf("IRQ stack: p0x%08lx v0x%08lx\n", irqstack.pv_pa, 565 irqstack.pv_va); 566 printf("ABT stack: p0x%08lx v0x%08lx\n", abtstack.pv_pa, 567 abtstack.pv_va); 568 printf("UND stack: p0x%08lx v0x%08lx\n", undstack.pv_pa, 569 undstack.pv_va); 570 printf("SVC stack: p0x%08lx v0x%08lx\n", kernelstack.pv_pa, 571 kernelstack.pv_va); 572#endif 573 574 /* Allocate the message buffer. */ 575 { 576 pv_addr_t msgbuf; 577 578 valloc_pages(msgbuf, round_page(MSGBUFSIZE) / PAGE_SIZE); 579 msgbufphys = msgbuf.pv_pa; 580 } 581 582 /* 583 * Ok we have allocated physical pages for the primary kernel 584 * page tables 585 */ 586 587#ifdef VERBOSE_INIT_ARM 588 printf("Creating L1 page table at 0x%08lx\n", kernel_l1pt.pv_pa); 589#endif 590 591 /* 592 * Now we start construction of the L1 page table 593 * We start by mapping the L2 page tables into the L1. 594 * This means that we can replace L1 mappings later on if necessary 595 */ 596 l1pagetable = kernel_l1pt.pv_va; 597 598 /* Map the L2 pages tables in the L1 page table */ 599 pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH & -L2_S_SEGSIZE, 600 &kernel_pt_table[KERNEL_PT_SYS]); 601 for (loop = 0; loop < KERNEL_PT_KERNEL_NUM; loop++) 602 pmap_link_l2pt(l1pagetable, KERNEL_BASE + loop * 0x00400000, 603 &kernel_pt_table[KERNEL_PT_KERNEL + loop]); 604 for (loop = 0; loop < KERNEL_PT_VMDATA_NUM; loop++) 605 pmap_link_l2pt(l1pagetable, KERNEL_VM_BASE + loop * 0x00400000, 606 &kernel_pt_table[KERNEL_PT_VMDATA + loop]); 607 608 /* update the top of the kernel VM */ 609 pmap_curmaxkvaddr = 610 KERNEL_VM_BASE + (KERNEL_PT_VMDATA_NUM * 0x00400000); 611 612#ifdef VERBOSE_INIT_ARM 613 printf("Mapping kernel\n"); 614#endif 615 616 /* Now we fill in the L2 pagetable for the kernel static code/data */ 617 { 618 extern char etext[], _end[]; 619 size_t textsize = (uintptr_t)etext - KERNEL_TEXT_BASE; 620 size_t totalsize = (uintptr_t)_end - KERNEL_TEXT_BASE; 621 u_int logical; 622 623 textsize = (textsize + PGOFSET) & ~PGOFSET; 624 totalsize = (totalsize + PGOFSET) & ~PGOFSET; 625 626 logical = 0x00000000; /* offset of kernel in RAM */ 627 628 logical += pmap_map_chunk(l1pagetable, KERNEL_BASE + logical, 629 physical_start + logical, textsize, 630 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 631 logical += pmap_map_chunk(l1pagetable, KERNEL_BASE + logical, 632 physical_start + logical, totalsize - textsize, 633 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 634 } 635 636#ifdef VERBOSE_INIT_ARM 637 printf("Constructing L2 page tables\n"); 638#endif 639 640 /* Map the stack pages */ 641 pmap_map_chunk(l1pagetable, irqstack.pv_va, irqstack.pv_pa, 642 IRQ_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 643 pmap_map_chunk(l1pagetable, abtstack.pv_va, abtstack.pv_pa, 644 ABT_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 645 pmap_map_chunk(l1pagetable, undstack.pv_va, undstack.pv_pa, 646 UND_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 647 pmap_map_chunk(l1pagetable, kernelstack.pv_va, kernelstack.pv_pa, 648 UPAGES * PAGE_SIZE, VM_PROT_READ | VM_PROT_WRITE, PTE_CACHE); 649 650 pmap_map_chunk(l1pagetable, kernel_l1pt.pv_va, kernel_l1pt.pv_pa, 651 L1_TABLE_SIZE, VM_PROT_READ | VM_PROT_WRITE, PTE_PAGETABLE); 652 653 for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) 654 pmap_map_chunk(l1pagetable, kernel_pt_table[loop].pv_va, 655 kernel_pt_table[loop].pv_pa, L2_TABLE_SIZE, 656 VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE); 657 658 /* Map the vector page. */ 659 pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa, 660 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE); 661 662 /* 663 * Map integrated peripherals at same address in first level page 664 * table so that we can continue to use console. 665 */ 666 pmap_devmap_bootstrap(l1pagetable, marvell_devmap); 667 668 /* 669 * Now we have the real page tables in place so we can switch to them. 670 * Once this is done we will be running with the REAL kernel page 671 * tables. 672 */ 673 674 /* Switch tables */ 675#ifdef VERBOSE_INIT_ARM 676 printf("switching to new L1 page table @%#lx...", kernel_l1pt.pv_pa); 677#endif 678 679 cpu_setttb(kernel_l1pt.pv_pa); 680 cpu_tlb_flushID(); 681 cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)); 682 683 /* 684 * Moved from cpu_startup() as data_abort_handler() references 685 * this during uvm init. 686 */ 687 uvm_lwp_setuarea(&lwp0, kernelstack.pv_va); 688 689#ifdef VERBOSE_INIT_ARM 690 printf("bootstrap done.\n"); 691#endif 692 693 arm32_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL); 694 695 /* 696 * Pages were allocated during the secondary bootstrap for the 697 * stacks for different CPU modes. 698 * We must now set the r13 registers in the different CPU modes to 699 * point to these stacks. 700 * Since the ARM stacks use STMFD etc. we must set r13 to the top end 701 * of the stack memory. 702 */ 703#ifdef VERBOSE_INIT_ARM 704 printf("init subsystems: stacks "); 705#endif 706 707 set_stackptr(PSR_IRQ32_MODE, 708 irqstack.pv_va + IRQ_STACK_SIZE * PAGE_SIZE); 709 set_stackptr(PSR_ABT32_MODE, 710 abtstack.pv_va + ABT_STACK_SIZE * PAGE_SIZE); 711 set_stackptr(PSR_UND32_MODE, 712 undstack.pv_va + UND_STACK_SIZE * PAGE_SIZE); 713 714 /* 715 * Well we should set a data abort handler. 716 * Once things get going this will change as we will need a proper 717 * handler. 718 * Until then we will use a handler that just panics but tells us 719 * why. 720 * Initialisation of the vectors will just panic on a data abort. 721 * This just fills in a slightly better one. 722 */ 723#ifdef VERBOSE_INIT_ARM 724 printf("vectors "); 725#endif 726 data_abort_handler_address = (u_int)data_abort_handler; 727 prefetch_abort_handler_address = (u_int)prefetch_abort_handler; 728 undefined_handler_address = (u_int)undefinedinstruction_bounce; 729 730 /* Initialise the undefined instruction handlers */ 731#ifdef VERBOSE_INIT_ARM 732 printf("undefined "); 733#endif 734 undefined_init(); 735 736 /* Load memory into UVM. */ 737#ifdef VERBOSE_INIT_ARM 738 printf("page "); 739#endif 740 uvm_setpagesize(); /* initialize PAGE_SIZE-dependent variables */ 741 uvm_page_physload(atop(physical_freestart), atop(physical_freeend), 742 atop(physical_freestart), atop(physical_freeend), 743 VM_FREELIST_DEFAULT); 744 745 /* Boot strap pmap telling it where the kernel page table is */ 746#ifdef VERBOSE_INIT_ARM 747 printf("pmap "); 748#endif 749 pmap_bootstrap(KERNEL_VM_BASE, KERNEL_VM_BASE + KERNEL_VM_SIZE); 750 751#ifdef VERBOSE_INIT_ARM 752 printf("done.\n"); 753#endif 754 755#ifdef __HAVE_MEMORY_DISK__ 756 md_root_setconf(memory_disk, sizeof memory_disk); 757#endif 758 759 boot_args = bootargs; 760 parse_mi_bootargs(boot_args); 761 762#ifdef BOOTHOWTO 763 boothowto |= BOOTHOWTO; 764#endif 765 766#ifdef KGDB 767 if (boothowto & RB_KDB) { 768 kgdb_debug_init = 1; 769 kgdb_connect(1); 770 } 771#endif 772 773#ifdef DDB 774 db_machine_init(); 775 if (boothowto & RB_KDB) 776 Debugger(); 777#endif 778 779 /* we've a specific device_register routine */ 780 evbarm_device_register = marvell_device_register; 781 782 /* We return the new stack pointer address */ 783 return(kernelstack.pv_va + USPACE_SVC_STACK_TOP); 784} 785 786void 787consinit(void) 788{ 789 static int consinit_called = 0; 790 791 if (consinit_called != 0) 792 return; 793 794 consinit_called = 1; 795 796#if NCOM > 0 797 { 798 extern int mvuart_cnattach(bus_space_tag_t, bus_addr_t, int, 799 uint32_t, int); 800 801 if (mvuart_cnattach(&mvsoc_bs_tag, 802 MARVELL_INTERREGS_VBASE + MVSOC_COM0_BASE, 803 comcnspeed, mvTclk, comcnmode)) 804 panic("can't init serial console"); 805 } 806#else 807 panic("serial console not configured"); 808#endif 809} 810 811 812static void 813marvell_device_register(device_t dev, void *aux) 814{ 815 prop_dictionary_t dict = device_properties(dev); 816 817#if NCOM > 0 818 if (device_is_a(dev, "com") && 819 device_is_a(device_parent(dev), "mvsoc")) 820 prop_dictionary_set_uint32(dict, "frequency", mvTclk); 821#endif 822 if (device_is_a(dev, "gtidmac")) { 823 prop_dictionary_set_uint32(dict, 824 "dmb_speed", mvTclk * sizeof(uint32_t)); /* XXXXXX */ 825 prop_dictionary_set_uint32(dict, 826 "xore-irq-begin", ORION_IRQ_XOR0); 827 } 828#if NGTPCI > 0 && defined(ORION) 829 if (device_is_a(dev, "gtpci")) { 830 extern struct bus_space 831 orion_pci_io_bs_tag, orion_pci_mem_bs_tag; 832 extern struct arm32_pci_chipset arm32_gtpci_chipset; 833 834 prop_data_t io_bs_tag, mem_bs_tag, pc; 835 prop_array_t int2gpp; 836 prop_number_t gpp; 837 uint64_t start, end; 838 int i, j; 839 static struct { 840 const char *boardtype; 841 int pin[PCI_INTERRUPT_PIN_MAX]; 842 } hints[] = { 843 { "kuronas_x4", 844 { 11, PCI_INTERRUPT_PIN_NONE } }, 845 846 { NULL, 847 { PCI_INTERRUPT_PIN_NONE } }, 848 }; 849 850 arm32_gtpci_chipset.pc_conf_v = device_private(dev); 851 arm32_gtpci_chipset.pc_intr_v = device_private(dev); 852 853 io_bs_tag = prop_data_create_data_nocopy( 854 &orion_pci_io_bs_tag, sizeof(struct bus_space)); 855 KASSERT(io_bs_tag != NULL); 856 prop_dictionary_set(dict, "io-bus-tag", io_bs_tag); 857 prop_object_release(io_bs_tag); 858 mem_bs_tag = prop_data_create_data_nocopy( 859 &orion_pci_mem_bs_tag, sizeof(struct bus_space)); 860 KASSERT(mem_bs_tag != NULL); 861 prop_dictionary_set(dict, "mem-bus-tag", mem_bs_tag); 862 prop_object_release(mem_bs_tag); 863 864 pc = prop_data_create_data_nocopy(&arm32_gtpci_chipset, 865 sizeof(struct arm32_pci_chipset)); 866 KASSERT(pc != NULL); 867 prop_dictionary_set(dict, "pci-chipset", pc); 868 prop_object_release(pc); 869 870 marvell_startend_by_tag(ORION_TAG_PCI_IO, &start, &end); 871 prop_dictionary_set_uint64(dict, "iostart", start); 872 prop_dictionary_set_uint64(dict, "ioend", end); 873 marvell_startend_by_tag(ORION_TAG_PCI_MEM, &start, &end); 874 prop_dictionary_set_uint64(dict, "memstart", start); 875 prop_dictionary_set_uint64(dict, "memend", end); 876 prop_dictionary_set_uint32(dict, 877 "cache-line-size", arm_dcache_align); 878 879 /* Setup the hint for interrupt-pin. */ 880#define BDSTR(s) _BDSTR(s) 881#define _BDSTR(s) #s 882#define THIS_BOARD(str) (strcmp(str, BDSTR(EVBARM_BOARDTYPE)) == 0) 883 for (i = 0; hints[i].boardtype != NULL; i++) 884 if (THIS_BOARD(hints[i].boardtype)) 885 break; 886 if (hints[i].boardtype == NULL) 887 return; 888 889 int2gpp = 890 prop_array_create_with_capacity(PCI_INTERRUPT_PIN_MAX + 1); 891 892 /* first set dummy */ 893 gpp = prop_number_create_integer(0); 894 prop_array_add(int2gpp, gpp); 895 prop_object_release(gpp); 896 897 for (j = 0; hints[i].pin[j] != PCI_INTERRUPT_PIN_NONE; j++) { 898 gpp = prop_number_create_integer(hints[i].pin[j]); 899 prop_array_add(int2gpp, gpp); 900 prop_object_release(gpp); 901 } 902 prop_dictionary_set(dict, "int2gpp", int2gpp); 903 } 904#endif /* NGTPCI > 0 && defined(ORION) */ 905#if NMVPEX > 0 906 if (device_is_a(dev, "mvpex")) { 907#ifdef ORION 908 extern struct bus_space 909 orion_pex0_io_bs_tag, orion_pex0_mem_bs_tag, 910 orion_pex1_io_bs_tag, orion_pex1_mem_bs_tag; 911#endif 912#ifdef KIRKWOOD 913 extern struct bus_space 914 kirkwood_pex_io_bs_tag, kirkwood_pex_mem_bs_tag; 915#endif 916 extern struct arm32_pci_chipset arm32_mvpex0_chipset; 917#ifdef ORION 918 extern struct arm32_pci_chipset arm32_mvpex1_chipset; 919#endif 920 921#ifdef ORION 922 struct marvell_attach_args *mva = aux; 923#endif 924 struct bus_space *mvpex_io_bs_tag, *mvpex_mem_bs_tag; 925 struct arm32_pci_chipset *arm32_mvpex_chipset; 926 prop_data_t io_bs_tag, mem_bs_tag, pc; 927 uint64_t start, end; 928 int iotag, memtag; 929 930 switch (mvsoc_model()) { 931#ifdef ORION 932 case MARVELL_ORION_1_88F5180N: 933 case MARVELL_ORION_1_88F5181: 934 case MARVELL_ORION_1_88F5182: 935 case MARVELL_ORION_1_88W8660: 936 case MARVELL_ORION_2_88F5281: 937 if (mva->mva_offset == MVSOC_PEX_BASE) { 938 mvpex_io_bs_tag = &orion_pex0_io_bs_tag; 939 mvpex_mem_bs_tag = &orion_pex0_mem_bs_tag; 940 arm32_mvpex_chipset = &arm32_mvpex0_chipset; 941 iotag = ORION_TAG_PEX0_IO; 942 memtag = ORION_TAG_PEX0_MEM; 943 } else { 944 mvpex_io_bs_tag = &orion_pex1_io_bs_tag; 945 mvpex_mem_bs_tag = &orion_pex1_mem_bs_tag; 946 arm32_mvpex_chipset = &arm32_mvpex1_chipset; 947 iotag = ORION_TAG_PEX1_IO; 948 memtag = ORION_TAG_PEX1_MEM; 949 } 950 break; 951#endif 952 953#ifdef KIRKWOOD 954 case MARVELL_KIRKWOOD_88F6180: 955 case MARVELL_KIRKWOOD_88F6192: 956 case MARVELL_KIRKWOOD_88F6281: 957 mvpex_io_bs_tag = &kirkwood_pex_io_bs_tag; 958 mvpex_mem_bs_tag = &kirkwood_pex_mem_bs_tag; 959 arm32_mvpex_chipset = &arm32_mvpex0_chipset; 960 iotag = KIRKWOOD_TAG_PEX_IO; 961 memtag = KIRKWOOD_TAG_PEX_MEM; 962 break; 963#endif 964 965 default: 966 return; 967 } 968 969 arm32_mvpex_chipset->pc_conf_v = device_private(dev); 970 arm32_mvpex_chipset->pc_intr_v = device_private(dev); 971 972 io_bs_tag = prop_data_create_data_nocopy( 973 mvpex_io_bs_tag, sizeof(struct bus_space)); 974 KASSERT(io_bs_tag != NULL); 975 prop_dictionary_set(dict, "io-bus-tag", io_bs_tag); 976 prop_object_release(io_bs_tag); 977 mem_bs_tag = prop_data_create_data_nocopy( 978 mvpex_mem_bs_tag, sizeof(struct bus_space)); 979 KASSERT(mem_bs_tag != NULL); 980 prop_dictionary_set(dict, "mem-bus-tag", mem_bs_tag); 981 prop_object_release(mem_bs_tag); 982 983 pc = prop_data_create_data_nocopy(arm32_mvpex_chipset, 984 sizeof(struct arm32_pci_chipset)); 985 KASSERT(pc != NULL); 986 prop_dictionary_set(dict, "pci-chipset", pc); 987 prop_object_release(pc); 988 989 marvell_startend_by_tag(iotag, &start, &end); 990 prop_dictionary_set_uint64(dict, "iostart", start); 991 prop_dictionary_set_uint64(dict, "ioend", end); 992 marvell_startend_by_tag(memtag, &start, &end); 993 prop_dictionary_set_uint64(dict, "memstart", start); 994 prop_dictionary_set_uint64(dict, "memend", end); 995 prop_dictionary_set_uint32(dict, 996 "cache-line-size", arm_dcache_align); 997 } 998#endif 999} 1000 1001#if NGTPCI > 0 || NMVPEX > 0 1002static void 1003marvell_startend_by_tag(int tag, uint64_t *start, uint64_t *end) 1004{ 1005 uint32_t base, size; 1006 int win; 1007 1008 win = mvsoc_target(tag, NULL, NULL, &base, &size); 1009 if (size != 0) { 1010 if (win < nremap) 1011 *start = read_mlmbreg(MVSOC_MLMB_WRLR(win)) | 1012 ((read_mlmbreg(MVSOC_MLMB_WRHR(win)) << 16) << 16); 1013 else 1014 *start = base; 1015 *end = *start + size - 1; 1016 } 1017} 1018#endif 1019