1#include <ctype.h> 2#include <string.h> 3#include <stdlib.h> 4#include <mach-o/ppc/reloc.h> 5#include "ppc-opcode.h" 6#include "as.h" 7#include "flonum.h" 8#include "expr.h" 9#include "hash.h" 10#include "read.h" 11#include "md.h" 12#include "obstack.h" 13#include "symbols.h" 14#include "messages.h" 15#include "atof-ieee.h" 16#include "input-scrub.h" 17#include "sections.h" 18#include "dwarf2dbg.h" 19 20/* 21 * The assembler can assemble the trailing +/- by setting either the Y-bit or 22 * the AT-bits. The default is setting the Y-bit and is the same as specifying: 23 * -static_branch_prediction_Y_bit 24 * Treat a single trailing '+' or '-' after a conditional PowerPC branch 25 * instruction as a static branch prediction that sets the Y-bit in the 26 * opcode. Pairs of trailing "++" or "--" always set the AT-bits. This is 27 * the default for Mac OS X. 28 * This can be changed by specifying: 29 * -static_branch_prediction_AT_bits 30 * Treat a single trailing '+' or '-' after a conditional PowerPC branch 31 * instruction as a static branch prediction sets the AT-bits in the 32 * opcode. Pairs of trailing "++" or "--" always set the AT-bits but with 33 * this option a warning is issued if this syntax is used. With this flag 34 * the assembler behaves like the IBM tools. 35 */ 36enum static_branch_prediction { 37 STATIC_BRANCH_PREDICTION_Y_BIT, 38 STATIC_BRANCH_PREDICTION_AT_BITS 39}; 40static int static_branch_prediction_specified = 0; 41static enum static_branch_prediction static_branch_prediction = 42 STATIC_BRANCH_PREDICTION_Y_BIT; 43 44/* relocation type for internal assembler use only for LIKELY_{,NOT_}TAKEN */ 45#define PPC_RELOC_BR14_predicted (0x10 | PPC_RELOC_BR14) 46enum branch_prediction { 47 BRANCH_PREDICTION_NONE, 48 BRANCH_PREDICTION_LIKELY_TAKEN, 49 BRANCH_PREDICTION_LIKELY_NOT_TAKEN, 50 BRANCH_PREDICTION_VERY_LIKELY_TAKEN, 51 BRANCH_PREDICTION_VERY_LIKELY_NOT_TAKEN 52}; 53 54/* 55 * Set if -no_ppc601 is specified or .no_pcc601 is seen. It flags all 601 56 * uses as errors. 57 */ 58static int no_ppc601 = 0; 59 60/* 61 * The directive .flag_reg and .noflag_reg use these to flag register usage. 62 */ 63int flag_registers = 0; 64int flag_gregs[32] = { 0 }; 65 66/* 67 * These are the default cputype and cpusubtype for the ppc architecture. 68 */ 69#ifdef ARCH64 70const cpu_type_t md_cputype = CPU_TYPE_POWERPC64; 71cpu_subtype_t md_cpusubtype = CPU_SUBTYPE_POWERPC_ALL; 72#else 73const cpu_type_t md_cputype = CPU_TYPE_POWERPC; 74cpu_subtype_t md_cpusubtype = CPU_SUBTYPE_POWERPC_ALL; 75#endif 76 77/* This is the byte sex for the ppc architecture */ 78const enum byte_sex md_target_byte_sex = BIG_ENDIAN_BYTE_SEX; 79 80/* These characters start a comment anywhere on the line */ 81const char md_comment_chars[] = ";"; 82 83/* These characters only start a comment at the beginning of a line */ 84const char md_line_comment_chars[] = "#"; 85 86/* 87 * These characters can be used to separate mantissa decimal digits from 88 * exponent decimal digits in floating point numbers. 89 */ 90const char md_EXP_CHARS[] = "eE"; 91 92/* 93 * The characters after a leading 0 that means this number is a floating point 94 * constant as in 0f123.456 or 0d1.234E-12 (see md_EXP_CHARS above). 95 */ 96const char md_FLT_CHARS[] = "dDfF"; 97 98/* 99 * This is the machine dependent pseudo opcode table for this target machine. 100 */ 101static void s_reg( 102 uintptr_t reg); 103static void s_no_ppc601( 104 uintptr_t ignore); 105static void s_flag_reg( 106 uintptr_t ignore); 107static void s_noflag_reg( 108 uintptr_t ignore); 109const pseudo_typeS md_pseudo_table[] = 110{ 111 {"greg", s_reg, 'r' }, 112 {"no_ppc601", s_no_ppc601, 0 }, 113 {"flag_reg", s_flag_reg, 0 }, 114 {"noflag_reg", s_noflag_reg, 0 }, 115 {"file", (void (*) (uintptr_t)) dwarf2_directive_file, 0}, 116 {"loc", dwarf2_directive_loc, 0}, 117 {0} /* end of table marker */ 118}; 119 120#define RT(x) (((x) >> 21) & 0x1f) 121#define RA(x) (((x) >> 16) & 0x1f) 122#define RB(x) (((x) >> 11) & 0x1f) 123 124struct ppc_insn { 125 uint32_t opcode; 126 expressionS exp; 127 expressionS jbsr_exp; 128 int reloc; 129 int32_t pcrel; 130 int32_t pcrel_reloc; 131}; 132 133/* 134 * The pointer to the opcode hash table built by md_begin() and used by 135 * md_assemble() to look up opcodes. 136 */ 137static struct hash_control *op_hash = NULL; 138 139/* 140 * These aid in the printing of better error messages for parameter syntax 141 * errors when there is only one mnemonic in the tables. 142 */ 143static uint32_t error_param_count = 0; 144static char *error_param_message = NULL; 145 146/* 147 * These are name names of the known special registers and the numbers assigned 148 * to them. 149 */ 150struct special_register { 151 uint32_t number; 152 char *name; 153}; 154static const struct special_register special_registers[] = { 155 { 0, "mq" }, /* 601 only */ 156 { 1, "xer" }, /* user access */ 157 { 4, "rtcu" },/* real time counter high (601 only, not in PowerPC arch)*/ 158 { 5, "rtcl" },/* real time counter low (601 only, not in PowerPC arch) */ 159 { 8, "lr" }, /* user access */ 160 { 9, "ctr" }, /* user access */ 161 { 18, "dsisr" }, 162 { 19, "dar" }, 163 { 22, "dec" }, 164 { 25, "sdr1" }, 165 { 26, "srr0" }, 166 { 27, "srr1" }, 167 { 256, "VRsave" }, /* user access, VMX register save */ 168 { 272, "sprg0" }, 169 { 273, "sprg1" }, 170 { 274, "sprg2" }, 171 { 275, "sprg3" }, 172 { 280, "asr" }, /* 64-bit implementaions only */ 173 { 282, "ear" }, /* optional in the PowerPC architecure */ 174 { 284, "tbl" }, 175 { 285, "tbu" }, 176 { 287, "pvr" }, 177 { 528, "ibat0u" }, 178 { 529, "ibat0l" }, 179 { 530, "ibat1u" }, 180 { 531, "ibat1l" }, 181 { 532, "ibat2u" }, 182 { 533, "ibat2l" }, 183 { 534, "ibat3u" }, 184 { 535, "ibat3l" }, 185 { 536, "dbat0u" }, 186 { 537, "dbat0l" }, 187 { 538, "dbat1u" }, 188 { 539, "dbat1l" }, 189 { 540, "dbat2u" }, 190 { 541, "dbat2l" }, 191 { 542, "dbat3u" }, 192 { 543, "dbat3l" }, 193 { 936, "ummcr0" },/* 750 only */ 194 { 937, "upmc1" }, /* 750 only */ 195 { 938, "upmc2" }, /* 750 only */ 196 { 939, "usia" }, /* 750 only */ 197 { 940, "ummcr1" },/* 750 only */ 198 { 941, "upmc3" }, /* 750 only */ 199 { 942, "upmc4" }, /* 750 only */ 200 { 952, "mmcr0" }, /* 604, 604e, 750 only */ 201 { 953, "pmc1" }, /* 604, 604e & 750 only */ 202 { 954, "pmc2" }, /* 604, 604e & 750 only */ 203 { 955, "sia" }, /* 604, 604e & 750 only */ 204 { 956, "mmcr1" }, /* 604e & 750 only */ 205 { 957, "pmc3" }, /* 604e & 750 only */ 206 { 958, "pmc4" }, /* 604e & 750 only */ 207 { 959, "sda" }, /* 604 & 604e only */ 208 { 976, "dmiss" }, /* 603 only */ 209 { 977, "dcmp" }, /* 603 only */ 210 { 978, "hash1" }, /* 603 only */ 211 { 979, "hash2" }, /* 603 only */ 212 { 980, "imiss" }, /* 603 only */ 213 { 981, "icmp" }, /* 603 only */ 214 { 982, "rpa" }, /* 603 only */ 215 { 1008,"hid0" }, /* 601, 603, 603e, 604, 604e, 750 only */ 216 { 1009,"hid1" }, /* 601, 603e, 604e 750 only */ 217 { 1010,"hid2" }, /* 601 */ 218 { 1010,"iabr" }, /* 601, 603, 603e, 604, 604e & 750 only */ 219 { 1013,"hid5" }, /* 601 only */ 220 { 1013,"dabr" }, /* optional in the PowerPC architecure (604, 604e & 750) */ 221 { 1017,"l2cr" }, /* 750 only */ 222 { 1019,"ictc" }, /* 750 only */ 223 { 1020,"thrm1" },/* 750 only */ 224 { 1021,"thrm2" },/* 750 only */ 225 { 1022,"thrm3" },/* 750 only */ 226 { 1023,"hid15" }, /* 601 only */ 227 { 1023,"pir" }, /* 601, 604 & 604e only */ 228 { 0, "" } /* end of table marker */ 229}; 230 231/* 232 * These are name names of the condition field special registers and the 233 * numbers assigned to them. 234 */ 235struct condition_symbol { 236 uint32_t value; 237 char *name; 238}; 239static const struct condition_symbol condition_symbols[] = { 240 { 0, "lt" }, /* less than */ 241 { 1, "gt" }, /* greater than */ 242 { 2, "eq" }, /* equal */ 243 { 3, "so" }, /* summary overflow */ 244 { 3, "un" }, /* unordered */ 245 { 0, "" } /* end of table marker */ 246}; 247 248struct CR_field { 249 uint32_t value; 250 char *name; 251}; 252static const struct CR_field CR_fields[] = { 253 { 0, "cr0" }, /* CR field 0 */ 254 { 4, "cr1" }, /* CR field 1 */ 255 { 8, "cr2" }, /* CR field 2 */ 256 { 12, "cr3" }, /* CR field 3 */ 257 { 16, "cr4" }, /* CR field 4 */ 258 { 20, "cr5" }, /* CR field 5 */ 259 { 24, "cr6" }, /* CR field 6 */ 260 { 28, "cr7" }, /* CR field 7 */ 261 { 0, "" } /* end of table marker */ 262}; 263 264/* 265 * These are built in macros because they are trivial to implement as macros 266 * which otherwise be less obvious to do special entries for them. 267 */ 268struct macros { 269 char *name; 270 char *body; 271}; 272static const struct macros ppc_macros[] = { 273 { "mr\n", "or $0,$1,$1\n" }, 274 { "mr.\n", "or. $0,$1,$1\n" }, 275 { "not\n", "nor $0,$1,$1\n" }, 276 { "not.\n", "nor. $0,$1,$1\n" }, 277 { "extldi\n", "rldicr $0,$1,$3,($2)-1\n" }, 278 { "extldi.\n", "rldicr. $0,$1,$3,($2)-1\n" }, 279 { "extrdi\n", "rldicl $0,$1,($2)+($3),64-($2)\n" }, 280 { "extrdi.\n", "rldicl. $0,$1,($2)+($3),64-($2)\n" }, 281 { "insrdi\n", "rldimi $0,$1,64-(($3)+($2)),$3\n" }, 282 { "insrdi.\n", "rldimi. $0,$1,64-(($3)+($2)),$3\n" }, 283 { "rotldi\n", "rldicl $0,$1,$2,0\n" }, 284 { "rotldi.\n", "rldicl. $0,$1,$2,0\n" }, 285 { "rotrdi\n", "rldicl $0,$1,64-($2),0\n" }, 286 { "rotrdi.\n", "rldicl. $0,$1,64-($2),0\n" }, 287 { "rotld\n", "rldcl $0,$1,$2,0\n" }, 288 { "rotld.\n", "rldcl. $0,$1,$2,0\n" }, 289 { "sldi\n", "rldicr $0,$1,$2,63-($2)\n" }, 290 { "sldi.\n", "rldicr. $0,$1,$2,63-($2)\n" }, 291 { "srdi\n", "rldicl $0,$1,64-($2),$2\n" }, 292 { "srdi.\n", "rldicl. $0,$1,64-($2),$2\n" }, 293 { "clrldi\n", "rldicl $0,$1,0,$2\n" }, 294 { "clrldi.\n", "rldicl. $0,$1,0,$2\n" }, 295 { "clrrdi\n", "rldicr $0,$1,0,63-($2)\n" }, 296 { "clrrdi.\n", "rldicr. $0,$1,0,63-($2)\n" }, 297 { "clrlsldi\n","rldic $0,$1,$3,($2)-($3)\n" }, 298 { "clrlsldi.\n","rldic. $0,$1,$3,($2)-($3)\n" }, 299 300 { "extlwi\n", "rlwinm $0,$1,$3,0,($2)-1\n" }, 301 { "extlwi.\n", "rlwinm. $0,$1,$3,0,($2)-1\n" }, 302 { "extrwi\n", "rlwinm $0,$1,($2)+($3),32-($2),31\n" }, 303 { "extrwi.\n", "rlwinm. $0,$1,($2)+($3),32-($2),31\n" }, 304 { "inslwi\n", "rlwimi $0,$1,32-($3),$3,(($3)+($2))-1\n" }, 305 { "inslwi.\n", "rlwimi. $0,$1,32-($3),$3,(($3)+($2))-1\n" }, 306 { "insrwi\n", "rlwimi $0,$1,32-(($3)+($2)),$3,(($3)+($2))-1\n" }, 307 { "insrwi.\n", "rlwimi. $0,$1,32-(($3)+($2)),$3,(($3)+($2))-1\n" }, 308 { "rotlwi\n", "rlwinm $0,$1,$2,0,31\n" }, 309 { "rotlwi.\n", "rlwinm. $0,$1,$2,0,31\n" }, 310 { "rotrwi\n", "rlwinm $0,$1,32-($2),0,31\n" }, 311 { "rotrwi.\n", "rlwinm. $0,$1,32-($2),0,31\n" }, 312 { "rotlw\n", "rlwnm $0,$1,$2,0,31\n" }, 313 { "rotlw.\n", "rlwnm. $0,$1,$2,0,31\n" }, 314 { "slwi\n", "rlwinm $0,$1,$2,0,31-($2)\n" }, 315 { "slwi.\n", "rlwinm. $0,$1,$2,0,31-($2)\n" }, 316 { "srwi\n", "rlwinm $0,$1,32-($2),$2,31\n" }, 317 { "srwi.\n", "rlwinm. $0,$1,32-($2),$2,31\n" }, 318 { "clrlwi\n", "rlwinm $0,$1,0,$2,31\n" }, 319 { "clrlwi.\n", "rlwinm. $0,$1,0,$2,31\n" }, 320 { "clrrwi\n", "rlwinm $0,$1,0,0,31-($2)\n" }, 321 { "clrrwi.\n", "rlwinm. $0,$1,0,0,31-($2)\n" }, 322 { "clrlslwi\n","rlwinm $0,$1,$3,($2)-($3),31-($3)\n" }, 323 { "clrlslwi.\n","rlwinm. $0,$1,$3,($2)-($3),31-($3)\n" }, 324 325 { "mtxer\n", "mtspr 1,$0\n"}, 326 { "mfxer\n", "mfspr $0,1\n"}, 327 { "mtlr\n", "mtspr 8,$0\n"}, 328 { "mflr\n", "mfspr $0,8\n"}, 329 { "mtctr\n", "mtspr 9,$0\n"}, 330 { "mfctr\n", "mfspr $0,9\n"}, 331 { "mtdsisr\n", "mtspr 18,$0\n"}, 332 { "mfdsisr\n", "mfspr $0,18\n"}, 333 { "mtdar\n", "mtspr 19,$0\n"}, 334 { "mfdar\n", "mfspr $0,19\n"}, 335 { "mtdec\n", "mtspr 22,$0\n"}, 336 { "mfdec\n", "mfspr $0,22\n"}, 337 { "mtsdr1\n", "mtspr 25,$0\n"}, 338 { "mfsdr1\n", "mfspr $0,25\n"}, 339 { "mtsrr0\n", "mtspr 26,$0\n"}, 340 { "mfsrr0\n", "mfspr $0,26\n"}, 341 { "mtsrr1\n", "mtspr 27,$0\n"}, 342 { "mfsrr1\n", "mfspr $0,27\n"}, 343 { "mtsprg\n", "mtspr 272+($0),$1\n"}, 344 { "mfsprg\n", "mfspr $0,272+($1)\n"}, 345 { "mtasr\n", "mtspr 280,$0\n"}, 346 { "mfasr\n", "mfspr $0,280\n"}, 347 { "mfear\n", "mfspr $0,282\n"}, 348 { "mtear\n", "mtspr 282,$0\n"}, 349 { "mfpvr\n", "mfspr $0,287\n"}, 350 { "mtvrsave\n","mtspr 256,$0\n"}, 351 { "mtibatu\n", "mtspr 528+2*($0),$1\n"}, 352 { "mfibatu\n", "mfspr $0,528+2*($1)\n"}, 353 { "mtibatl\n", "mtspr 529+2*($0),$1\n"}, 354 { "mfibatl\n", "mfspr $0,529+2*($1)\n"}, 355 { "mtdbatu\n", "mtspr 536+2*($0),$1\n"}, 356 { "mfdbatu\n", "mfspr $0,536+2*($1)\n"}, 357 { "mtdbatl\n", "mtspr 537+2*($0),$1\n"}, 358 { "mfdbatl\n", "mfspr $0,537+2*($1)\n"}, 359 360 { "subi\n", "addi $0,$1,-($2)\n"}, 361 { "subis\n", "addis $0,$1,-($2)\n"}, 362 { "subic\n", "addic $0,$1,-($2)\n"}, 363 { "subic.\n", "addic. $0,$1,-($2)\n"}, 364 365 { "crclr\n", "crxor $0,$0,$0\n"}, 366 { "crmove\n", "cror $0,$1,$1\n"}, 367 { "crnot\n", "crnor $0,$1,$1\n"}, 368 { "crset\n", "creqv $0,$0,$0\n"}, 369 { "mtcr\n", "mtcrf 0xff,$0\n"}, 370 { "mtfs\n", "mtfsf 0xff,$0\n"}, 371 { "mtfs.\n", "mtfsf. 0xff,$0\n"}, 372 373 { "vmr\n", "vor $0,$1,$1\n"}, 374 { "vnot\n", "vnor $0,$1,$1\n"}, 375 376 { "", "" } /* end of table marker */ 377}; 378 379static int calcop( 380 struct ppc_opcode *format, 381 char *param, 382 struct ppc_insn *insn, 383 char *op, 384 enum branch_prediction prediction); 385static char *parse_jbsr( 386 char *param, 387 struct ppc_insn *insn, 388 struct ppc_opcode *format, 389 int parcnt); 390static char *parse_branch( 391 char *param, 392 struct ppc_insn *insn, 393 struct ppc_opcode *format, 394 int parcnt); 395static char *parse_displacement( 396 char *param, 397 struct ppc_insn *insn, 398 struct ppc_opcode *format, 399 int parcnt); 400static char *parse_immediate( 401 char *param, 402 struct ppc_insn *insn, 403 struct ppc_opcode *format, 404 int parcnt); 405static char *parse_reg( 406 char *reg_name, 407 char *param, 408 struct ppc_insn *insn, 409 struct ppc_opcode *format, 410 uint32_t parcnt); 411static char *parse_spreg( 412 char *param, 413 struct ppc_insn *insn, 414 struct ppc_opcode *format, 415 uint32_t parcnt); 416static char *parse_bcnd( 417 char *param, 418 struct ppc_insn *insn, 419 struct ppc_opcode *format, 420 uint32_t parcnt); 421static char *parse_crf( 422 char *param, 423 struct ppc_insn *insn, 424 struct ppc_opcode *format, 425 uint32_t parcnt); 426static char *parse_num( 427 char *param, 428 struct ppc_insn *insn, 429 struct ppc_opcode *format, 430 uint32_t parcnt, 431 int32_t max_width_zero, 432 int32_t zero_only, 433 int32_t signed_num, 434 int32_t bit_mask_with_1_bit_set); 435static char *parse_mbe( 436 char *param, 437 struct ppc_insn *insn, 438 struct ppc_opcode *format, 439 uint32_t parcnt); 440static char *parse_sh( 441 char *param, 442 struct ppc_insn *insn, 443 struct ppc_opcode *format, 444 uint32_t parcnt); 445static char *parse_mb( 446 char *param, 447 struct ppc_insn *insn, 448 struct ppc_opcode *format, 449 uint32_t parcnt); 450 451/* 452 * md_begin() is called from main() in as.c before assembly begins. It is used 453 * to allow target machine dependent initialization. 454 */ 455void 456md_begin(void) 457{ 458 uint32_t i; 459 char *name; 460 const char *retval; 461 462 /* initialize the opcode hash table */ 463 op_hash = hash_new(); 464 if(op_hash == NULL) 465 as_fatal("Could not initialize the opcode hash table"); 466 467 /* loop until you see the end of the list */ 468 i = 0; 469 while(*ppc_opcodes[i].name){ 470 name = ppc_opcodes[i].name; 471 472 /* hash each mnemonic and record its position */ 473 retval = hash_insert(op_hash, name, (char *)&ppc_opcodes[i]); 474 if(retval != NULL && *retval != '\0') 475 as_fatal("Can't hash instruction '%s':%s", 476 ppc_opcodes[i].name, retval); 477 478 /* skip to next unique mnemonic or end of list */ 479 for(i++; strcmp(ppc_opcodes[i].name, name) == 0; i++) 480 ; 481 } 482 483 /* 484 * Load the builtin macros for extended mnemonics for rotate and 485 * shift mnemonics. 486 */ 487 for(i = 0; *ppc_macros[i].name != '\0'; i++){ 488 input_line_pointer = ppc_macros[i].name; 489 s_macro(0); 490 add_to_macro_definition(ppc_macros[i].body); 491 s_endmacro(0); 492 } 493} 494 495/* 496 * md_end() is called from main() in as.c after assembly ends. It is used 497 * to allow target machine dependent clean up. 498 */ 499void 500md_end(void) 501{ 502} 503 504/* 505 * md_parse_option() is called from main() in as.c to parse target machine 506 * dependent command line options. This routine returns 0 if it is passed an 507 * option that is not recognized non-zero otherwise. 508 */ 509int 510md_parse_option( 511char **argP, 512int *cntP, 513char ***vecP) 514{ 515 switch(**argP) { 516 case 'n': 517 if(strcmp(*argP, "no_ppc601") == 0){ 518 no_ppc601 = 1; 519 *argP = ""; 520 return(1); 521 } 522 break; 523 case 'p': 524 if(strcmp(*argP, "ppcasm") == 0){ 525 *argP = ""; 526 return(1); 527 } 528 break; 529 case 's': 530 if(strcmp(*argP, "static_branch_prediction_Y_bit") == 0){ 531 if(static_branch_prediction_specified && 532 static_branch_prediction != STATIC_BRANCH_PREDICTION_Y_BIT) 533 as_bad("Can't specify both -static_branch_prediction_Y_bit" 534 " and -static_branch_prediction_AT_bits"); 535 static_branch_prediction_specified = 1; 536 static_branch_prediction = STATIC_BRANCH_PREDICTION_Y_BIT; 537 *argP = ""; 538 return(1); 539 } 540 else if(strcmp(*argP, "static_branch_prediction_AT_bits") == 0){ 541 if(static_branch_prediction_specified && 542 static_branch_prediction != STATIC_BRANCH_PREDICTION_AT_BITS) 543 as_bad("Can't specify both -static_branch_prediction_Y_bit" 544 " and -static_branch_prediction_AT_bits"); 545 static_branch_prediction_specified = 1; 546 static_branch_prediction = STATIC_BRANCH_PREDICTION_AT_BITS; 547 *argP = ""; 548 return(1); 549 } 550 break; 551 } 552 return(0); 553} 554 555/* 556 * s_reg() is used to implement ".greg symbol,exp" which sets symbol to 1 or 0 557 * depending on if the expression is a general register. This is intended for 558 * use in macros. 559 */ 560static 561void 562s_reg( 563uintptr_t reg) 564{ 565 char *name, *end_name, delim; 566 symbolS *symbolP; 567 uint32_t n_value, val; 568 569 if( * input_line_pointer == '"') 570 name = input_line_pointer + 1; 571 else 572 name = input_line_pointer; 573 delim = get_symbol_end(); 574 end_name = input_line_pointer; 575 *end_name = delim; 576 SKIP_WHITESPACE(); 577 if ( * input_line_pointer != ',' ) { 578 *end_name = 0; 579 as_bad("Expected comma after name \"%s\"", name); 580 *end_name = delim; 581 ignore_rest_of_line(); 582 return; 583 } 584 input_line_pointer ++; 585 *end_name = 0; 586 587 SKIP_WHITESPACE(); 588 n_value = 0; 589 if (*input_line_pointer == reg || *input_line_pointer == toupper(reg)){ 590 input_line_pointer++; 591 if(isdigit(*input_line_pointer)){ 592 val = 0; 593 while (isdigit(*input_line_pointer)){ 594 if ((val = val * 10 + *input_line_pointer++ - '0') > 31) 595 break; 596 } 597 SKIP_WHITESPACE(); 598 if(val <= 31 && 599 (*input_line_pointer == '\n' || *input_line_pointer == '@')) 600 n_value = 1; 601 } 602 } 603 604 symbolP = symbol_find_or_make (name); 605 symbolP -> sy_type = N_ABS; 606 symbolP -> sy_other = 0; /* NO_SECT */ 607 symbolP -> sy_value = n_value; 608 symbolP -> sy_frag = & zero_address_frag; 609 610 *end_name = delim; 611 totally_ignore_line(); 612} 613 614/* 615 * s_no_ppc601() inplements .no_ppc601 which causes 601 instructions to be 616 * flagged as errors. This is the same as if -no_ppc601 is specified. 617 */ 618static 619void 620s_no_ppc601( 621uintptr_t ignore) 622{ 623 no_ppc601 = 1; 624 totally_ignore_line(); 625} 626 627/* 628 * s_flag_reg() implements .flag_reg <reg_number> so that uses of that register 629 * get flagged as warnings. 630 */ 631static 632void 633s_flag_reg( 634uintptr_t ignore) 635{ 636 int reg; 637 638 reg = get_absolute_expression(); 639 if(reg < 0 || reg >= 32) 640 as_bad("register number (%d) out of range (0-31) for .flag_reg", 641 reg); 642 demand_empty_rest_of_line(); 643 flag_registers = 1; 644 flag_gregs[reg] = 1; 645} 646 647/* 648 * s_noflag_reg() implements .noflag_reg <reg_number> so that uses of that 649 * register no longer get flagged as warnings. 650 */ 651static 652void 653s_noflag_reg( 654uintptr_t ignore) 655{ 656 int i, reg; 657 658 reg = get_absolute_expression(); 659 if(reg < 0 || reg >= 32) 660 as_bad("register number (%d) out of range (0-31) for .noflag_reg", 661 reg); 662 demand_empty_rest_of_line(); 663 flag_gregs[reg] = 0; 664 flag_registers = 0; 665 for(i = 0; i < 32; i++){ 666 if(flag_gregs[i]){ 667 flag_registers = 1; 668 return; 669 } 670 } 671} 672 673/* 674 * md_assemble() is passed a pointer to a string that should be a assembly 675 * statement for the target machine. 676 */ 677void 678md_assemble( 679char *op) 680{ 681 char *param, *thisfrag, *start_op, *end_op; 682 enum branch_prediction prediction; 683 struct ppc_opcode *format; 684 struct ppc_insn insn; 685 uint32_t i, val, retry; 686 687 static char *file_spec; 688 static uint32_t line_spec; 689 static int syntax_warning_issued_for_AT_bits = 0; 690 691 /* 692 * Pick up the instruction and any trailing branch prediction character 693 * (a trailing '+', '-' on the instruction). 694 */ 695 prediction = BRANCH_PREDICTION_NONE; 696 start_op = op; 697 end_op = op; 698 for(param = op; !isspace(*param) && *param != '\0' ; param++) 699 end_op = param; 700 if(*end_op == '+'){ 701 if(end_op != start_op && end_op[-1] == '+'){ 702 if(static_branch_prediction == 703 STATIC_BRANCH_PREDICTION_AT_BITS && 704 syntax_warning_issued_for_AT_bits == 0){ 705 as_warn("branch prediction ++/-- syntax always sets the " 706 "AT-bits"); 707 syntax_warning_issued_for_AT_bits = 1; 708 } 709 prediction = BRANCH_PREDICTION_VERY_LIKELY_TAKEN; 710 end_op[-1] = '\0'; 711 } 712 else{ 713 if(static_branch_prediction == STATIC_BRANCH_PREDICTION_AT_BITS) 714 prediction = BRANCH_PREDICTION_VERY_LIKELY_TAKEN; 715 else 716 prediction = BRANCH_PREDICTION_LIKELY_TAKEN; 717 *end_op = '\0'; 718 } 719 } 720 else if(*end_op == '-'){ 721 if(end_op != start_op && end_op[-1] == '-'){ 722 if(static_branch_prediction == 723 STATIC_BRANCH_PREDICTION_AT_BITS && 724 syntax_warning_issued_for_AT_bits == 0){ 725 as_warn("branch prediction ++/-- syntax always sets the " 726 "AT-bits"); 727 syntax_warning_issued_for_AT_bits = 1; 728 } 729 prediction = BRANCH_PREDICTION_VERY_LIKELY_NOT_TAKEN; 730 end_op[-1] = '\0'; 731 } 732 else{ 733 if(static_branch_prediction == STATIC_BRANCH_PREDICTION_AT_BITS) 734 prediction = BRANCH_PREDICTION_VERY_LIKELY_NOT_TAKEN; 735 else 736 prediction = BRANCH_PREDICTION_LIKELY_NOT_TAKEN; 737 *end_op = '\0'; 738 } 739 } 740 if(*param != '\0') 741 *param++ = '\0'; 742 743 /* try to find the instruction in the hash table */ 744 if((format = (struct ppc_opcode *)hash_find(op_hash, op)) == NULL){ 745 as_bad("Invalid mnemonic '%s'", op); 746 return; 747 } 748 749 /* try parsing this instruction into insn */ 750 retry = 0; 751 error_param_count = 0; 752 error_param_message = NULL; 753 while(calcop(format, param, &insn, op, prediction) == 0){ 754 /* if it doesn't parse try the next instruction */ 755 if(strcmp(format->name, format[1].name) == 0){ 756 format++; 757 retry = 1; 758 } 759 else{ 760 if(retry == 0){ 761 if(error_param_message != NULL) 762 as_bad("%s (parameter %u)", error_param_message, 763 error_param_count + 1); 764 else 765 as_bad("Parameter syntax error (parameter %u)", 766 error_param_count + 1); 767 } 768 else 769 as_bad("Parameter syntax error"); 770 return; 771 } 772 } 773 774#ifndef ALLOW_INVALID_FORMS 775 /* 776 * Check for invalid forms of instructions. For the following 777 * instructions: lbzu, lbzux, lhzu, lhzux, lhau, lhaux, lwzu, lwzux, 778 * lwaux, ldu, ldux 779 * if RA == 0 or RA == RT the instruction form is invalid. 780 */ 781 if((insn.opcode & 0xfc000000) == 0x8c000000 || /* lbzu */ 782 (insn.opcode & 0xfc0007fe) == 0x7c0000ee || /* lbzux */ 783 (insn.opcode & 0xfc000000) == 0xa4000000 || /* lhzu */ 784 (insn.opcode & 0xfc0007fe) == 0x7c00026e || /* lbzux */ 785 (insn.opcode & 0xfc000000) == 0xac000000 || /* lhau */ 786 (insn.opcode & 0xfc0007fe) == 0x7c0002ee || /* lhaux */ 787 (insn.opcode & 0xfc000000) == 0x84000000 || /* lwzu */ 788 (insn.opcode & 0xfc0007fe) == 0x7c00006e || /* lwzux */ 789 (insn.opcode & 0xfc0007fe) == 0x7c0002ea || /* lwaux */ 790 (insn.opcode & 0xfc000003) == 0xe8000001 || /* ldu */ 791 (insn.opcode & 0xfc0007fe) == 0x7c00006a){ /* ldux */ 792 if(RA(insn.opcode) == 0) 793 as_bad("Invalid form of the instruction (RA must not be 0)"); 794 if(RA(insn.opcode) == RT(insn.opcode)) 795 as_bad("Invalid form of the instruction (RA must not the same " 796 "as RT)"); 797 } 798 /* 799 * For the following instructions: stbu, stbux, sthu, sthux, stwu, 800 * stwux, stdu, stdux, lfsu, lfsux, lfdu, lfdux, stfsu, stfsux, stfdu, 801 * stfdux 802 * if RA == 0 the instruction form is invalid. 803 */ 804 if((insn.opcode & 0xfc000000) == 0x9c000000 || /* stbu */ 805 (insn.opcode & 0xfc0007fe) == 0x7c0001ee || /* stbux */ 806 (insn.opcode & 0xfc000000) == 0xb4000000 || /* sthu */ 807 (insn.opcode & 0xfc0007fe) == 0x7c00036e || /* sthux */ 808 (insn.opcode & 0xfc000000) == 0x94000000 || /* stwu */ 809 (insn.opcode & 0xfc0007fe) == 0x7c00016e || /* stwux */ 810 (insn.opcode & 0xfc000003) == 0xf8000001 || /* stdu */ 811 (insn.opcode & 0xfc0007fe) == 0x7c00016a || /* stdux */ 812 (insn.opcode & 0xfc000000) == 0xc4000000 || /* lfsu */ 813 (insn.opcode & 0xfc0007fe) == 0x7c00046e || /* lfsux */ 814 (insn.opcode & 0xfc000000) == 0xcc000000 || /* lfdu */ 815 (insn.opcode & 0xfc0007fe) == 0x7c0004ee || /* lfdux */ 816 (insn.opcode & 0xfc000000) == 0xd4000000 || /* stfsu */ 817 (insn.opcode & 0xfc0007fe) == 0x7c00056e || /* stfsux */ 818 (insn.opcode & 0xfc000000) == 0xdc000000 || /* stfdu */ 819 (insn.opcode & 0xfc0007fe) == 0x7c0005ee || /* stfdux */ 820 (insn.opcode & 0xfc0007fe) == 0x7c0002ac || /* dst, dstt */ 821 (insn.opcode & 0xfc0007fe) == 0x7c0002ec){ /* dstst, dststt */ 822 if(RA(insn.opcode) == 0) 823 as_bad("Invalid form of the instruction (RA must not be 0)"); 824 } 825 /* 826 * For the following instruction lmw if RA is in the range of 827 * registers to be loaded or RT == RA == 0 the instruction form is 828 * invalid. 829 */ 830 if((insn.opcode & 0xfc000000) == 0xb8000000){ /* lmw */ 831 if(RT(insn.opcode) <= RA(insn.opcode)) 832 as_bad("Invalid form of the instruction (RA is in the range " 833 "of registers to be loaded)"); 834 } 835 /* 836 * For the lswi instruction if RA is in the range of registers to be 837 * loaded the instruction form is invalid. 838 */ 839 if((insn.opcode & 0xfc0007fe) == 0x7c0004aa){ /* lswi */ 840 uint32_t nb, nr; 841 842 nb = (insn.opcode & 0x0000f800) >> 11; 843 if(nb == 0) 844 nb = 32; 845 nr = (nb + 3) / 4; 846 if(RA(insn.opcode) >= RT(insn.opcode) && 847 RA(insn.opcode) <= RT(insn.opcode) + nr - 1) 848 as_bad("Invalid form of the instruction (RA is in the " 849 "range of registers to be loaded)"); 850 if(RT(insn.opcode) + nr - 1 > 31 && 851 RA(insn.opcode) < (RT(insn.opcode) + nr - 1) - 31) 852 as_bad("Invalid form of the instruction (RA is in the " 853 "range of registers to be loaded)"); 854 } 855 /* 856 * For the lswx instruction if RT == RA or RT == RB the instruction 857 * form is invalid. Of if RT and RA both specifiy r0 the form is 858 * invalid (covered by the RT == RA case). 859 */ 860 if((insn.opcode & 0xfc0007fe) == 0x7c00042a){ /* lswx */ 861 if(RT(insn.opcode) == RA(insn.opcode)) 862 as_bad("Invalid form of the instruction (RT must not the same " 863 "as RA)"); 864 if(RT(insn.opcode) == RB(insn.opcode)) 865 as_bad("Invalid form of the instruction (RT must not the same " 866 "as RB)"); 867 } 868#if !defined(ARCH64) 869 /* 870 * The 64-bit compares are invalid on 32-bit implementations. Since 871 * we don't expect to ever use the 620 all 64-bit instructions require 872 * the -force_cpusubtype_ALL option to not be flagged as invalid. 873 */ 874 if(((insn.opcode & 0xfc4007ff) == 0x7c000000 || /* cmp */ 875 (insn.opcode & 0xfc4007ff) == 0x7c000040 || /* cmpl */ 876 (insn.opcode & 0xfc400000) == 0x2c000000 || /* cmpi */ 877 (insn.opcode & 0xfc400000) == 0x28000000) && /* cmpli */ 878 (insn.opcode & 0x00200000) == 0x00200000 && /* the L bit */ 879 !force_cpusubtype_ALL && 880 archflag_cpusubtype != CPU_SUBTYPE_POWERPC_970){ 881 as_bad("Invalid form of the instruction (64-bit compares not " 882 "allowed without -force_cpusubtype_ALL option)"); 883 } 884#endif /* !defined(ARCH64) */ 885 /* 886 * For branch conditional instructions certian BO fields are reserved. 887 * These are flagged as invalid forms unless the -force_cpusubtype_ALL 888 * option is specified. 889 */ 890 if(((insn.opcode & 0xfc000000) == 0x40000000 || /* bc */ 891 (insn.opcode & 0xfc00fffe) == 0x4c000420 || /* bcctr */ 892 (insn.opcode & 0xfc00fffe) == 0x4c000020) && /* bclr */ 893 !force_cpusubtype_ALL){ 894 /* 895 * We have a branch conditional instruction and force_cpusubtype_ALL 896 * is not specified. So check for reserved BO fields where the z 897 * bits should be zero. 898 */ 899 if((insn.opcode & 0x02800000) == 0x02800000 && /* 1z1zz */ 900 (insn.opcode & 0x01600000) != 0x00000000){ 901 as_bad("Invalid form of the instruction (reserved bits in the " 902 "BO field must be zero without -force_cpusubtype_ALL " 903 "option)"); 904 } 905 } 906#endif /* ALLOW_INVALID_FORMS */ 907 908 /* 909 * If the -g flag is present generate a line number stab for the 910 * instruction. 911 * 912 * See the detailed comments about stabs in read_a_source_file() for a 913 * description of what is going on here. 914 */ 915 if(flagseen['g'] && frchain_now->frch_nsect == text_nsect){ 916 (void)symbol_new( 917 "", 918 68 /* N_SLINE */, 919 text_nsect, 920 logical_input_line /* n_desc, line number */, 921 obstack_next_free(&frags) - frag_now->fr_literal, 922 frag_now); 923 } 924 925 /* grow the current frag and plop in the opcode */ 926 thisfrag = frag_more(4); 927 md_number_to_chars(thisfrag, insn.opcode, 4); 928 dwarf2_emit_insn(4); 929 930 /* 931 * If we are to flag registers not to be used then check the instruction 932 * we just assembled for registers to be flagged. 933 */ 934 if(flag_registers){ 935 for(i = 0; i < 5; i++){ 936 if(format->ops[i].type == GREG || 937 format->ops[i].type == G0REG){ 938 val = (insn.opcode & (0x1f << format->ops[i].offset)) >> 939 format->ops[i].offset; 940 if(flag_gregs[val]) 941 as_bad("flagged register r%u used", val); 942 } 943 } 944 } 945 946 /* 947 * Deal with the instructions that are for specific cpusubtypes. 948 */ 949 if(format->cpus != 0 && !force_cpusubtype_ALL){ 950 if(no_ppc601 == 1 && format->cpus == CPU601) 951 as_bad("not allowed 601 instruction \"%s\"", format->name); 952#if !defined(ARCH64) 953 if((format->cpus & IMPL64) == IMPL64 954 && archflag_cpusubtype != CPU_SUBTYPE_POWERPC_970 955 ){ 956 as_bad("%s instruction is only for 64-bit implementations (not " 957 "allowed without -force_cpusubtype_ALL option)", 958 format->name); 959 } 960 if((format->cpus & OPTIONAL) == OPTIONAL){ 961 if((format->cpus & CPU970) == CPU970 && 962 archflag_cpusubtype != CPU_SUBTYPE_POWERPC_970) 963 as_bad("%s instruction is optional for the PowerPC (not " 964 "allowed without -force_cpusubtype_ALL option)", 965 format->name); 966 } 967 if(format->cpus == VMX && 968 (archflag_cpusubtype != CPU_SUBTYPE_POWERPC_7400 && 969 archflag_cpusubtype != CPU_SUBTYPE_POWERPC_7450 && 970 archflag_cpusubtype != CPU_SUBTYPE_POWERPC_970)){ 971 as_bad("%s vector instruction is optional for the PowerPC (not " 972 "allowed without -force_cpusubtype_ALL option)", 973 format->name); 974 } 975 else 976#endif /* !defined(ARCH64) */ 977 if(md_cpusubtype == CPU_SUBTYPE_POWERPC_ALL){ 978 switch(format->cpus){ 979 case CPU601: 980 if(archflag_cpusubtype != -1 && 981 archflag_cpusubtype != CPU_SUBTYPE_POWERPC_601) 982 as_bad("%s 601 instruction not allowed with -arch %s", 983 format->name, specific_archflag); 984 else{ 985 file_spec = logical_input_file ? 986 logical_input_file : physical_input_file; 987 line_spec = logical_input_line ? 988 logical_input_line : physical_input_line; 989 md_cpusubtype = CPU_SUBTYPE_POWERPC_601; 990 } 991 break; 992 } 993 } 994 else{ 995 switch(format->cpus){ 996 case CPU601: 997 if(archflag_cpusubtype != -1 && 998 archflag_cpusubtype != CPU_SUBTYPE_POWERPC_601) 999 as_bad("%s 601 instruction not allowed with -arch %s", 1000 format->name, specific_archflag); 1001 else{ 1002 if(md_cpusubtype != CPU_SUBTYPE_POWERPC_601) 1003 as_bad("more than one implementation specific " 1004 "instruction seen and -force_cpusubtype_ALL " 1005 "not specified (first implementation " 1006 "specific instruction in: %s at line %u)", 1007 file_spec, line_spec); 1008 } 1009 break; 1010 } 1011 } 1012 } 1013 1014 /* 1015 * We are putting a machine instruction in this section so mark it as 1016 * containg some machine instructions. 1017 */ 1018 frchain_now->frch_section.flags |= S_ATTR_SOME_INSTRUCTIONS; 1019 1020 /* if this instruction requires labels mark it for later */ 1021 switch(insn.reloc){ 1022 case PPC_RELOC_HI16: 1023 case PPC_RELOC_LO16: 1024 case PPC_RELOC_HA16: 1025 case PPC_RELOC_LO14: 1026 fix_new(frag_now, 1027 thisfrag - frag_now->fr_literal, 1028 4, 1029 insn.exp.X_add_symbol, 1030 insn.exp.X_subtract_symbol, 1031 insn.exp.X_add_number, 1032 0, 0, 1033 insn.reloc); 1034 break; 1035 case PPC_RELOC_BR14: 1036 fix_new(frag_now, 1037 thisfrag - frag_now->fr_literal, 1038 4, 1039 insn.exp.X_add_symbol, 1040 insn.exp.X_subtract_symbol, 1041 insn.exp.X_add_number, 1042 insn.pcrel, 1043 insn.pcrel_reloc, 1044 insn.reloc); 1045 break; 1046 1047 case PPC_RELOC_BR24: 1048 fix_new(frag_now, 1049 thisfrag - frag_now->fr_literal, 1050 4, 1051 insn.exp.X_add_symbol, 1052 insn.exp.X_subtract_symbol, 1053 insn.exp.X_add_number, 1054 insn.pcrel, 1055 insn.pcrel_reloc, 1056 insn.reloc); 1057 break; 1058 default: 1059 as_bad("Unknown relocation type"); 1060 break; 1061 } 1062 if(insn.jbsr_exp.X_add_symbol != NULL){ 1063 fix_new(frag_now, 1064 thisfrag - frag_now->fr_literal, 1065 4, 1066 insn.jbsr_exp.X_add_symbol, 1067 insn.jbsr_exp.X_subtract_symbol, 1068 insn.jbsr_exp.X_add_number, 1069 0, /* pcrel */ 1070 1, /* pcrel_reloc */ 1071 PPC_RELOC_JBSR); 1072 } 1073} 1074 1075static 1076int 1077calcop( 1078struct ppc_opcode *format, 1079char *param, 1080struct ppc_insn *insn, 1081char *op, 1082enum branch_prediction prediction) 1083{ 1084 uint32_t parcnt, bo; 1085 1086 /* initial the passed structure */ 1087 memset(insn, '\0', sizeof(struct ppc_insn)); 1088 insn->opcode = format->opcode; 1089 insn->reloc = NO_RELOC; 1090 1091 /* parse all parameters */ 1092 for(parcnt = 0; parcnt < 5 && 1093 format->ops[parcnt].type != NONE; parcnt++){ 1094 error_param_count = parcnt; 1095 1096 switch(format->ops[parcnt].type){ 1097 case JBSR: 1098 param = parse_jbsr(param, insn, format, parcnt); 1099 break; 1100 case PCREL: 1101 case BADDR: 1102 param = parse_branch(param, insn, format, parcnt); 1103 break; 1104 case D: 1105 case DS: 1106 param = parse_displacement(param, insn, format, parcnt); 1107 break; 1108 case SI: 1109 case UI: 1110 case HI: 1111 param = parse_immediate(param, insn, format, parcnt); 1112 break; 1113 case GREG: 1114 case G0REG: 1115 param = parse_reg("r", param, insn, format, parcnt); 1116 break; 1117 case FREG: 1118 param = parse_reg("f", param, insn, format, parcnt); 1119 break; 1120 case VREG: 1121 param = parse_reg("v", param, insn, format, parcnt); 1122 break; 1123 case SGREG: 1124 param = parse_reg("sr", param, insn, format, parcnt); 1125 break; 1126 case SPREG: 1127 param = parse_spreg(param, insn, format, parcnt); 1128 break; 1129 case BCND: 1130 param = parse_bcnd(param, insn, format, parcnt); 1131 break; 1132 case CRF: 1133 case CRFONLY: 1134 param = parse_crf(param, insn, format, parcnt); 1135 break; 1136 case SNUM: 1137 param = parse_num(param, insn, format, parcnt, 0, 0, 1, 0); 1138 break; 1139 case FXM: 1140 param = parse_num(param, insn, format, parcnt, 0, 0, 0, 1); 1141 break; 1142 case NUM: 1143 param = parse_num(param, insn, format, parcnt, 0, 0, 0, 0); 1144 break; 1145 case NUM0: 1146 param = parse_num(param, insn, format, parcnt, 1, 0, 0, 0); 1147 break; 1148 case MBE: 1149 param = parse_mbe(param, insn, format, parcnt); 1150 break; 1151 case ZERO: 1152 param = parse_num(param, insn, format, parcnt, 0, 1, 0, 0); 1153 break; 1154 case sh: 1155 param = parse_sh(param, insn, format, parcnt); 1156 break; 1157 case mb: 1158 param = parse_mb(param, insn, format, parcnt); 1159 break; 1160 default: 1161 as_fatal("Unknown parameter type"); 1162 } 1163 1164 /* see if parser failed or not */ 1165 if (param == NULL) 1166 return(0); 1167 } 1168 if((parcnt == 5 && *param != '\0') || 1169 (format->ops[0].type == NONE && *param != '\0')){ 1170 error_param_message = "too many parameters"; 1171 return(0); 1172 } 1173 1174 if(IS_BRANCH_CONDITIONAL(insn->opcode)){ 1175 if(prediction != BRANCH_PREDICTION_NONE){ 1176 if(prediction == BRANCH_PREDICTION_LIKELY_TAKEN || 1177 prediction == BRANCH_PREDICTION_LIKELY_NOT_TAKEN){ 1178 /* 1179 * Set the Y_BIT assuming the displacement is non-negitive. 1180 * If the displacement is negitive then the Y_BIT is flipped 1181 * in md_number_to_imm() if the reloc is 1182 * PPC_RELOC_BR14_predicted. 1183 */ 1184 if(insn->reloc == PPC_RELOC_BR14) 1185 insn->reloc = PPC_RELOC_BR14_predicted; 1186 if(prediction == BRANCH_PREDICTION_LIKELY_TAKEN) 1187 insn->opcode |= Y_BIT; 1188 else{ /* prediction == BRANCH_PREDICTION_LIKELY_NOT_TAKEN */ 1189 if((insn->opcode & Y_BIT) != 0) 1190 as_warn("branch prediction ('-') ignored (specified" 1191 " operand has prediction bit set)"); 1192 else 1193 insn->opcode &= ~(Y_BIT); 1194 } 1195 } 1196 if(prediction == BRANCH_PREDICTION_VERY_LIKELY_TAKEN || 1197 prediction == BRANCH_PREDICTION_VERY_LIKELY_NOT_TAKEN){ 1198 bo = (insn->opcode >> 21) & 0x1f; 1199 /* 1200 * For 'branch if the condition is FALSE or TRUE' the AT 1201 * bits are the lower 2 bits of the BO field (xxxAT). 1202 */ 1203 if(bo == 0x04 || bo == 0x0c){ 1204 if(prediction == BRANCH_PREDICTION_VERY_LIKELY_TAKEN) 1205 insn->opcode |= 0x00600000; /* AT == 11 */ 1206 else 1207 insn->opcode |= 0x00400000; /* AT == 10 */ 1208 } 1209 else if(bo == 0x10 || bo == 0x12){ 1210 /* 1211 * For 'decrement the CTR, then branch if the 1212 * decremented CTR is non-zero or zero' the AT bits are 1213 * the xAxxT bits of the BO field. 1214 */ 1215 if(prediction == BRANCH_PREDICTION_VERY_LIKELY_TAKEN) 1216 insn->opcode |= 0x01200000; /* AT == 11 */ 1217 else 1218 insn->opcode |= 0x01000000; /* AT == 10 */ 1219 } 1220 else{ 1221 if(prediction == BRANCH_PREDICTION_VERY_LIKELY_TAKEN) 1222 as_warn("branch prediction ('++') ignored " 1223 "(specified operand has does not allow this" 1224 " prediction)"); 1225 else 1226 as_warn("branch prediction ('--') ignored " 1227 "(specified operand has does not allow this" 1228 " prediction)"); 1229 } 1230 } 1231 } 1232 } 1233 else{ 1234 if(prediction != '\0') 1235 as_warn("branch prediction ignored (instruction is not a " 1236 "conditional branch)"); 1237 } 1238 return(1); 1239} 1240 1241static 1242char * 1243parse_displacement( 1244char *param, 1245struct ppc_insn *insn, 1246struct ppc_opcode *format, 1247int parcnt) 1248{ 1249 signed_target_addr_t val; 1250 char *end, *saveptr, *saveparam; 1251 segT seg; 1252 1253 1254 if(parcnt != 1 || 1255 (format->ops[2].type != G0REG && format->ops[2].type != GREG)) 1256 as_fatal("internal error, bad table entry for instruction %s " 1257 "(displacement operand not second operand or general " 1258 "register not third operand)", format->name); 1259 1260 /* 1261 * There must be "(rX)" (where X is a number between 0-31) or "(0)" 1262 * at the end of the parameter string. To know out where the 1263 * displacement expression ends determine the begining the "(rX)" 1264 * by looking for the last '(' in the string. The parsing of this 1265 * trailing string will be done in another routine. 1266 */ 1267 end = strrchr(param, '('); 1268 if(end == NULL) 1269 return(NULL); 1270 *end = '\0'; 1271 1272 /* 1273 * The expression may have one of the following: hi16(exp), ha16(exp), 1274 * or lo16(exp) around the expression which determines the relocation 1275 * type. 1276 */ 1277 if(strncmp(param,"hi16(",5) == 0){ 1278 insn->reloc = PPC_RELOC_HI16; 1279 param += 5; 1280 } 1281 else if(strncmp(param,"ha16(",5) == 0){ 1282 insn->reloc = PPC_RELOC_HA16; 1283 param += 5; 1284 } 1285 else if(strncmp(param,"lo16(",5) == 0){ 1286 if(format->ops[parcnt].type == DS) 1287 insn->reloc = PPC_RELOC_LO14; 1288 else 1289 insn->reloc = PPC_RELOC_LO16; 1290 param += 5; 1291 } 1292 1293 saveptr = input_line_pointer; 1294 input_line_pointer = param; 1295 1296 seg = expression(&insn->exp); 1297 try_to_make_absolute(&insn->exp); 1298 seg = insn->exp.X_seg; 1299 1300 saveparam = input_line_pointer; 1301 input_line_pointer = saveptr; 1302 *end = '('; 1303 1304 if(insn->reloc != NO_RELOC){ 1305 if(*saveparam != ')' || ++saveparam != end) 1306 return(NULL); 1307 } 1308 else{ 1309 if(saveparam != end) 1310 return(NULL); 1311 val = insn->exp.X_add_number; 1312 if(seg != SEG_ABSOLUTE){ 1313 error_param_message = "Parameter error: expression must be " 1314 "absolute"; 1315 return(NULL); 1316 } 1317 if(val & 0x8000){ 1318 if((val & 0xffff0000) != 0xffff0000){ 1319 error_param_message = "Parameter error: expression out of " 1320 "range"; 1321 return(NULL); 1322 } 1323 val = val & 0xffff; 1324 } 1325 else{ 1326 if((val & 0xffff0000) != 0){ 1327 error_param_message = "Parameter error: expression out of " 1328 "range"; 1329 return(NULL); 1330 } 1331 } 1332 if(format->ops[parcnt].type == DS){ 1333 if((val & 0x3) != 0){ 1334 error_param_message = "Parameter error: expression must be " 1335 "a multiple of 4"; 1336 return(NULL); 1337 } 1338 val >>= 2; 1339 } 1340 insn->opcode |= val << format->ops[parcnt].offset; 1341 } 1342 return(saveparam); 1343} 1344 1345static 1346char * 1347parse_immediate( 1348char *param, 1349struct ppc_insn *insn, 1350struct ppc_opcode *format, 1351int parcnt) 1352{ 1353 uint32_t val; 1354 char *saveptr, *saveparam; 1355 segT seg; 1356 1357 /* 1358 * The expression may have one of the following: hi16(exp), ha16(exp), 1359 * or lo16(exp) around the expression which determines the relocation 1360 * type. 1361 */ 1362 if(strncmp(param,"hi16(",5) == 0){ 1363 insn->reloc = PPC_RELOC_HI16; 1364 param += 5; 1365 } 1366 else if(strncmp(param,"ha16(",5) == 0){ 1367 insn->reloc = PPC_RELOC_HA16; 1368 param += 5; 1369 } 1370 else if(strncmp(param,"lo16(",5) == 0){ 1371 if(format->ops[parcnt].type == DS) 1372 insn->reloc = PPC_RELOC_LO14; 1373 else 1374 insn->reloc = PPC_RELOC_LO16; 1375 param += 5; 1376 } 1377 1378 saveptr = input_line_pointer; 1379 input_line_pointer = param; 1380 1381 seg = expression(&insn->exp); 1382 try_to_make_absolute(&insn->exp); 1383 seg = insn->exp.X_seg; 1384 1385 saveparam = input_line_pointer; 1386 input_line_pointer = saveptr; 1387 1388 if(insn->reloc != NO_RELOC){ 1389 if(*saveparam != ')') 1390 return(NULL); 1391 saveparam++; 1392 if(*saveparam == '\0'){ 1393 if(parcnt == 4 || format->ops[parcnt+1].type == NONE) 1394 return(saveparam); 1395 else 1396 return(NULL); 1397 } 1398 else if(*saveparam == ','){ 1399 if(parcnt != 4 && format->ops[parcnt+1].type != NONE) 1400 return(saveparam+1); 1401 else 1402 return(NULL); 1403 } 1404 else 1405 return(NULL); 1406 } 1407 else{ 1408 val = insn->exp.X_add_number; 1409 if(seg != SEG_ABSOLUTE){ 1410 error_param_message = "Parameter error: expression must be " 1411 "absolute"; 1412 return(NULL); 1413 } 1414 if(format->ops[parcnt].type == SI){ 1415 if(val & 0x8000){ 1416 if((val & 0xffff0000) != 0xffff0000){ 1417 error_param_message = "Parameter error: expression out " 1418 "of range"; 1419 return(NULL); 1420 } 1421 val = val & 0xffff; 1422 } 1423 else{ 1424 if((val & 0xffff0000) != 0){ 1425 error_param_message = "Parameter error: expression out " 1426 "of range"; 1427 return(NULL); 1428 } 1429 } 1430 } 1431 else if(format->ops[parcnt].type == UI){ 1432 if((val & 0xffff0000) != 0){ 1433 error_param_message = "Parameter error: expression out " 1434 "of range"; 1435 return(NULL); 1436 } 1437 } 1438 else if(format->ops[parcnt].type == HI){ 1439 if((val & 0xffff0000) != 0 && 1440 (val & 0xffff0000) != 0xffff0000){ 1441 error_param_message = "Parameter error: expression out " 1442 "of range"; 1443 return(NULL); 1444 } 1445 val = val & 0xffff; 1446 } 1447 if(*saveparam == '\0'){ 1448 if(parcnt == 4 || format->ops[parcnt+1].type == NONE){ 1449 insn->opcode |= val << format->ops[parcnt].offset; 1450 return(saveparam); 1451 } 1452 else 1453 return(NULL); 1454 } 1455 else if(*saveparam == ','){ 1456 if(parcnt != 4 && format->ops[parcnt+1].type != NONE){ 1457 insn->opcode |= val << format->ops[parcnt].offset; 1458 return(saveparam+1); 1459 } 1460 else 1461 return(NULL); 1462 } 1463 else 1464 return(NULL); 1465 } 1466 return(saveparam); 1467} 1468 1469static 1470char * 1471parse_jbsr( 1472char *param, 1473struct ppc_insn *insn, 1474struct ppc_opcode *format, 1475int parcnt) 1476{ 1477 char *saveptr, *saveparam, *p; 1478 segT seg; 1479 short reference; 1480 1481 reference = 0; 1482 saveptr = input_line_pointer; 1483 input_line_pointer = param; 1484 1485 /* 1486 * If we are assembling -dynamic then if the symbol name before the ',' 1487 * has not yet been seen it will be marked as a non-lazy reference. 1488 */ 1489 if(flagseen[(int)'k'] == TRUE){ 1490 p = strchr(param, ','); 1491 if(p != NULL) 1492 *p = '\0'; 1493 if(symbol_find(param) == NULL) 1494 reference = REFERENCE_FLAG_UNDEFINED_LAZY; 1495 else 1496 reference = REFERENCE_FLAG_UNDEFINED_NON_LAZY; 1497 if(p != NULL) 1498 *p = ','; 1499 } 1500 1501 seg = expression(&insn->jbsr_exp); 1502 try_to_make_absolute(&insn->jbsr_exp); 1503 seg = insn->jbsr_exp.X_seg; 1504 1505 if(flagseen[(int)'k'] == TRUE) 1506 insn->jbsr_exp.X_add_symbol->sy_desc |= reference; 1507 1508 saveparam = input_line_pointer; 1509 input_line_pointer = saveptr; 1510 1511 if(*saveparam == ',') 1512 return(saveparam+1); 1513 else 1514 return(NULL); 1515} 1516 1517static 1518char * 1519parse_branch( 1520char *param, 1521struct ppc_insn *insn, 1522struct ppc_opcode *format, 1523int parcnt) 1524{ 1525 char *saveptr, *saveparam; 1526 segT seg; 1527 1528 saveptr = input_line_pointer; 1529 input_line_pointer = param; 1530 1531 seg = expression(&insn->exp); 1532 try_to_make_absolute(&insn->exp); 1533 seg = insn->exp.X_seg; 1534 1535 saveparam = input_line_pointer; 1536 input_line_pointer = saveptr; 1537 1538 insn->pcrel = 0; 1539 insn->pcrel_reloc = 0; 1540 if(format->ops[parcnt].type == PCREL){ 1541 /* 1542 * The NeXT linker has the ability to scatter blocks of 1543 * sections between labels. This requires that brances to 1544 * labels that survive to the link phase must be able to 1545 * be relocated. 1546 */ 1547 if(insn->exp.X_add_symbol != NULL && 1548 (insn->exp.X_add_symbol->sy_name[0] != 'L' || flagseen ['L'])){ 1549 if(insn->jbsr_exp.X_add_symbol != NULL) 1550 as_fatal("Stub label used in a JBSR must be " 1551 "non-relocatable"); 1552 insn->pcrel_reloc = 1; 1553 } 1554 else{ 1555 insn->pcrel_reloc = 0; 1556 } 1557 insn->pcrel = 1; 1558 } 1559 switch(format->ops[parcnt].width){ 1560 case 14: 1561 insn->reloc = PPC_RELOC_BR14; 1562 break; 1563 case 24: 1564 insn->reloc = PPC_RELOC_BR24; 1565 break; 1566 default: 1567 as_fatal("Unknown branch instruction width %d", 1568 format->ops[parcnt].width); 1569 break; 1570 } 1571 return(saveparam); 1572} 1573 1574static 1575char * 1576parse_reg( 1577char *reg_name, 1578char *param, 1579struct ppc_insn *insn, 1580struct ppc_opcode *format, 1581uint32_t parcnt) 1582{ 1583 uint32_t val, d; 1584 1585 d = 0; 1586 if(*param == '(' && parcnt == 2 && 1587 (format->ops[1].type == D || format->ops[1].type == DS)){ 1588 d = 1; 1589 param++; 1590 } 1591 1592 if(format->ops[parcnt].type == G0REG && *param == '0'){ 1593 val = 0; 1594 param++; 1595 } 1596 else{ 1597 val = 0; 1598 while(*reg_name){ 1599 if(*param++ != *reg_name++) 1600 return(NULL); 1601 } 1602 if(!isdigit(*param)) 1603 return(NULL); 1604 1605 while(isdigit(*param)) 1606 if((val = val * 10 + *param++ - '0') >= 1607 (uint32_t)(1 << format->ops[parcnt].width)) 1608 return(NULL); 1609 1610 if(format->ops[parcnt].type == G0REG && val == 0){ 1611 error_param_message = "Parameter error: r0 not allowed " 1612 "for parameter %lu (code as 0 not r0)"; 1613 return(NULL); 1614 } 1615 } 1616 1617 if(*param == '\0'){ 1618 if(parcnt == 4 || format->ops[parcnt+1].type == NONE){ 1619 insn->opcode |= val << format->ops[parcnt].offset; 1620 return(param); 1621 } 1622 else 1623 return(NULL); 1624 } 1625 else if(*param == ','){ 1626 if(parcnt != 4 && format->ops[parcnt+1].type != NONE){ 1627 insn->opcode |= val << format->ops[parcnt].offset; 1628 return(param+1); 1629 } 1630 else 1631 return(NULL); 1632 } 1633 else if(d == 1 && *param == ')' && param[1] == '\0'){ 1634 if(parcnt == 4 || format->ops[parcnt+1].type == NONE){ 1635 insn->opcode |= val << format->ops[parcnt].offset; 1636 return(++param); 1637 } 1638 else 1639 return(NULL); 1640 } 1641 return(NULL); 1642} 1643 1644static 1645char * 1646parse_spreg( 1647char *param, 1648struct ppc_insn *insn, 1649struct ppc_opcode *format, 1650uint32_t parcnt) 1651{ 1652 signed_target_addr_t val; 1653 uint32_t i; 1654 char *saveptr, save_c; 1655 expressionS exp; 1656 segT seg; 1657 1658 saveptr = input_line_pointer; 1659 input_line_pointer = param; 1660 while(*param != ',' && *param != '\0') 1661 param++; 1662 save_c = *param; 1663 *param = '\0'; 1664 1665 seg = SEG_ABSOLUTE; 1666 val = 0; 1667 for(i = 0; *special_registers[i].name != '\0'; i++){ 1668 if(strcmp(input_line_pointer, special_registers[i].name) == 0){ 1669 val = special_registers[i].number; 1670 break; 1671 } 1672 } 1673 if(*special_registers[i].name == '\0'){ 1674 seg = expression(&exp); 1675 try_to_make_absolute(&exp); 1676 seg = exp.X_seg; 1677 val = exp.X_add_number; 1678 } 1679 *param = save_c; 1680 input_line_pointer = saveptr; 1681 1682 if(seg != SEG_ABSOLUTE){ 1683 error_param_message = "Parameter error: expression must be " 1684 "absolute"; 1685 return(NULL); 1686 } 1687 if(val > 1024 || val < 0){ 1688 error_param_message = "Parameter error: expression out " 1689 "of range"; 1690 return(NULL); 1691 } 1692 1693 val = ((val & 0x1f) << 5) | ((val >> 5) & 0x1f); 1694 1695 if(*param == '\0'){ 1696 if(parcnt == 4 || format->ops[parcnt+1].type == NONE){ 1697 insn->opcode |= val << format->ops[parcnt].offset; 1698 return(param); 1699 } 1700 else 1701 return(NULL); 1702 } 1703 else if(*param == ','){ 1704 if(parcnt != 4 && format->ops[parcnt+1].type != NONE){ 1705 insn->opcode |= val << format->ops[parcnt].offset; 1706 return(param+1); 1707 } 1708 else 1709 return(NULL); 1710 } 1711 return(NULL); 1712} 1713 1714static 1715char * 1716parse_bcnd( 1717char *param, 1718struct ppc_insn *insn, 1719struct ppc_opcode *format, 1720uint32_t parcnt) 1721{ 1722 signed_target_addr_t val; 1723 uint32_t i, j; 1724 char *saveptr, save_c, *plus, save_plus; 1725 expressionS exp; 1726 segT seg; 1727 1728 saveptr = input_line_pointer; 1729 input_line_pointer = param; 1730 while(*param != ',' && *param != '\0') 1731 param++; 1732 save_c = *param; 1733 *param = '\0'; 1734 1735 /* 1736 * look for "[CR_field+]condition_symbol". 1737 */ 1738 val = -1; 1739 for(plus = input_line_pointer; *plus != '+' && *plus != '\0'; plus++) 1740 ; 1741 if(*plus == '+'){ 1742 save_plus = *plus; 1743 *plus = '\0'; 1744 for(i = 0; *CR_fields[i].name != '\0'; i++) 1745 if(strcmp(input_line_pointer, CR_fields[i].name) == 0) 1746 break; 1747 *plus = save_plus; 1748 if(*CR_fields[i].name != '\0'){ 1749 for(j = 0; *condition_symbols[j].name != '\0'; j++) 1750 if(strcmp(plus+1, condition_symbols[j].name) == 0) 1751 break; 1752 if(*condition_symbols[j].name != '\0'){ 1753 val = CR_fields[i].value + condition_symbols[j].value; 1754 } 1755 } 1756 } 1757 else{ 1758 for(i = 0; *condition_symbols[i].name != '\0'; i++) 1759 if(strcmp(input_line_pointer, condition_symbols[i].name) == 0) 1760 break; 1761 if(*condition_symbols[i].name != '\0') 1762 val = condition_symbols[i].value; 1763 } 1764 if(val == -1){ 1765 seg = expression(&exp); 1766 try_to_make_absolute(&exp); 1767 seg = exp.X_seg; 1768 val = exp.X_add_number; 1769 if(seg != SEG_ABSOLUTE){ 1770 error_param_message = "Parameter error: expression must be " 1771 "absolute"; 1772 *param = save_c; 1773 input_line_pointer = saveptr; 1774 return(NULL); 1775 } 1776 if(val >= (1 << format->ops[parcnt].width) || val < 0){ 1777 error_param_message = "Parameter error: expression out " 1778 "of range"; 1779 *param = save_c; 1780 input_line_pointer = saveptr; 1781 return(NULL); 1782 } 1783 } 1784 1785 *param = save_c; 1786 input_line_pointer = saveptr; 1787 1788 1789 if(*param == '\0'){ 1790 if(parcnt == 4 || format->ops[parcnt+1].type == NONE){ 1791 insn->opcode |= val << format->ops[parcnt].offset; 1792 return(param); 1793 } 1794 else 1795 return(NULL); 1796 } 1797 else if(*param == ','){ 1798 if(parcnt != 4 && format->ops[parcnt+1].type != NONE){ 1799 insn->opcode |= val << format->ops[parcnt].offset; 1800 return(param+1); 1801 } 1802 else 1803 return(NULL); 1804 } 1805 return(NULL); 1806 1807} 1808 1809static 1810char * 1811parse_crf( 1812char *param, 1813struct ppc_insn *insn, 1814struct ppc_opcode *format, 1815uint32_t parcnt) 1816{ 1817 signed_target_addr_t val; 1818 uint32_t i; 1819 char *saveptr, save_c; 1820 expressionS exp; 1821 segT seg; 1822 1823 saveptr = input_line_pointer; 1824 input_line_pointer = param; 1825 while(*param != ',' && *param != '\0') 1826 param++; 1827 save_c = *param; 1828 *param = '\0'; 1829 val = -1; 1830 for(i = 0; *CR_fields[i].name != '\0'; i++){ 1831 if(strcmp(input_line_pointer, CR_fields[i].name) == 0){ 1832 val = CR_fields[i].value; 1833 break; 1834 } 1835 } 1836 if(val == -1){ 1837 if(format->ops[parcnt].type == CRFONLY){ 1838 *param = save_c; 1839 input_line_pointer = saveptr; 1840 return(NULL); 1841 } 1842 seg = expression(&exp); 1843 try_to_make_absolute(&exp); 1844 seg = exp.X_seg; 1845 val = exp.X_add_number; 1846 if(seg != SEG_ABSOLUTE){ 1847 error_param_message = "Parameter error: expression must be " 1848 "absolute"; 1849 *param = save_c; 1850 input_line_pointer = saveptr; 1851 return(NULL); 1852 } 1853 if(val >= (1 << format->ops[parcnt].width) || val < 0){ 1854 error_param_message = "Parameter error: expression out " 1855 "of range"; 1856 *param = save_c; 1857 input_line_pointer = saveptr; 1858 return(NULL); 1859 } 1860 } 1861 *param = save_c; 1862 input_line_pointer = saveptr; 1863 1864 if(*param == '\0'){ 1865 if(parcnt == 4 || format->ops[parcnt+1].type == NONE){ 1866 insn->opcode |= val << format->ops[parcnt].offset; 1867 return(param); 1868 } 1869 else 1870 return(NULL); 1871 } 1872 else if(*param == ','){ 1873 if(parcnt != 4 && format->ops[parcnt+1].type != NONE){ 1874 insn->opcode |= val << format->ops[parcnt].offset; 1875 return(param+1); 1876 } 1877 else 1878 return(NULL); 1879 } 1880 return(NULL); 1881} 1882 1883static 1884char * 1885parse_num( 1886char *param, 1887struct ppc_insn *insn, 1888struct ppc_opcode *format, 1889uint32_t parcnt, 1890int32_t max_width_zero, 1891int32_t zero_only, 1892int32_t signed_num, 1893int32_t bit_mask_with_1_bit_set) 1894{ 1895 signed_target_addr_t val; 1896 int i, max, min, mask, temp; 1897 char *saveptr, save_c; 1898 expressionS exp; 1899 segT seg; 1900 1901 saveptr = input_line_pointer; 1902 input_line_pointer = param; 1903 while(*param != ',' && *param != '\0') 1904 param++; 1905 save_c = *param; 1906 *param = '\0'; 1907 seg = expression(&exp); 1908 try_to_make_absolute(&exp); 1909 seg = exp.X_seg; 1910 *param = save_c; 1911 input_line_pointer = saveptr; 1912 1913 val = exp.X_add_number; 1914 if(seg != SEG_ABSOLUTE){ 1915 error_param_message = "Parameter error: expression must be " 1916 "absolute"; 1917 return(NULL); 1918 } 1919 if(max_width_zero){ 1920 if(val == (1 << format->ops[parcnt].width)) 1921 val = 0; 1922 } 1923 if(signed_num){ 1924 max = (1 << (format->ops[parcnt].width - 1)) - 1; 1925 min = (0xffffffff << (format->ops[parcnt].width - 1)); 1926 temp = val; 1927 if(temp > max || temp < min){ 1928 error_param_message = "Parameter error: expression out " 1929 "of range"; 1930 return(NULL); 1931 } 1932 } 1933 else{ 1934 max = (1 << (format->ops[parcnt].width)) - 1; 1935 if(val > max){ 1936 error_param_message = "Parameter error: expression out " 1937 "of range"; 1938 return(NULL); 1939 } 1940 } 1941 if(bit_mask_with_1_bit_set){ 1942 mask = 1; 1943 for(i = 0; i < format->ops[parcnt].width; i++){ 1944 if(mask & val) 1945 break; 1946 mask = mask << 1; 1947 } 1948 /* 1949 * If this is the mtcrf opcode (0x7c000120) and val is not zero and 1950 * has exactly one bit set then use the new form of the mtcrf 1951 * opcode. This has bit 0x00100000 set and the FXM field is a bit 1952 * mask. Else use the old form without bit 0x00100000 set. 1953 */ 1954 if(insn->opcode == 0x7c000120){ 1955 if(val != 0 && val == mask) 1956 insn->opcode |= 0x00100000; 1957 } 1958 else{ 1959 /* 1960 * For instructions other than mtcrf if exactly one bit in val 1961 * is not set it is an error. 1962 */ 1963 if(val == 0 || val != mask){ 1964 error_param_message = "Parameter error: expression must " 1965 "have exactly one bit set"; 1966 return(NULL); 1967 } 1968 } 1969 } 1970 if(zero_only == 1 && val != 0){ 1971 error_param_message = "Parameter error: expression must have a " 1972 "value of zero"; 1973 return(NULL); 1974 } 1975 if(*param == '\0'){ 1976 if(parcnt == 4 || format->ops[parcnt+1].type == NONE){ 1977 insn->opcode |= (val & ((1 << format->ops[parcnt].width)-1)) << 1978 format->ops[parcnt].offset; 1979 return(param); 1980 } 1981 else 1982 return(NULL); 1983 } 1984 else if(*param == ','){ 1985 if(parcnt != 4 && format->ops[parcnt+1].type != NONE){ 1986 insn->opcode |= (val & ((1 << format->ops[parcnt].width)-1)) << 1987 format->ops[parcnt].offset; 1988 return(param+1); 1989 } 1990 else 1991 return(NULL); 1992 } 1993 return(NULL); 1994} 1995 1996static 1997char * 1998parse_mbe( 1999char *param, 2000struct ppc_insn *insn, 2001struct ppc_opcode *format, 2002uint32_t parcnt) 2003{ 2004 signed_target_addr_t val; 2005 char *saveptr, save_c; 2006 expressionS exp; 2007 segT seg; 2008 2009 if (parcnt == 4 && *param == '\0') 2010 return param; 2011 2012 saveptr = input_line_pointer; 2013 input_line_pointer = param; 2014 while(*param != ',' && *param != '\0') 2015 param++; 2016 save_c = *param; 2017 *param = '\0'; 2018 seg = expression(&exp); 2019 try_to_make_absolute(&exp); 2020 seg = exp.X_seg; 2021 *param = save_c; 2022 input_line_pointer = saveptr; 2023 2024 val = exp.X_add_number; 2025 if(seg != SEG_ABSOLUTE){ 2026 error_param_message = "Parameter error: expression must be " 2027 "absolute"; 2028 return(NULL); 2029 } 2030 /* Note that we need to allow all 32-bit values for val. */ 2031 2032 /* Look for the special case. */ 2033 2034 if (parcnt == 3 && *param == '\0') 2035 { 2036 uint32_t uval, mask; 2037 int mb, me, mx, count, last; 2038 2039 uval = val; 2040 2041 mb = 0; 2042 me = 32; 2043 if ((uval & 1) != 0) 2044 last = 1; 2045 else 2046 last = 0; 2047 count = 0; 2048 2049 /* mb: location of last 0->1 transition */ 2050 /* me: location of last 1->0 transition */ 2051 /* count: # transitions */ 2052 2053 for (mx = 0, mask = 1 << 31; mx < 32; ++mx, mask >>= 1) 2054 { 2055 if ((uval & mask) && !last) 2056 { 2057 ++count; 2058 mb = mx; 2059 last = 1; 2060 } 2061 else if (!(uval & mask) && last) 2062 { 2063 ++count; 2064 me = mx; 2065 last = 0; 2066 } 2067 } 2068 if (me == 0) 2069 me = 32; 2070 2071 if (count != 2 && (count != 0 || ! last)) 2072 { 2073 return NULL; 2074 } 2075 2076 insn->opcode |= (mb & ((1 << format->ops[parcnt].width)-1)) << 2077 format->ops[parcnt].offset; 2078 insn->opcode |= ((me - 1) & ((1 << format->ops[parcnt+1].width)-1)) << 2079 format->ops[parcnt+1].offset; 2080 2081 return param; 2082 } 2083 2084 if((parcnt == 3 || parcnt == 4)){ 2085 insn->opcode |= (val & ((1 << format->ops[parcnt].width)-1)) << 2086 format->ops[parcnt].offset; 2087 return((parcnt == 3 ? param+1 : param)); 2088 } 2089 2090 return(NULL); 2091 2092} 2093 2094static 2095char * 2096parse_sh( 2097char *param, 2098struct ppc_insn *insn, 2099struct ppc_opcode *format, 2100uint32_t parcnt) 2101{ 2102 signed_target_addr_t val; 2103 char *saveptr, save_c; 2104 expressionS exp; 2105 segT seg; 2106 2107 saveptr = input_line_pointer; 2108 input_line_pointer = param; 2109 while(*param != ',' && *param != '\0') 2110 param++; 2111 save_c = *param; 2112 *param = '\0'; 2113 seg = expression(&exp); 2114 try_to_make_absolute(&exp); 2115 seg = exp.X_seg; 2116 *param = save_c; 2117 input_line_pointer = saveptr; 2118 2119 val = exp.X_add_number; 2120 if(seg != SEG_ABSOLUTE){ 2121 error_param_message = "Parameter error: expression must be " 2122 "absolute"; 2123 return(NULL); 2124 } 2125 if(val == 64) 2126 val = 0; 2127 if(val >= 64 || val < 0){ 2128 error_param_message = "Parameter error: expression out " 2129 "of range"; 2130 return(NULL); 2131 } 2132 2133 if(*param == '\0'){ 2134 if(parcnt == 4 || format->ops[parcnt+1].type == NONE){ 2135 insn->opcode |= (val & 0x1f) << 11; 2136 insn->opcode |= ((val >> 5) & 0x1) << 1; 2137 return(param); 2138 } 2139 else 2140 return(NULL); 2141 } 2142 else if(*param == ','){ 2143 if(parcnt != 4 && format->ops[parcnt+1].type != NONE){ 2144 insn->opcode |= (val & 0x1f) << 11; 2145 insn->opcode |= ((val >> 5) & 0x1) << 1; 2146 return(param+1); 2147 } 2148 else 2149 return(NULL); 2150 } 2151 return(NULL); 2152 2153} 2154 2155static 2156char * 2157parse_mb( 2158char *param, 2159struct ppc_insn *insn, 2160struct ppc_opcode *format, 2161uint32_t parcnt) 2162{ 2163 signed_target_addr_t val; 2164 char *saveptr, save_c; 2165 expressionS exp; 2166 segT seg; 2167 2168 saveptr = input_line_pointer; 2169 input_line_pointer = param; 2170 while(*param != ',' && *param != '\0') 2171 param++; 2172 save_c = *param; 2173 *param = '\0'; 2174 seg = expression(&exp); 2175 try_to_make_absolute(&exp); 2176 seg = exp.X_seg; 2177 *param = save_c; 2178 input_line_pointer = saveptr; 2179 2180 val = exp.X_add_number; 2181 if(seg != SEG_ABSOLUTE){ 2182 error_param_message = "Parameter error: expression must be " 2183 "absolute"; 2184 return(NULL); 2185 } 2186 if(val > 64 || val < 0){ 2187 error_param_message = "Parameter error: expression out " 2188 "of range"; 2189 return(NULL); 2190 } 2191 2192 if(*param == '\0'){ 2193 if(parcnt == 4 || format->ops[parcnt+1].type == NONE){ 2194 insn->opcode |= (val & 0x1f) << 6; 2195 insn->opcode |= ((val >> 5) & 0x1) << 5; 2196 return(param); 2197 } 2198 else 2199 return(NULL); 2200 } 2201 else if(*param == ','){ 2202 if(parcnt != 4 && format->ops[parcnt+1].type != NONE){ 2203 insn->opcode |= (val & 0x1f) << 6; 2204 insn->opcode |= ((val >> 5) & 0x1) << 5; 2205 return(param+1); 2206 } 2207 else 2208 return(NULL); 2209 } 2210 return(NULL); 2211 2212} 2213 2214/* 2215 * md_number_to_chars() is the target machine dependent routine that puts out 2216 * a binary value of size 8, 4, 2, or 1 bytes into the specified buffer. This 2217 * is done in the target machine's byte sex. In this case the byte order is 2218 * big endian. 2219 */ 2220void 2221md_number_to_chars( 2222char *buf, 2223signed_expr_t val, 2224int nbytes) 2225{ 2226 switch(nbytes){ 2227 case 8: 2228 *buf++ = val >> 56; 2229 *buf++ = val >> 48; 2230 *buf++ = val >> 40; 2231 *buf++ = val >> 32; 2232 case 4: 2233 *buf++ = val >> 24; 2234 *buf++ = val >> 16; 2235 case 2: 2236 *buf++ = val >> 8; 2237 case 1: 2238 *buf = val; 2239 break; 2240 2241 default: 2242 abort(); 2243 } 2244} 2245 2246/* 2247 * md_number_to_imm() is the target machine dependent routine that puts out 2248 * a binary value of size 4, 2, or 1 bytes into the specified buffer with 2249 * reguard to a possible relocation entry (the fixP->fx_r_type field in the fixS 2250 * structure pointed to by fixP) for the section with the ordinal nsect. This 2251 * is done in the target machine's byte sex using it's relocation types. 2252 * In this case the byte order is big endian. 2253 */ 2254void 2255md_number_to_imm( 2256unsigned char *buf, 2257signed_expr_t val, 2258int nbytes, 2259fixS *fixP, 2260int nsect) 2261{ 2262 uint32_t opcode; 2263 2264 if(fixP->fx_r_type == NO_RELOC || 2265 fixP->fx_r_type == PPC_RELOC_VANILLA){ 2266 switch(nbytes){ 2267 case 8: 2268 *buf++ = val >> 56; 2269 *buf++ = val >> 48; 2270 *buf++ = val >> 40; 2271 *buf++ = val >> 32; 2272 case 4: 2273 *buf++ = val >> 24; 2274 *buf++ = val >> 16; 2275 case 2: 2276 *buf++ = val >> 8; 2277 case 1: 2278 *buf = val; 2279 break; 2280 2281 default: 2282 abort(); 2283 } 2284 return; 2285 } 2286 switch(fixP->fx_r_type){ 2287 case PPC_RELOC_HI16: 2288 buf[2] = val >> 24; 2289 buf[3] = val >> 16; 2290 break; 2291 2292 case PPC_RELOC_LO16: 2293 buf[2] = val >> 8; 2294 buf[3] = val; 2295 break; 2296 2297 case PPC_RELOC_HA16: 2298 val += 0x00008000; 2299 buf[2] = val >> 24; 2300 buf[3] = val >> 16; 2301 break; 2302 2303 case PPC_RELOC_LO14: 2304 buf[2] = val >> 8; 2305 buf[3] |= val & 0xfc; 2306 break; 2307 2308 case PPC_RELOC_BR14: 2309 case PPC_RELOC_BR14_predicted: 2310 if(fixP->fx_pcrel) 2311 val += 4; 2312 if((val & 0xffff8000) && ((val & 0xffff8000) != 0xffff8000)){ 2313 layout_file = fixP->file; 2314 layout_line = fixP->line; 2315 as_bad("Fixup of %lld too large for field width of 16 " 2316 "bits", val); 2317 } 2318 if((val & 0x3) != 0){ 2319 layout_file = fixP->file; 2320 layout_line = fixP->line; 2321 as_bad("Fixup of %lld is not to a 4 byte address", val); 2322 } 2323 /* 2324 * Note PPC_RELOC_BR14 are only used with bc, "branch conditional" 2325 * instructions. The Y_BIT was previously set assuming the 2326 * displacement is non-negitive. If the displacement is negitive 2327 * then the Y_BIT is flipped if the prediction was specified (the 2328 * reloc type is PPC_RELOC_BR14_predicted). If the prediction was 2329 * not specified (the reloc type is PPC_RELOC_BR14) then the bit 2330 * must remain cleared as per the PowerPC book. 2331 */ 2332 if((val & 0x00008000) != 0){ 2333 opcode = buf[0] << 24 | buf[1] << 16 | buf[2] << 8 | buf[3]; 2334 /* 2335 * The 5-bit BO encoding of branch always is 1z1zz. Where z is 2336 * ignored but should be set to zero. If the user as specified 2337 * the BO "branch always" value with some of the z bits on then 2338 * treat it like a branch always and don't change the Y bit 2339 * based on the sign of the displacement. 2340 */ 2341 if(((opcode) & 0x02800000) != 0x02800000){ 2342 if(fixP->fx_r_type == PPC_RELOC_BR14_predicted) 2343 opcode ^= Y_BIT; 2344 buf[0] = opcode >> 24; 2345 buf[1] = opcode >> 16; 2346 buf[2] = opcode >> 8; 2347 buf[3] = opcode; 2348 } 2349 } 2350 buf[2] = val >> 8; 2351 buf[3] |= val & 0xfc; 2352 break; 2353 2354 case PPC_RELOC_BR24: 2355 if(fixP->fx_pcrel) 2356 val += 4; 2357 if((val & 0xfc000000) && ((val & 0xfc000000) != 0xfc000000)){ 2358 layout_file = fixP->file; 2359 layout_line = fixP->line; 2360 as_bad("Fixup of %lld too large for field width of 26 " 2361 "bits", val); 2362 } 2363 if((val & 0x3) != 0){ 2364 layout_file = fixP->file; 2365 layout_line = fixP->line; 2366 as_bad("Fixup of %lld is not to a 4 byte address", val); 2367 } 2368 buf[0] |= (val >> 24) & 0x03; 2369 buf[1] = val >> 16; 2370 buf[2] = val >> 8; 2371 buf[3] |= val & 0xfc; 2372 break; 2373 2374 case PPC_RELOC_JBSR: 2375 /* no bytes are written for JBSR, only a relocation entry */ 2376 break; 2377 2378 default: 2379 layout_file = fixP->file; 2380 layout_line = fixP->line; 2381 as_bad("Bad relocation type"); 2382 break; 2383 } 2384} 2385 2386/* 2387 * md_atof() turns a string pointed to by input_line_pointer into a floating 2388 * point constant of type type, and store the appropriate bytes in *litP. 2389 * The number of LITTLENUMS emitted is stored indirectly through *sizeP. 2390 * An error message is returned, or a string containg only a '\0' for OK. 2391 * For this machine only IEEE single and IEEE double floating-point formats 2392 * are allowed. 2393 */ 2394char * 2395md_atof( 2396int type, 2397char *litP, 2398int *sizeP) 2399{ 2400 int prec; 2401 LITTLENUM_TYPE words[6]; 2402 LITTLENUM_TYPE *wordP; 2403 char *t; 2404 2405 switch(type){ 2406 case 'f': 2407 case 'F': 2408 case 's': 2409 case 'S': 2410 prec = 2; 2411 break; 2412 2413 case 'd': 2414 case 'D': 2415 case 'r': 2416 case 'R': 2417 prec = 4; 2418 break; 2419 2420 default: 2421 *sizeP = 0; 2422 return("Bad call to MD_ATOF()"); 2423 } 2424 t = atof_ieee(input_line_pointer, type, words); 2425 if(t != NULL) 2426 input_line_pointer = t; 2427 2428 *sizeP = prec * sizeof(LITTLENUM_TYPE); 2429 for(wordP = words; prec--; ){ 2430 md_number_to_chars(litP, (int32_t)(*wordP++), sizeof(LITTLENUM_TYPE)); 2431 litP += sizeof(LITTLENUM_TYPE); 2432 } 2433 return ""; /* OK */ 2434} 2435 2436int 2437md_estimate_size_before_relax( 2438fragS *fragP, 2439int segment_type) 2440{ 2441 as_bad("Relaxation should never occur"); 2442 return(sizeof(int32_t)); 2443} 2444 2445const relax_typeS md_relax_table[] = { {0} }; 2446 2447void 2448md_convert_frag( 2449fragS *fragP) 2450{ 2451 as_bad("Relaxation should never occur"); 2452} 2453