1#undef CHECK_WORD_IMMEDIATES /* bug #26863 */ 2 3/* m68k.c All the m68020 specific stuff in one convenient, huge, 4 slow to compile, easy to find file. 5 Copyright (C) 1987 Free Software Foundation, Inc. 6 7This file is part of GAS, the GNU Assembler. 8 9GAS is free software; you can redistribute it and/or modify 10it under the terms of the GNU General Public License as published by 11the Free Software Foundation; either version 1, or (at your option) 12any later version. 13 14GAS is distributed in the hope that it will be useful, 15but WITHOUT ANY WARRANTY; without even the implied warranty of 16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17GNU General Public License for more details. 18 19You should have received a copy of the GNU General Public License 20along with GAS; see the file COPYING. If not, write to 21the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ 22 23#include <stdio.h> 24#include <stdlib.h> 25#include <string.h> 26#include <ctype.h> 27#include "m68k-opcode.h" 28#include "as.h" 29#include "obstack.h" 30#include "struc-symbol.h" 31#include "flonum.h" 32#include "expr.h" 33#include "hash.h" 34#include "frags.h" 35#include "fixes.h" 36#include "read.h" 37#include "md.h" 38#ifndef NeXT_MOD 39#include "m68k.h" 40#endif /* NeXT_MOD */ 41#include "xmalloc.h" 42#include "sections.h" 43#include "messages.h" 44#include "atof-ieee.h" 45#include "input-scrub.h" 46#include "symbols.h" 47 48/* 49 * These are the default cputype and cpusubtype for the m68k architecture. 50 */ 51const cpu_type_t md_cputype = CPU_TYPE_MC680x0; 52cpu_subtype_t md_cpusubtype = CPU_SUBTYPE_MC680x0_ALL; 53 54/* This is the byte sex for the m68k architecture */ 55const enum byte_sex md_target_byte_sex = BIG_ENDIAN_BYTE_SEX; 56 57/* 58 * This array holds the chars that always start a comment. If the 59 * pre-processor is disabled, these aren't very useful. 60 */ 61const char md_comment_chars[] = "|"; 62 63/* 64 * This array holds the chars that only start a comment at the beginning of 65 * a line. If the line seems to have the form '# 123 filename' 66 * .line and .file directives will appear in the pre-processed output. 67 * 68 * Note that input_file.c hand checks for '#' at the beginning of the 69 * first line of the input file. This is because the compiler outputs 70 * #NO_APP at the beginning of its output. 71 * 72 * Also note that a '/' followed by a '*' will always start a comment. 73 */ 74const char md_line_comment_chars[] = "#"; 75 76/* Chars that can be used to separate mant from exp in floating point nums. */ 77const char md_EXP_CHARS[] = "eE"; 78 79/* 80 * Chars that mean this number is a floating point constant. 81 * As in 0f12.456 82 * or 0d1.2345e12 83 * 84 * Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be 85 * changed in read.c . Ideally it shouldn't have to know about it at all, 86 * but nothing is ideal around here. 87 */ 88const char md_FLT_CHARS[] = "rRsSfFdDxXeEpP"; 89 90/* Its an arbitrary name: This means I don't approve of it */ 91/* See flames below */ 92static struct obstack robyn; 93 94/* 95 * These macros are used to encode a mode for the rlx_more field of the struct 96 * relax_typeS in the array md_relax_table below. The array is indexed by a 97 * TAB(x,y) value where x is one of BRANCH, FBRANCH, ... and y is BYTE, SHORT, 98 * ... Thus the array md_relax_table below is declared to match this use of 99 * indexes. The macro TABTYPE(xy) take the value and returns one of BRANCH, 100 * FBRANCH, ... 101 */ 102#define TAB(x,y) (((x)<<2)+(y)) 103#define TABTYPE(xy) ((xy) >> 2) 104 105#define BRANCH 1 106#define FBRANCH 2 107#define PCREL 3 108#define BCC68000 4 109#define DBCC 5 110 111#define BYTE 0 112#define SHORT 1 113#define LONG 2 114#define SZ_UNDEF 3 115 116/* 117 * BCC68000 is for patching in an extra jmp instruction for long offsets 118 * on the 68000. The 68000 doesn't support long branches with branchs. 119 */ 120 121/* 122 * Note that calls to frag_var need to specify the maximum expansion needed. 123 * This is currently 10 bytes for DBCC. 124 */ 125 126/* 127 * This table desribes how you change sizes for the various types of variable 128 * size expressions. This version only supports two kinds. 129 * The fields are: 130 * How far Forward this mode will reach: 131 * How far Backward this mode will reach: 132 * How many bytes this mode will add to the size of the frag 133 * Which mode to go to if the offset won't fit in this one 134 */ 135const 136relax_typeS 137md_relax_table[] = { 138{ 1, 1, 0, 0 }, /* First entries aren't used */ 139{ 1, 1, 0, 0 }, /* For no good reason except */ 140{ 1, 1, 0, 0 }, /* that the VAX doesn't either */ 141{ 1, 1, 0, 0 }, 142 143{ (127), (-128), 0, TAB(BRANCH,SHORT)}, 144{ (32767), (-32768), 2, TAB(BRANCH,LONG) }, 145{ 0, 0, 4, 0 }, 146{ 1, 1, 0, 0 }, 147 148{ 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE */ 149{ (32767), (-32768), 2, TAB(FBRANCH,LONG)}, 150{ 0, 0, 4, 0 }, 151{ 1, 1, 0, 0 }, 152 153{ 1, 1, 0, 0 }, /* PCREL doesn't come BYTE */ 154{ (32767), (-32768), 2, TAB(PCREL,LONG)}, 155{ 0, 0, 4, 0 }, 156{ 1, 1, 0, 0 }, 157 158{ (127), (-128), 0, TAB(BCC68000,SHORT)}, 159{ (32767), (-32768), 2, TAB(BCC68000,LONG) }, 160{ 0, 0, 6, 0 }, /* jmp long space */ 161{ 1, 1, 0, 0 }, 162 163{ 1, 1, 0, 0 }, /* DBCC doesn't come BYTE */ 164{ (32767), (-32768), 2, TAB(DBCC,LONG) }, 165{ 0, 0, 10, 0 }, /* bra/jmp long space */ 166{ 1, 1, 0, 0 }, 167 168}; 169 170static void s_even( 171 uintptr_t value); 172static void s_proc( 173 uintptr_t value); 174 175/* 176 * These are the machine dependent pseudo-ops. These are included so 177 * the assembler can work on the output from the SUN C compiler, which 178 * generates these. 179 */ 180 181/* This table describes all the machine specific pseudo-ops the assembler 182 * has to support. The fields are: 183 * pseudo-op name without dot 184 * function to call to execute this pseudo-op 185 * Integer arg to pass to the function 186 */ 187const pseudo_typeS md_pseudo_table[] = { 188 { "float", float_cons, 'f' }, 189 { "int", cons, 4 }, 190 { "word", cons, 2 }, 191 { "quad", big_cons, 8 }, 192 { "octa", big_cons, 16 }, 193 { "even", s_even, 0 }, 194 { "skip", s_space, 0 }, 195 { "proc", s_proc, 0 }, 196 { 0, 0, 0 } 197}; 198 199#define issbyte(x) ((x)>=-128 && (x)<=127) 200#define isubyte(x) ((x)>=0 && (x)<=255) 201#define issword(x) ((x)>=-32768 && (x)<=32767) 202#define isuword(x) ((x)>=0 && (x)<=65535) 203 204#define isbyte(x) ((x)>=-128 && (x)<=255) 205#define isword(x) ((x)>=-32768 && (x)<=65535) 206#define islong(x) (1) 207 208/* Operands we can parse: (And associated modes) 209 210numb: 8 bit num 211numw: 16 bit num 212numl: 32 bit num 213dreg: data reg 0-7 214reg: address or data register 215areg: address register 216apc: address register, PC, ZPC or empty string 217num: 16 or 32 bit num 218num2: like num 219sz: w or l if omitted, l assumed 220scale: 1 2 4 or 8 if omitted, 1 assumed 221 2227.4 IMMED #num --> NUM 2230.? DREG dreg --> dreg 2241.? AREG areg --> areg 2252.? AINDR areg@ --> *(areg) 2263.? AINC areg@+ --> *(areg++) 2274.? ADEC areg@- --> *(--areg) 2285.? AOFF apc@(numw) --> *(apc+numw) -- empty string and ZPC not allowed here 2296.? AINDX apc@(num,reg:sz:scale) --> *(apc+num+reg*scale) 2306.? AINDX apc@(reg:sz:scale) --> same, with num=0 2316.? APODX apc@(num)@(num2,reg:sz:scale) --> *(*(apc+num)+num2+reg*scale) 2326.? APODX apc@(num)@(reg:sz:scale) --> same, with num2=0 2336.? AMIND apc@(num)@(num2) --> *(*(apc+num)+num2) (previous mode without an index reg) 2346.? APRDX apc@(num,reg:sz:scale)@(num2) --> *(*(apc+num+reg*scale)+num2) 2356.? APRDX apc@(reg:sz:scale)@(num2) --> same, with num=0 2367.0 ABSL num:sz --> *(num) 237 num --> *(num) (sz L assumed) 238*** MSCR otherreg --> Magic 239With -l option 2405.? AOFF apc@(num) --> *(apc+num) -- empty string and ZPC not allowed here still 241 242examples: 243 #foo #0x35 #12 244 d2 245 a4 246 a3@ 247 a5@+ 248 a6@- 249 a2@(12) pc@(14) 250 a1@(5,d2:w:1) @(45,d6:l:4) 251 pc@(a2) @(d4) 252 etc . . . 253 254 255#name@(numw) -->turn into PC rel mode 256apc@(num8,reg:sz:scale) --> *(apc+num8+reg*scale) 257 258*/ 259 260#define IMMED 1 261#define DREG 2 262#define AREG 3 263#define AINDR 4 264#define ADEC 5 265#define AINC 6 266#define AOFF 7 267#define AINDX 8 268#define APODX 9 269#define AMIND 10 270#define APRDX 11 271#define ABSL 12 272#define MSCR 13 273#define REGLST 14 274 275#define FAIL 0 276#define OK 1 277 278/* DATA and ADDR have to be contiguous, so that reg-DATA gives 0-7==data reg, 279 8-15==addr reg for operands that take both types */ 280#define DATA 1 /* 1- 8 == data registers 0-7 */ 281#define ADDR (DATA+8) /* 9-16 == address regs 0-7 */ 282#define FPREG (ADDR+8) /* 17-24 Eight FP registers */ 283#define COPNUM (FPREG+8) /* 25-32 Co-processor #1-#8 */ 284#undef PC 285#define PC (COPNUM+8) /* 33 Program counter */ 286#define ZPC (PC+1) /* 34 Hack for Program space, but 0 addressing */ 287#define SR (ZPC+1) /* 35 Status Reg */ 288#define CCR (SR+1) /* 36 Condition code Reg */ 289 290#define FPI (CCR+1) /* 37 floating-point instruction register */ 291#define FPS (FPI+1) /* 38 floating-point status register */ 292#define FPC (FPS+1) /* 39 floating-point condition register */ 293 294/* These have to be in order for the movec instruction to work. */ 295/* The comment above should read: All the registers that can be in a movec 296 instruction must be bounded by USP and MSP (or SRP if BUILTIN_MMUS is 297 defined) for the 'J' kind of operand to be checked correctly in m68_ip() */ 298#define USP (FPC+1) /* 40 User Stack Pointer */ 299#define ISP (USP+1) /* 41 Interrupt stack pointer */ 300#define SFC (ISP+1) /* 42 Source function control code register */ 301#define DFC (SFC+1) /* 43 Destination function code register */ 302#define CACR (DFC+1) /* 44 Cashe control register */ 303#define VBR (CACR+1) /* 45 wector base register */ 304#define CAAR (VBR+1) /* 46 Cashe address register */ 305#define MSP (CAAR+1) /* 47 Master stack pointer */ 306 307#ifdef BUILTIN_MMUS 308/* mc68040 mmu registers, can be used in a movec instruction */ 309#define ITT0 (MSP+1) /* 48 instruction transparent translation register 0 */ 310#define ITT1 (ITT0+1) /* 49 instruction transparent translation register 1 */ 311#define DTT0 (ITT1+1) /* 50 data transparent translation register 0 */ 312#define DTT1 (DTT0+1) /* 51 data transparent translation register 1 */ 313#define URP (DTT1+1) /* 53 user root pointer */ 314 315/* mc68030 and mc68040 mmu registers, can be used in a movec instruction */ 316#define MMUSR (URP+1) /* 52 MMU status register */ 317#define TC (MMUSR+1)/* 54 MMU translation control register */ 318#define SRP (TC+1) /* 55 supervisor root pointer */ 319 320/* mc68030 mmu registers, can't be used in a movec instruction (but rather in a 321 pmove instruction) */ 322#define CRP (SRP+1) /* 56 cpu root pointer */ 323#define TT0 (CRP+1) /* 57 transparent translation register 0 */ 324#define TT1 (TT0+1) /* 58 transparent translation register 0 */ 325 326/* mc68040 operands to cache instructions */ 327#define IC (TT1+1) /* 59 instruction cache */ 328#define DC (IC+1) /* 60 data cache */ 329#define BC (DC+1) /* 61 both instruction and data caches */ 330#endif /* BUILTIN_MMUS */ 331 332#ifdef m68851 333/* 334 * these defines should be in m68k.c but 335 * i put them here to keep all the m68851 stuff 336 * together -rab 337 * JF--Make sure these #s don't clash with the ones in m68k.c 338 * That would be BAD. 339 */ 340#define TC (MSP+1) /* 48 */ 341#define DRP (TC+1) /* 49 */ 342#define SRP (DRP+1) /* 50 */ 343#define CRP (SRP+1) /* 51 */ 344#define CAL (CRP+1) /* 52 */ 345#define VAL (CAL+1) /* 53 */ 346#define SCC (VAL+1) /* 54 */ 347#define AC (SCC+1) /* 55 */ 348#define BAD (AC+1) /* 56,57,58,59, 60,61,62,63 */ 349#define BAC (BAD+8) /* 64,65,66,67, 68,69,70,71 */ 350#define PSR (BAC+8) /* 72 */ 351#define PCSR (PSR+1) /* 73 */ 352#endif /* m68851 */ 353 354 355/* Note that COPNUM==processor #1 -- COPNUM+7==#8, which stores as 000 */ 356/* I think. . . */ 357 358#undef SP 359#define SP ADDR+7 360 361/* JF these tables here are for speed at the expense of size */ 362/* You can replace them with the #if 0 versions if you really 363 need space and don't mind it running a bit slower */ 364 365static char mklower_table[256]; 366#define mklower(c) (mklower_table[(unsigned char)(c)]) 367static char notend_table[256]; 368static char alt_notend_table[256]; 369#define notend(s) ( !(notend_table[(unsigned char)(*s)] || (*s==':' &&\ 370 alt_notend_table[(unsigned char)(s[1])]))) 371 372#if 0 373#define mklower(c) (isupper(c) ? tolower(c) : c) 374#endif 375 376 377struct m68k_exp { 378 char *e_beg; 379 char *e_end; 380 expressionS e_exp; 381 short e_siz; /* 0== default 1==short/byte 2==word 3==long */ 382}; 383 384/* Internal form of an operand. */ 385struct m68k_op { 386 char *error; /* Couldn't parse it */ 387 int mode; /* What mode this instruction is in. */ 388 uint32_t reg; /* Base register */ 389 struct m68k_exp *con1; 390 int ireg; /* Index register */ 391 int isiz; /* 0==unspec 1==byte(?) 2==short 3==long */ 392 int imul; /* Multipy ireg by this (1,2,4,or 8) */ 393 struct m68k_exp *con2; 394}; 395 396/* internal form of a 68020 instruction */ 397struct m68_it { 398 char *error; 399 char *args; /* list of opcode info */ 400 int numargs; 401 402#ifdef NeXT_MOD 403 char *cpus; 404#endif /* NeXT_MOD */ 405 int numo; /* Number of shorts in opcode */ 406 short opcode[11]; 407 408 struct m68k_op operands[6]; 409 410 int nexp; /* number of exprs in use */ 411 struct m68k_exp exprs[4]; 412 413 int nfrag; /* Number of frags we have to produce */ 414 struct { 415 int fragoff; /* Where in the current opcode[] the frag ends */ 416 symbolS *fadd; 417 int32_t foff; 418 int fragty; 419 } fragb[4]; 420 421 int nrel; /* Num of reloc strucs in use */ 422 struct { 423 int n; 424 symbolS *add, 425 *sub; 426 int32_t off; 427 char wid; 428 char pcrel; 429 } reloc[5]; /* Five is enough??? */ 430}; 431 432static struct m68_it the_ins; /* the instruction being assembled */ 433 434 435/* Macros for adding things to the m68_it struct */ 436 437#define addword(w) the_ins.opcode[the_ins.numo++]=(w) 438 439/* Like addword, but goes BEFORE general operands */ 440#define insop(w) {int z;\ 441 for(z=the_ins.numo;z>opcode->m_codenum;--z)\ 442 the_ins.opcode[z]=the_ins.opcode[z-1];\ 443 for(z=0;z<the_ins.nrel;z++)\ 444 the_ins.reloc[z].n+=2;\ 445 the_ins.opcode[opcode->m_codenum]=(w);\ 446 the_ins.numo++;\ 447} 448 449 450#define add_exp(beg,end) (\ 451 the_ins.exprs[the_ins.nexp].e_beg=(beg),\ 452 the_ins.exprs[the_ins.nexp].e_end=(end),\ 453 &the_ins.exprs[the_ins.nexp++]\ 454) 455 456 457/* The numo+1 kludge is so we can hit the low order byte of the prev word. Blecch*/ 458#define add_fix(width,exp,pc_rel) {\ 459 the_ins.reloc[the_ins.nrel].n= ((width)=='B') ? (the_ins.numo*2-1) : \ 460 (((width)=='b') ? ((the_ins.numo-1)*2) : (the_ins.numo*2));\ 461 the_ins.reloc[the_ins.nrel].add=adds((exp));\ 462 the_ins.reloc[the_ins.nrel].sub=subs((exp));\ 463 the_ins.reloc[the_ins.nrel].off=offs((exp));\ 464 the_ins.reloc[the_ins.nrel].wid=(width);\ 465 the_ins.reloc[the_ins.nrel++].pcrel=(pc_rel);\ 466} 467 468#define add_frag(add,off,type) {\ 469 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;\ 470 the_ins.fragb[the_ins.nfrag].fadd=(add);\ 471 the_ins.fragb[the_ins.nfrag].foff=(off);\ 472 the_ins.fragb[the_ins.nfrag++].fragty=(type);\ 473} 474 475#define isvar(exp) ((exp) && (adds(exp) || subs(exp))) 476 477#define seg(exp) ((exp)->e_exp.X_seg) 478#define adds(exp) ((exp)->e_exp.X_add_symbol) 479#define subs(exp) ((exp)->e_exp.X_subtract_symbol) 480#define offs(exp) ((exp)->e_exp.X_add_number) 481 482 483struct m68_incant { 484 char *m_operands; 485 uint32_t m_opcode; 486 short m_opnum; 487 short m_codenum; 488#ifdef NeXT_MOD 489 char *m_cpus; 490#endif /* NeXT_MOD */ 491 struct m68_incant *m_next; 492}; 493 494#define getone(x) ((((x)->m_opcode)>>16)&0xffff) 495#define gettwo(x) (((x)->m_opcode)&0xffff) 496 497/* 498 * Declarations static functions in this file. 499 */ 500static int m68k_reg_parse( 501 char **ccp); 502static int m68k_ip_op( 503 char *str, 504 struct m68k_op *opP); 505static int try_index( 506 char **s, 507 struct m68k_op *opP); 508static void m68_ip( 509 char *instring); 510static int get_regs( 511 int i, 512 struct m68k_op *opP, 513 char *str); 514static int reverse_16_bits( 515 int in); 516static int reverse_8_bits( 517 int in); 518static void install_operand( 519 int mode, 520 int val); 521static void install_gen_operand( 522 int mode, 523 int val); 524static char *crack_operand( 525 char *str, 526 struct m68k_op *opP); 527static int get_num( 528 struct m68k_exp *exp, 529 int ok); 530 531/* JF modified this to handle cases where the first part of a symbol name 532 looks like a register */ 533 534static 535int 536m68k_reg_parse( 537char **ccp) 538{ 539 register char c1, 540 c2, 541 c3, 542 c4; 543#ifdef BUILTIN_MMUS 544 char c5; 545#endif 546 register int n = 0, 547 ret = 0; 548 549 c1=mklower(ccp[0][0]); 550 c2=mklower(ccp[0][1]); 551 c3=mklower(ccp[0][2]); 552 c4=mklower(ccp[0][3]); 553#ifdef BUILTIN_MMUS 554 c5=mklower(ccp[0][4]); 555#endif 556 557 switch(c1) { 558 case 'a': 559 if(c2>='0' && c2<='7') { 560 n=2; 561 ret=ADDR+c2-'0'; 562 } 563#ifdef m68851 564 else if (c2 == 'c') { 565 n = 2; 566 ret = AC; 567 } 568#endif 569 break; 570#ifdef m68851 571 case 'b': 572 if (c2 == 'a') { 573 if (c3 == 'd') { 574 if (c4 >= '0' && c4 <= '7') { 575 n = 4; 576 ret = BAD + c4 - '0'; 577 } 578 } 579 if (c3 == 'c') { 580 if (c4 >= '0' && c4 <= '7') { 581 n = 4; 582 ret = BAC + c4 - '0'; 583 } 584 } 585 } 586 break; 587#endif 588#ifdef BUILTIN_MMUS 589 case 'b': 590 if (c2 == 'c') { 591 n = 2; 592 ret = (BC); 593 } 594 break; 595#endif 596 case 'c': 597#ifdef m68851 598 if (c2 == 'a' && c3 == 'l') { 599 n = 3; 600 ret = CAL; 601 } else 602#endif 603 /* This supports both CCR and CC as the ccr reg. */ 604 if(c2=='c' && c3=='r') { 605 n=3; 606 ret = CCR; 607 } else if(c2=='c') { 608 n=2; 609 ret = CCR; 610 } else if(c2=='a' && (c3=='a' || c3=='c') && c4=='r') { 611 n=4; 612 ret = c3=='a' ? CAAR : CACR; 613 } 614#if defined(m68851) || defined (BUILTIN_MMUS) 615 else if (c2 == 'r' && c3 == 'p') { 616 n = 3; 617 ret = (CRP); 618 } 619#endif 620 break; 621 case 'd': 622 if(c2>='0' && c2<='7') { 623 n=2; 624 ret = DATA+c2-'0'; 625 } else if(c2=='f' && c3=='c') { 626 n=3; 627 ret = DFC; 628 } 629#ifdef m68851 630 else if (c2 == 'r' && c3 == 'p') { 631 n = 3; 632 ret = (DRP); 633 } 634#endif 635#ifdef BUILTIN_MMUS 636 else if (c2 == 't' && c3 == 't' && (c4 == '0' || c4 == '1')) { 637 n = 4; 638 if(c4 == '0') 639 ret = (DTT0); 640 else 641 ret = (DTT1); 642 } 643 else if (c2 == 'c') { 644 n = 2; 645 ret = (DC); 646 } 647#endif 648 break; 649 case 'f': 650 if(c2=='p') { 651 if(c3>='0' && c3<='7') { 652 n=3; 653 ret = FPREG+c3-'0'; 654 if(c4==':') 655 ccp[0][3]=','; 656 } else if(c3=='i') { 657 n=3; 658 ret = FPI; 659 } else if(c3=='s') { 660 n= (c4 == 'r' ? 4 : 3); 661 ret = FPS; 662 } else if(c3=='c') { 663 n= (c4 == 'r' ? 4 : 3); 664 ret = FPC; 665 } 666 } 667 break; 668 case 'i': 669 if(c2=='s' && c3=='p') { 670 n=3; 671 ret = ISP; 672 } 673#ifdef BUILTIN_MMUS 674 else if (c2 == 't' && c3 == 't' && (c4 == '0' || c4 == '1')) { 675 n = 4; 676 if(c4 == '0') 677 ret = (ITT0); 678 else 679 ret = (ITT1); 680 } 681 else if (c2 == 'c') { 682 n = 2; 683 ret = (IC); 684 } 685#endif 686 break; 687 case 'm': 688 if(c2=='s' && c3=='p') { 689 n=3; 690 ret = MSP; 691 } 692#ifdef BUILTIN_MMUS 693 if(c2=='m' && c3=='u' && c4=='s' && c5=='r') { 694 n=5; 695 ret = MMUSR; 696 } 697#endif 698 break; 699 case 'p': 700 if(c2=='c') { 701#ifdef m68851 702 if(c3 == 's' && c4=='r') { 703 n=4; 704 ret = (PCSR); 705 } else 706#endif 707 { 708 n=2; 709 ret = PC; 710 } 711 } 712#ifdef m68851 713 else if (c2 == 's' && c3 == 'r') { 714 n = 3; 715 ret = (PSR); 716 } 717#endif 718#ifdef BUILTIN_MMUS 719 else if (c2 == 's' && c3 == 'r') { 720 n = 3; 721 ret = (MMUSR); 722 } 723#endif 724 break; 725 case 's': 726#if defined(m68851) || defined(BUILTIN_MMUS) 727 if (c2 == 'r' && c3 == 'p') { 728 n = 3; 729 ret = (SRP); 730 } 731#endif 732#ifdef m68851 733 else if (c2 == 'c' && c3 == 'c') { 734 n = 3; 735 ret = (SCC); 736 } 737#endif 738#if defined(m68851) || defined(BUILTIN_MMUS) 739 else 740#endif 741 if(c2=='r') { 742 n=2; 743 ret = SR; 744 } else if(c2=='p') { 745 n=2; 746 ret = ADDR+7; 747 } else if(c2=='f' && c3=='c') { 748 n=3; 749 ret = SFC; 750 } 751 break; 752#if defined(m68851) || defined(BUILTIN_MMUS) 753 case 't': 754 if(c2 == 'c') { 755 n=2; 756 ret=TC; 757 } 758#ifdef BUILTIN_MMUS 759 else if (c2 == 't' && (c3 == '0' || c3 == '1')) { 760 n = 3; 761 if(c3 == '0') 762 ret = (TT0); 763 else 764 ret = (TT1); 765 } 766#endif 767 break; 768#endif 769 case 'u': 770 if(c2=='s' && c3=='p') { 771 n=3; 772 ret = USP; 773 } 774#ifdef BUILTIN_MMUS 775 else if(c2=='r' && c3=='p') { 776 n=3; 777 ret = URP; 778 } 779#endif 780 break; 781 case 'v': 782#ifdef m68851 783 if (c2 == 'a' && c3 == 'l') { 784 n = 3; 785 ret = (VAL); 786 } else 787#endif 788 if(c2=='b' && c3=='r') { 789 n=3; 790 ret = VBR; 791 } 792 break; 793 case 'z': 794 if(c2=='p' && c3=='c') { 795 n=3; 796 ret = ZPC; 797 } 798 break; 799 default: 800 break; 801 } 802 if(n) { 803 if(isalnum(ccp[0][n]) || ccp[0][n]=='_') 804 ret=FAIL; 805 else 806 ccp[0]+=n; 807 } else 808 ret = FAIL; 809 return ret; 810} 811 812#define SKIP_WHITE() { str++; if(*str==' ') str++;} 813 814static 815int 816m68k_ip_op( 817char *str, 818struct m68k_op *opP) 819{ 820 char *strend; 821 int32_t i; 822 823 if(*str==' ') 824 str++; 825 /* Find the end of the string */ 826 if(!*str) { 827 /* Out of gas */ 828 opP->error="Missing operand"; 829 return FAIL; 830 } 831 for(strend=str;*strend;strend++) 832 ; 833 --strend; 834 835 /* Guess what: A constant. Shar and enjoy */ 836 if(*str=='#') { 837 str++; 838 opP->con1=add_exp(str,strend); 839 opP->mode=IMMED; 840 return OK; 841 } 842 i=m68k_reg_parse(&str); 843 if((i==FAIL || *str!='\0') && *str!='@') { 844 char *stmp; 845 846 if(i!=FAIL && (*str=='/' || *str=='-')) { 847 opP->mode=REGLST; 848 return get_regs(i,opP,str); 849 } 850 if((stmp=index(str,'@'))) { 851 opP->con1=add_exp(str,stmp-1); 852 if(stmp==strend) { 853 opP->mode=AINDX; 854 return OK; 855 } 856 stmp++; 857 if(*stmp++!='(' || *strend--!=')') { 858 opP->error="Malformed operand"; 859 return FAIL; 860 } 861 i=try_index(&stmp,opP); 862 opP->con2=add_exp(stmp,strend); 863 if(i==FAIL) opP->mode=AMIND; 864 else opP->mode=APODX; 865 return OK; 866 } 867 opP->mode=ABSL; 868 opP->con1=add_exp(str,strend); 869 return OK; 870 } 871 opP->reg=i; 872 if(*str=='\0') { 873 if(i>=DATA+0 && i<=DATA+7) 874 opP->mode=DREG; 875 else if(i>=ADDR+0 && i<=ADDR+7) 876 opP->mode=AREG; 877 else 878 opP->mode=MSCR; 879 return OK; 880 } 881 if((i<ADDR+0 || i>ADDR+7) && i!=PC && i!=ZPC && i!=FAIL) { /* Can't indirect off non address regs */ 882 opP->error="Invalid indirect register"; 883 return FAIL; 884 } 885 if(*str!='@') 886 abort(); 887 str++; 888 switch(*str) { 889 case '\0': 890 opP->mode=AINDR; 891 return OK; 892 case '-': 893 opP->mode=ADEC; 894 return OK; 895 case '+': 896 opP->mode=AINC; 897 return OK; 898 case '(': 899 str++; 900 break; 901 default: 902 opP->error="Junk after indirect"; 903 return FAIL; 904 } 905 /* Some kind of indexing involved. Lets find out how bad it is */ 906 i=try_index(&str,opP); 907 /* Didn't start with an index reg, maybe its offset or offset,reg */ 908 if(i==FAIL) { 909 char *beg_str; 910 911 beg_str=str; 912 for(i=1;i;) { 913 switch(*str++) { 914 case '\0': 915 opP->error="Missing )"; 916 return FAIL; 917 case ',': i=0; break; 918 case '(': i++; break; 919 case ')': --i; break; 920 } 921 } 922 opP->con1=add_exp(beg_str,str-2); 923 /* Should be offset,reg */ 924 if(str[-1]==',') { 925 i=try_index(&str,opP); 926 if(i==FAIL) { 927 opP->error="Malformed index reg"; 928 return FAIL; 929 } 930 } 931 } 932 /* We've now got offset) offset,reg) or reg) */ 933 934 if(*str=='\0') { 935 /* Th-the-thats all folks */ 936#ifdef NeXT_MOD 937 /* all forms using zpc must use pc@(bd,Xn) and not pc@(d16) because 938 you can only suppress the base register in the first form */ 939 if(opP->reg==FAIL || opP->reg==ZPC) opP->mode=AINDX; /* Other form of indirect */ 940#else /* !defined(NeXT_MOD) */ 941 if(opP->reg==FAIL) opP->mode=AINDX; /* Other form of indirect */ 942#endif /* NeXT_MOD */ 943 else if(opP->ireg==FAIL) opP->mode=AOFF; 944 else opP->mode=AINDX; 945 return OK; 946 } 947 /* Next thing had better be another @ */ 948 if(*str!='@' || str[1]!='(') { 949 opP->error="junk after indirect"; 950 return FAIL; 951 } 952 str+=2; 953 if(opP->ireg!=FAIL) { 954 opP->mode=APRDX; 955 i=try_index(&str,opP); 956 if(i!=FAIL) { 957 opP->error="Two index registers! not allowed!"; 958 return FAIL; 959 } 960 } else 961 i=try_index(&str,opP); 962 if(i==FAIL) { 963 char *beg_str; 964 965 beg_str=str; 966 for(i=1;i;) { 967 switch(*str++) { 968 case '\0': 969 opP->error="Missing )"; 970 return FAIL; 971 case ',': i=0; break; 972 case '(': i++; break; 973 case ')': --i; break; 974 } 975 } 976 opP->con2=add_exp(beg_str,str-2); 977 if(str[-1]==',') { 978 if(opP->ireg!=FAIL) { 979 opP->error="Can't have two index regs"; 980 return FAIL; 981 } 982 i=try_index(&str,opP); 983 if(i==FAIL) { 984 opP->error="malformed index reg"; 985 return FAIL; 986 } 987 opP->mode=APODX; 988 } else if(opP->ireg!=FAIL) 989 opP->mode=APRDX; 990 else 991 opP->mode=AMIND; 992 } else 993 opP->mode=APODX; 994 if(*str!='\0') { 995 opP->error="Junk after indirect"; 996 return FAIL; 997 } 998 return OK; 999} 1000 1001static 1002int 1003try_index( 1004char **s, 1005struct m68k_op *opP) 1006{ 1007 register int i; 1008 char *ss; 1009#define SKIP_W() { ss++; if(*ss==' ') ss++;} 1010 1011 ss= *s; 1012 /* SKIP_W(); */ 1013 i=m68k_reg_parse(&ss); 1014 if(!(i>=DATA+0 && i<=ADDR+7)) { /* if i is not DATA or ADDR reg */ 1015 *s=ss; 1016 return FAIL; 1017 } 1018 opP->ireg=i; 1019 /* SKIP_W(); */ 1020 if(*ss==')') { 1021 opP->isiz=0; 1022 opP->imul=1; 1023 SKIP_W(); 1024 *s=ss; 1025 return OK; 1026 } 1027 if(*ss!=':') { 1028 opP->error="Missing : in index register"; 1029 *s=ss; 1030 return FAIL; 1031 } 1032 SKIP_W(); 1033 if(mklower(*ss)=='w') opP->isiz=2; 1034 else if(mklower(*ss)=='l') opP->isiz=3; 1035 else { 1036 opP->error="Size spec not :w or :l"; 1037 *s=ss; 1038 return FAIL; 1039 } 1040 SKIP_W(); 1041 if(*ss==':') { 1042 SKIP_W(); 1043 switch(*ss) { 1044 case '1': 1045 case '2': 1046 case '4': 1047 case '8': 1048 opP->imul= *ss-'0'; 1049 break; 1050 default: 1051 opP->error="index multiplier not 1, 2, 4 or 8"; 1052 *s=ss; 1053 return FAIL; 1054 } 1055 SKIP_W(); 1056 } else opP->imul=1; 1057 if(*ss!=')') { 1058 opP->error="Missing )"; 1059 *s=ss; 1060 return FAIL; 1061 } 1062 SKIP_W(); 1063 *s=ss; 1064 return OK; 1065} 1066 1067#ifdef TEST1 /* TEST1 tests m68k_ip_op(), which parses operands */ 1068void 1069main( 1070int argc, 1071char *argv[], 1072char *envp[]) 1073{ 1074 char buf[128]; 1075 struct m68k_op thark; 1076 1077 for(;;){ 1078 if(!gets(buf)) 1079 break; 1080 memset(&thark, '\0', sizeof(thark)); 1081 if(!m68k_ip_op(buf, &thark)) 1082 printf("FAIL:"); 1083 if(thark.error) 1084 printf("op1 error %s in %s\n",thark.error,buf); 1085 printf("mode %d, reg %d, ",thark.mode,thark.reg); 1086 if(thark.con1) 1087 printf("con1: '%.*s',", 1088 1 + thark.con1->e_end - thark.con1->e_beg, 1089 thark.con1->e_beg); 1090 printf("ireg %d, isiz %d, imul %d ", 1091 thark.ireg, thark.isiz, thark.imul); 1092 if(thark.con2) 1093 printf("con2: '%.*s'", 1094 1 + thark.con2->e_end - thark.con2->e_beg, 1095 thark.con2->e_beg); 1096 printf("\n"); 1097 } 1098 exit(0); 1099} 1100#endif /* TEST1 */ 1101 1102 1103/* 1104 * Handle of the OPCODE hash table NULL means any use before m68_ip_begin() 1105 * will crash. 1106 */ 1107static struct hash_control *op_hash = NULL; 1108 1109 1110/* 1111 * m 6 8 _ i p ( ) 1112 * 1113 * This converts a string into a 68k instruction. 1114 * The string must be a bare single instruction in sun format 1115 * with RMS-style 68020 indirects 1116 * (example: ) 1117 * 1118 * It provides some error messages: at most one fatal error message (which 1119 * stops the scan) and at most one warning message for each operand. 1120 * The 68k instruction is returned in exploded form, since we have no 1121 * knowledge of how you parse (or evaluate) your expressions. 1122 * We do however strip off and decode addressing modes and operation 1123 * mnemonic. 1124 * 1125 * This function's value is a string. If it is not "" then an internal 1126 * logic error was found: read this code to assign meaning to the string. 1127 * No argument string should generate such an error string: 1128 * it means a bug in our code, not in the user's text. 1129 * 1130 * You MUST have called m86_ip_begin() once and m86_ip_end() never before using 1131 * this function. 1132 */ 1133 1134/* JF this function no longer returns a useful value. Sorry */ 1135static 1136void 1137m68_ip( 1138char *instring) 1139{ 1140 register char *p; 1141 register struct m68k_op *opP; 1142 register struct m68_incant *opcode; 1143 register char *s; 1144 register int tmpreg = 0, 1145 baseo = 0, 1146 outro = 0, 1147 nextword; 1148 int siz1, 1149 siz2; 1150 char c; 1151 int losing; 1152 int opsfound; 1153 LITTLENUM_TYPE words[6]; 1154 LITTLENUM_TYPE *wordp; 1155 1156 if (*instring == ' ') 1157 instring++; /* skip leading whitespace */ 1158 1159 /* Scan up to end of operation-code, which MUST end in end-of-string 1160 or exactly 1 space. */ 1161 for (p = instring; *p != '\0'; p++) 1162 if (*p == ' ') 1163 break; 1164 1165 1166 if (p == instring) { 1167 the_ins.error = "No operator"; 1168 the_ins.opcode[0] = 0; 1169 /* the_ins.numo=1; */ 1170 return; 1171 } 1172 1173 /* p now points to the end of the opcode name, probably whitespace. 1174 make sure the name is null terminated by clobbering the whitespace, 1175 look it up in the hash table, then fix it back. */ 1176 c = *p; 1177 *p = '\0'; 1178 opcode = (struct m68_incant *)hash_find (op_hash, instring); 1179 *p = c; 1180 1181 if (opcode == NULL) { 1182 the_ins.error = "Unknown operator"; 1183 the_ins.opcode[0] = 0; 1184 /* the_ins.numo=1; */ 1185 return; 1186 } 1187 1188 /* found a legitimate opcode, start matching operands */ 1189 for(opP= &the_ins.operands[0];*p;opP++) { 1190 p = crack_operand (p, opP); 1191 if(opP->error) { 1192 the_ins.error=opP->error; 1193 return; 1194 } 1195 } 1196 1197 opsfound=opP- &the_ins.operands[0]; 1198 /* This ugly hack is to support the floating pt opcodes in their standard form */ 1199 /* Essentially, we fake a first enty of type COP#1 */ 1200 if(opcode->m_operands[0]=='I') { 1201 int n; 1202 1203 for(n=opsfound;n>0;--n) 1204 the_ins.operands[n]=the_ins.operands[n-1]; 1205 1206 /* bcopy((char *)(&the_ins.operands[0]),(char *)(&the_ins.operands[1]),opsfound*sizeof(the_ins.operands[0])); */ 1207 memset((char *)(&the_ins.operands[0]), '\0', 1208 sizeof(the_ins.operands[0])); 1209 the_ins.operands[0].mode=MSCR; 1210 the_ins.operands[0].reg=COPNUM; /* COP #1 */ 1211 opsfound++; 1212 } 1213 /* We've got the operands. Find an opcode that'll 1214 accept them */ 1215 for(losing=0;;) { 1216 if(opsfound!=opcode->m_opnum) 1217 losing++; 1218 else for(s=opcode->m_operands,opP= &the_ins.operands[0];*s && !losing;s+=2,opP++) { 1219 /* Warning: this switch is huge! */ 1220 /* I've tried to organize the cases into this order: 1221 non-alpha first, then alpha by letter. lower-case goes directly 1222 before uppercase counterpart. */ 1223 /* Code with multiple case ...: gets sorted by the lowest case ... 1224 it belongs to. I hope this makes sense. */ 1225 switch(*s) { 1226 case '!': 1227 if(opP->mode==MSCR || opP->mode==IMMED || 1228 opP->mode==DREG || opP->mode==AREG || opP->mode==AINC || opP->mode==ADEC || opP->mode==REGLST) 1229 losing++; 1230 break; 1231 1232 case '#': 1233 if(opP->mode!=IMMED) 1234 losing++; 1235 else { 1236 int32_t t; 1237 1238 t=get_num(opP->con1,80); 1239 if(s[1]=='b' && !isbyte(t)) 1240 losing++; 1241#ifdef CHECK_WORD_IMMEDIATES 1242 else if((s[1]=='w' || s[1]=='z') && 1243 !isword(t)) 1244 losing++; 1245#else 1246 else if(s[1]=='z' && !isword(t)) 1247 losing++; 1248#endif 1249 } 1250 break; 1251 1252 case '^': 1253 case 'T': 1254 if(opP->mode!=IMMED) 1255 losing++; 1256 break; 1257 1258 case '$': 1259 if(opP->mode==MSCR || opP->mode==AREG || 1260 opP->mode==IMMED || opP->reg==PC || opP->reg==ZPC || opP->mode==REGLST) 1261 losing++; 1262 break; 1263 1264 case '%': 1265 if(opP->mode==MSCR || opP->reg==PC || 1266 opP->reg==ZPC || opP->mode==REGLST) 1267 losing++; 1268 break; 1269 1270 1271 case '&': 1272 if(opP->mode==MSCR || opP->mode==DREG || 1273 opP->mode==AREG || opP->mode==IMMED || opP->reg==PC || opP->reg==ZPC || 1274 opP->mode==AINC || opP->mode==ADEC || opP->mode==REGLST) 1275 losing++; 1276 break; 1277 1278 case '*': 1279 if(opP->mode==MSCR || opP->mode==REGLST) 1280 losing++; 1281 break; 1282 1283 case '+': 1284 if(opP->mode!=AINC) 1285 losing++; 1286 break; 1287 1288 case '-': 1289 if(opP->mode!=ADEC) 1290 losing++; 1291 break; 1292 1293#ifdef NeXT_MOD 1294 case '0': 1295 if(opP->mode!=AINDR) 1296 losing++; 1297 break; 1298#endif /* NeXT_MOD */ 1299 1300 case '/': 1301 if(opP->mode==MSCR || opP->mode==AREG || 1302 opP->mode==AINC || opP->mode==ADEC || opP->mode==IMMED || opP->mode==REGLST) 1303 losing++; 1304 break; 1305 1306 case ';': 1307 if(opP->mode==MSCR || opP->mode==AREG || opP->mode==REGLST) 1308 losing++; 1309 break; 1310 1311 case '?': 1312 if(opP->mode==MSCR || opP->mode==AREG || 1313 opP->mode==AINC || opP->mode==ADEC || opP->mode==IMMED || opP->reg==PC || 1314 opP->reg==ZPC || opP->mode==REGLST) 1315 losing++; 1316 break; 1317 1318 case '@': 1319 if(opP->mode==MSCR || opP->mode==AREG || 1320 opP->mode==IMMED || opP->mode==REGLST) 1321 losing++; 1322 break; 1323 1324 case '~': /* For now! (JF FOO is this right?) */ 1325 if(opP->mode==MSCR || opP->mode==DREG || 1326 opP->mode==AREG || opP->mode==IMMED || opP->reg==PC || opP->reg==ZPC || opP->mode==REGLST) 1327 losing++; 1328 break; 1329 1330 case 'A': 1331 if(opP->mode!=AREG) 1332 losing++; 1333 break; 1334 1335 case 'B': /* FOO */ 1336 if(opP->mode!=ABSL) 1337 losing++; 1338 break; 1339 1340 case 'C': 1341 if(opP->mode!=MSCR || opP->reg!=CCR) 1342 losing++; 1343 break; 1344 1345 case 'd': /* FOO This mode is a KLUDGE!! */ 1346 if(opP->mode!=AOFF && (opP->mode!=ABSL || 1347 opP->con1->e_beg[0]!='(' || opP->con1->e_end[0]!=')')) 1348 losing++; 1349 break; 1350 1351 case 'D': 1352 if(opP->mode!=DREG) 1353 losing++; 1354 break; 1355 1356 case 'F': 1357 if(opP->mode!=MSCR || opP->reg<(FPREG+0) || opP->reg>(FPREG+7)) 1358 losing++; 1359 break; 1360 1361 case 'I': 1362 if(opP->mode!=MSCR || opP->reg<COPNUM || 1363 opP->reg>=COPNUM+7) 1364 losing++; 1365 break; 1366 1367 case 'J': 1368#ifdef BUILTIN_MMUS 1369 if(opP->mode!=MSCR || opP->reg<USP || opP->reg>SRP) 1370#else 1371 if(opP->mode!=MSCR || opP->reg<USP || opP->reg>MSP) 1372#endif 1373 losing++; 1374 break; 1375 1376 case 'k': 1377 if(opP->mode!=IMMED) 1378 losing++; 1379 break; 1380 1381 case 'l': 1382 case 'L': 1383 if(opP->mode==DREG || opP->mode==AREG || opP->mode==FPREG) { 1384 if(s[1]=='8') 1385 losing++; 1386 else { 1387 opP->mode=REGLST; 1388 opP->reg=1<<(opP->reg-DATA); 1389 } 1390 } else if(opP->mode!=REGLST) { 1391 losing++; 1392 } else if(s[1]=='8' && opP->reg&0x0FFffFF) 1393 losing++; 1394 else if(s[1]=='3' && opP->reg&0x7000000) 1395 losing++; 1396 break; 1397 1398 case 'M': 1399 if(opP->mode!=IMMED) 1400 losing++; 1401 else { 1402 int32_t t; 1403 1404 t=get_num(opP->con1,80); 1405#ifdef NeXT_MOD /* feature to try to make expressions absolute */ 1406 /* DJA -- Bug fix. allow absolute expressions */ 1407 if(! (issbyte(t) && seg(opP->con1)==SEG_ABSOLUTE) ) 1408#else /* !defined(NeXT_MOD) */ 1409 if(!issbyte(t) || isvar(opP->con1)) 1410#endif /* NeXT_MOD */ 1411 losing++; 1412 } 1413 break; 1414 1415 case 'O': 1416 if(opP->mode!=DREG && opP->mode!=IMMED) 1417 losing++; 1418 break; 1419 1420 case 'Q': 1421 if(opP->mode!=IMMED) 1422 losing++; 1423 else { 1424 int32_t t; 1425 1426 t=get_num(opP->con1,80); 1427 if(t<1 || t>8 || isvar(opP->con1)) 1428 losing++; 1429 } 1430 break; 1431 1432 case 'R': 1433 if(opP->mode!=DREG && opP->mode!=AREG) 1434 losing++; 1435 break; 1436 1437 case 's': 1438 if(opP->mode!=MSCR || !(opP->reg==FPI || opP->reg==FPS || opP->reg==FPC)) 1439 losing++; 1440 break; 1441 1442 case 'S': 1443 if(opP->mode!=MSCR || opP->reg!=SR) 1444 losing++; 1445 break; 1446 1447 case 'U': 1448 if(opP->mode!=MSCR || opP->reg!=USP) 1449 losing++; 1450 break; 1451 1452 /* JF these are out of order. We could put them 1453 in order if we were willing to put up with 1454 bunches of #ifdef m68851s in the code */ 1455#ifdef m68851 1456 /* Memory addressing mode used by pflushr */ 1457 case '|': 1458 if(opP->mode==MSCR || opP->mode==DREG || 1459 opP->mode==AREG || opP->mode==REGLST) 1460 losing++; 1461 break; 1462#endif 1463 1464#if defined(m68851) || defined(BUILTIN_MMUS) 1465 case 'f': 1466 if (opP->mode != MSCR || (opP->reg != SFC && opP->reg != DFC)) 1467 losing++; 1468 break; 1469#endif 1470 1471#ifdef m68851 1472 case 'P': 1473 if (opP->mode != MSCR || (opP->reg != TC && opP->reg != CAL && 1474 opP->reg != VAL && opP->reg != SCC && opP->reg != AC)) 1475 losing++; 1476 break; 1477 1478 case 'V': 1479 if (opP->reg != VAL) 1480 losing++; 1481 break; 1482 1483 case 'W': 1484 if (opP->mode != MSCR || (opP->reg != DRP && opP->reg != SRP && 1485 opP->reg != CRP)) 1486 losing++; 1487 break; 1488 1489 case 'X': 1490 if (opP->mode != MSCR || 1491 (!(opP->reg >= BAD && opP->reg <= BAD+7) && 1492 !(opP->reg >= BAC && opP->reg <= BAC+7))) 1493 losing++; 1494 break; 1495 1496 case 'Y': 1497 if (opP->reg != PSR) 1498 losing++; 1499 break; 1500 1501 case 'Z': 1502 if (opP->reg != PCSR) 1503 losing++; 1504 break; 1505#endif 1506#ifdef BUILTIN_MMUS 1507 case 'a': 1508 if ((opP->mode != MSCR) || (opP->reg != SRP && 1509 opP->reg != CRP && opP->reg != TC)) 1510 losing++; 1511 break; 1512 case 'b': 1513 if (opP->mode != MSCR || opP->reg != MMUSR) 1514 losing++; 1515 break; 1516 case 'c': 1517 if ((opP->mode != MSCR) || (opP->reg != IC && 1518 opP->reg != DC && opP->reg != BC)) 1519 losing++; 1520 break; 1521 case 'e': 1522 if ((opP->mode != MSCR) || (opP->reg != TT0 && 1523 opP->reg != TT1)) 1524 losing++; 1525 break; 1526#endif 1527 default: 1528 as_fatal("Internal error: Operand mode %c unknown",*s); 1529 } 1530 } 1531 if(!losing) 1532 break; 1533 opcode=opcode->m_next; 1534 if(!opcode) { /* Fell off the end */ 1535 the_ins.error="instruction/operands mismatch"; 1536 return; 1537 } 1538 losing=0; 1539 } 1540 the_ins.args=opcode->m_operands; 1541 the_ins.numargs=opcode->m_opnum; 1542 the_ins.numo=opcode->m_codenum; 1543 the_ins.opcode[0]=getone(opcode); 1544 the_ins.opcode[1]=gettwo(opcode); 1545#ifdef NeXT_MOD 1546 the_ins.cpus=opcode->m_cpus; 1547#endif /* NeXT_MOD */ 1548 1549 for(s=the_ins.args,opP= &the_ins.operands[0];*s;s+=2,opP++) { 1550 /* This switch is a doozy. 1551 What the first step; its a big one! */ 1552 switch(s[0]) { 1553 1554 case '*': 1555 case '~': 1556 case '%': 1557 case ';': 1558 case '@': 1559 case '!': 1560 case '&': 1561 case '$': 1562 case '?': 1563 case '/': 1564#ifdef m68851 1565 case '|': 1566#endif 1567 switch(opP->mode) { 1568 case IMMED: 1569 tmpreg=0x3c; /* 7.4 */ 1570 if(index("bwzl",s[1])) 1571 nextword=get_num(opP->con1,80); 1572 else 1573 nextword=get_num(opP->con1,0); 1574 if(isvar(opP->con1)) 1575 add_fix(s[1],opP->con1,0); 1576 switch(s[1]) { 1577 case 'b': 1578 if(!isbyte(nextword)) 1579 opP->error="operand out of range"; 1580 addword(nextword); 1581 baseo=0; 1582 break; 1583 case 'w': 1584 case 'z': 1585#ifdef CHECK_WORD_IMMEDIATES 1586 if(!isword(nextword)) 1587 opP->error="operand out of range"; 1588#endif 1589 addword(nextword); 1590 baseo=0; 1591 break; 1592#ifdef NeXT_MOD /* Used in the fmoveml (control) registers */ 1593 case 's': 1594#endif /* NeXT_MOD */ 1595 case 'l': 1596 addword(nextword>>16); 1597 addword(nextword); 1598 baseo=0; 1599 break; 1600 1601 case 'f': 1602 baseo=2; 1603 outro=8; 1604 break; 1605 case 'F': 1606 baseo=4; 1607 outro=11; 1608 break; 1609 case 'x': 1610 baseo=6; 1611 outro=15; 1612 break; 1613#ifdef PACKED_IMMEDIATE 1614/* This does not work. The call to gen_to_words() below does not put out 1615 68k packed decimal format. */ 1616 case 'p': 1617 baseo=6; 1618 outro= -1; 1619 break; 1620#endif 1621 default: 1622 as_fatal("Internal error: Can't decode %c%c",*s,s[1]); 1623 } 1624 if(!baseo) 1625 break; 1626 1627 /* We gotta put out some float */ 1628 if(seg(opP->con1)!=SEG_BIG) { 1629 int_to_gen(nextword); 1630 gen_to_words(words,baseo,(int32_t)outro); 1631 for(wordp=words;baseo--;wordp++) 1632 addword(*wordp); 1633 break; 1634 } /* Its BIG */ 1635 if(offs(opP->con1)>0) { 1636#ifndef NeXT_MOD /* fix for bug #8331 */ 1637 as_warn("Bignum assumed to be binary bit-pattern"); 1638#endif /* NeXT_MOD */ 1639 if(offs(opP->con1)>baseo) { 1640 as_warn("Bignum too big for %c format; truncated",s[1]); 1641 offs(opP->con1)=baseo; 1642 } 1643 baseo-=offs(opP->con1); 1644 for(wordp=generic_bignum+offs(opP->con1)-1;offs(opP->con1)--;--wordp) 1645 addword(*wordp); 1646 while(baseo--) 1647 addword(0); 1648 break; 1649 } 1650 gen_to_words(words,baseo,(int32_t)outro); 1651 for(wordp=words;baseo--;wordp++) 1652 addword(*wordp); 1653 break; 1654 case DREG: 1655 tmpreg=opP->reg-DATA; /* 0.dreg */ 1656 break; 1657 case AREG: 1658 tmpreg=0x08+opP->reg-ADDR; /* 1.areg */ 1659 break; 1660 case AINDR: 1661#ifdef NeXT_MOD 1662 /* fixes "pc@" operand */ 1663 if(opP->reg==PC){ 1664 tmpreg=0x3A; /* 7.2 */ 1665 addword(0x0000); 1666 } 1667 else 1668#endif /* NeXT_MOD */ 1669 tmpreg=0x10+opP->reg-ADDR; /* 2.areg */ 1670 break; 1671 case ADEC: 1672 tmpreg=0x20+opP->reg-ADDR; /* 4.areg */ 1673 break; 1674 case AINC: 1675 tmpreg=0x18+opP->reg-ADDR; /* 3.areg */ 1676 break; 1677 case AOFF: 1678 if(opP->reg==PC) 1679 tmpreg=0x3A; /* 7.2 */ 1680 else 1681 tmpreg=0x28+opP->reg-ADDR; /* 5.areg */ 1682 nextword=get_num(opP->con1,80); 1683 /* Force into index mode. Hope this works */ 1684 if(!issword(nextword)) { 1685 if(opP->reg==PC) 1686 tmpreg=0x3B; /* 7.3 */ 1687 else 1688 tmpreg=0x30+opP->reg-ADDR; /* 6.areg */ 1689 /* addword(0x0171); */ 1690/* 171 seems to be wrong, and I can't find the 68020 manual, so we'll try 170 1691 (which is what the Sun asm seems to generate */ 1692 addword(0x0170); 1693 if(isvar(opP->con1)) 1694 add_fix('l',opP->con1,0); 1695 addword(nextword>>16); 1696 /* addword(nextword); */ 1697 } else if(isvar(opP->con1)) { 1698 if(opP->reg==PC) 1699 tmpreg=0x3B; /* 7.3 */ 1700 else 1701 tmpreg=0x30+opP->reg-ADDR; 1702 addword(0x0170); 1703 /* 1704 * If this is a pc register with 1705 * a SEGDIFF where the -symbol 1706 * is "." adjust the value of 1707 * of "." to include the two 1708 * bytes of opcode. 1709 */ 1710 if(opP->reg==PC && 1711 seg(opP->con1) == SEG_DIFFSECT && 1712 opP->con1-> e_exp.X_subtract_symbol-> 1713 sy_frag == frag_now && 1714 strcmp(opP->con1-> 1715 e_exp.X_subtract_symbol->sy_name, 1716 "L0\001") == 0) 1717 opP->con1-> e_exp.X_subtract_symbol-> 1718 sy_nlist.n_value += 2; 1719 add_fix('l',opP->con1,0); 1720 addword(nextword>>16); 1721 } 1722 addword(nextword); 1723 break; 1724 case AINDX: 1725 case APODX: 1726 case AMIND: 1727 case APRDX: 1728 nextword=0; 1729 baseo=get_num(opP->con1,80); 1730 outro=get_num(opP->con2,80); 1731 /* Figure out the 'addressing mode' */ 1732 /* Also turn on the BASE_DISABLE bit, if needed */ 1733 if(opP->reg==PC || opP->reg==ZPC) { 1734 tmpreg=0x3b; /* 7.3 */ 1735 if(opP->reg==ZPC) 1736 nextword|=0x80; 1737 } else if(opP->reg==FAIL) { 1738 nextword|=0x80; 1739 tmpreg=0x30; /* 6.garbage */ 1740 } else tmpreg=0x30+opP->reg-ADDR; /* 6.areg */ 1741 1742 siz1= (opP->con1) ? opP->con1->e_siz : 0; 1743 siz2= (opP->con2) ? opP->con2->e_siz : 0; 1744 1745 /* Index register stuff */ 1746 if(opP->ireg>=DATA+0 && opP->ireg<=ADDR+7) { 1747 nextword|=(opP->ireg-DATA)<<12; 1748 1749 if(opP->isiz==0 || opP->isiz==3) 1750 nextword|=0x800; 1751 switch(opP->imul) { 1752 case 1: break; 1753 case 2: nextword|=0x200; break; 1754 case 4: nextword|=0x400; break; 1755 case 8: nextword|=0x600; break; 1756 default: abort(); 1757 } 1758 /* IF its simple, GET US OUT OF HERE! */ 1759 /* Must be INDEX, with an index register. Address register 1760 cannot be ZERO-PC, and either :b was forced, or we know it'll fit */ 1761 if(opP->mode==AINDX && 1762 opP->reg!=FAIL && opP->reg!=ZPC && (siz1==1 || (issbyte(baseo) && 1763 !isvar(opP->con1)))) { 1764 nextword +=baseo&0xff; 1765 addword(nextword); 1766 if(isvar(opP->con1)) 1767 add_fix('B',opP->con1,0); 1768 break; 1769 } 1770 } else 1771 nextword|=0x40; /* No index reg */ 1772 1773 /* It aint simple */ 1774 nextword|=0x100; 1775 /* If the guy specified a width, we assume that 1776 it is wide enough. Maybe it isn't. Ifso, we lose 1777 */ 1778 switch(siz1) { 1779 case 0: 1780 if(isvar(opP->con1) || !issword(baseo)) { 1781 siz1=3; 1782 nextword|=0x30; 1783 } else if(baseo==0) 1784 nextword|=0x10; 1785 else { 1786 nextword|=0x20; 1787 siz1=2; 1788 } 1789 break; 1790 case 1: 1791 as_warn("Byte dispacement won't work. Defaulting to :w"); 1792 case 2: 1793 nextword|=0x20; 1794 break; 1795 case 3: 1796 nextword|=0x30; 1797 break; 1798 } 1799 1800 /* Figure out innner displacement stuff */ 1801 if(opP->mode!=AINDX) { 1802 switch(siz2) { 1803 case 0: 1804 if(isvar(opP->con2) || !issword(outro)) { 1805 siz2=3; 1806 nextword|=0x3; 1807 } else if(outro==0) 1808 nextword|=0x1; 1809 else { 1810 nextword|=0x2; 1811 siz2=2; 1812 } 1813 break; 1814 case 1: 1815 as_warn("Byte dispacement won't work. Defaulting to :w"); 1816 case 2: 1817 nextword|=0x2; 1818 break; 1819 case 3: 1820 nextword|=0x3; 1821 break; 1822 } 1823 if(opP->mode==APODX) nextword|=0x04; 1824 else if(opP->mode==AMIND) nextword|=0x40; 1825 } 1826 addword(nextword); 1827 1828 if(isvar(opP->con1)) 1829 add_fix(siz1==3 ? 'l' : 'w',opP->con1,0); 1830 if(siz1==3) 1831 addword(baseo>>16); 1832 if(siz1) 1833 addword(baseo); 1834 1835 if(isvar(opP->con2)) 1836 add_fix(siz2==3 ? 'l' : 'w',opP->con2,0); 1837 if(siz2==3) 1838 addword(outro>>16); 1839 if(siz2) 1840 addword(outro); 1841 1842 break; 1843 1844 case ABSL: 1845 nextword=get_num(opP->con1,80); 1846 switch(opP->con1->e_siz) { 1847 case 1: /* treat like not there, fall through */ 1848 as_warn("ignoring :b suffix on %*s", 1849 (int)(opP->con1->e_end-opP->con1->e_beg), 1850 opP->con1->e_beg); 1851 case 0: 1852 if(!isvar(opP->con1) && 1853 issword(offs(opP->con1))) { 1854 tmpreg=0x38; /* 7.0 */ 1855 addword(nextword); 1856 break; 1857 } 1858 /* Don't generate pc relative code 1859 on 68010 and 68000 */ 1860 if(isvar(opP->con1) && 1861 !subs(opP->con1) && 1862 seg(opP->con1) == SEG_SECT && 1863 frchain_now->frch_nsect == 1864 opP->con1->e_exp.X_add_symbol-> 1865 sy_nlist.n_sect && 1866 flagseen['m'] == 0 && 1867 !index("~%&$?", s[0])) { 1868 tmpreg=0x3A; /* 7.2 */ 1869 add_frag(adds(opP->con1), 1870 offs(opP->con1), 1871 TAB(PCREL,SZ_UNDEF)); 1872 break; 1873 } 1874 case 3: /* Fall through into long */ 1875 if(isvar(opP->con1)) 1876 add_fix('l',opP->con1,0); 1877 1878 tmpreg=0x39; /* 7.1 mode */ 1879 addword(nextword>>16); 1880 addword(nextword); 1881 break; 1882 1883 case 2: /* Word */ 1884 if(isvar(opP->con1)) 1885 add_fix('w',opP->con1,0); 1886 1887 tmpreg=0x38; /* 7.0 mode */ 1888 addword(nextword); 1889 break; 1890 } 1891 break; 1892 case MSCR: 1893 default: 1894 as_bad("unknown/incorrect operand"); 1895 /* abort(); */ 1896 } 1897 install_gen_operand(s[1],tmpreg); 1898 break; 1899 1900 case '#': 1901 case '^': 1902 switch(s[1]) { /* JF: I hate floating point! */ 1903 case 'j': 1904 tmpreg=70; 1905 break; 1906 case '8': 1907 tmpreg=20; 1908 break; 1909 case 'C': 1910 tmpreg=50; 1911 break; 1912 case '3': 1913 default: 1914 tmpreg=80; 1915 break; 1916 } 1917 tmpreg=get_num(opP->con1,tmpreg); 1918 if(isvar(opP->con1)) 1919 add_fix(s[1],opP->con1,0); 1920 switch(s[1]) { 1921 case 'b': /* Danger: These do no check for 1922 certain types of overflow. 1923 user beware! */ 1924 if(!isbyte(tmpreg)) 1925 opP->error="out of range"; 1926 insop(tmpreg); 1927 if(isvar(opP->con1)) 1928 the_ins.reloc[the_ins.nrel-1].n=(opcode->m_codenum)*2; 1929 break; 1930#ifdef NeXT_MOD 1931 case 'j': 1932 if(tmpreg < 0 || tmpreg > 0xfff) 1933 opP->error="out of range"; 1934 tmpreg&=0xFFF; 1935 install_operand(s[1],tmpreg); 1936 break; 1937#endif /* NeXT_MOD */ 1938 case 'w': 1939 case 'z': 1940#ifdef CHECK_WORD_IMMEDIATES 1941 if(!isword(tmpreg)) 1942 opP->error="out of range"; 1943#endif 1944 insop(tmpreg); 1945 if(isvar(opP->con1)) 1946 the_ins.reloc[the_ins.nrel-1].n=(opcode->m_codenum)*2; 1947 break; 1948 case 'l': 1949 insop(tmpreg); /* Because of the way insop works, we put these two out backwards */ 1950 insop(tmpreg>>16); 1951 if(isvar(opP->con1)) 1952 the_ins.reloc[the_ins.nrel-1].n=(opcode->m_codenum)*2; 1953 break; 1954 case '3': 1955 tmpreg&=0xFF; 1956#ifdef NeXT_MOD 1957 if (isvar(opP->con1)) 1958 the_ins.reloc[the_ins.nrel-1].n = 1959 (opcode->m_codenum) + 1; 1960#endif /* NeXT_MOD */ 1961 case '8': 1962 case 'C': 1963 install_operand(s[1],tmpreg); 1964 break; 1965 default: 1966 as_fatal("Internal error: Unknown mode #%c",s[1]); 1967 } 1968 break; 1969 1970 case '+': 1971 case '-': 1972 case 'A': 1973 install_operand(s[1],opP->reg-ADDR); 1974 break; 1975 1976 case 'B': 1977 tmpreg = get_num(opP->con1, 80); 1978 switch(s[1]){ 1979 case 'g': 1980 /* Deal with fixed size stuff by hand */ 1981 if(opP->con1->e_siz){ 1982 switch(opP->con1->e_siz){ 1983 case 1: 1984 add_fix('B', opP->con1, 1); 1985 break; 1986 case 2: 1987 if(strncmp(instring, "jbsr", 4) == 0){ 1988 if(isvar(opP->con1)) 1989 add_fix('w', opP->con1, 0); 1990 /* force a jsr 7.0 mode (xxx):W */ 1991 the_ins.opcode[the_ins.numo-1] = 0x4eb8; 1992 addword(tmpreg); 1993 break; 1994 } 1995 if(strncmp(instring, "jra", 3) == 0){ 1996 if(isvar(opP->con1)) 1997 add_fix('w', opP->con1, 0); 1998 /* force a jmp 7.0 mode (xxx):W */ 1999 the_ins.opcode[the_ins.numo-1] = 0x4ef8; 2000 addword(tmpreg); 2001 break; 2002 } 2003 opP->con1->e_exp.X_add_number += 2; 2004 add_fix('w', opP->con1, 1); 2005 addword(0); 2006 break; 2007 case 3: 2008 the_ins.opcode[the_ins.numo-1] |= 0xff; 2009 opP->con1->e_exp.X_add_number += 4; 2010 add_fix('l', opP->con1, 1); 2011 addword(0); 2012 addword(0); 2013 break; 2014 default: 2015 as_fatal("Bad size for expression %d", 2016 opP->con1->e_siz); 2017 } 2018 } 2019 else if(subs(opP->con1)){ 2020 /* We can't relax it */ 2021 the_ins.opcode[the_ins.numo-1] |= 0xff; 2022 add_fix('l', opP->con1, 1); 2023 addword(0); 2024 addword(0); 2025 } 2026 else if(adds(opP->con1)){ 2027 if(flagseen['m'] && 2028 (the_ins.opcode[0] >= 0x6200) && 2029 (the_ins.opcode[0] <= 0x6f00)){ 2030 add_frag(adds(opP->con1), 2031 offs(opP->con1), 2032 TAB(BCC68000, SZ_UNDEF)); 2033 } 2034 else{ 2035 add_frag(adds(opP->con1), 2036 offs(opP->con1), 2037 TAB(BRANCH, SZ_UNDEF)); 2038 } 2039 } 2040 else{ 2041 the_ins.opcode[the_ins.numo-1] |= 0xff; 2042 opP->con1->e_exp.X_add_number += 4; 2043 add_fix('l', opP->con1, 1); 2044 addword(0); 2045 addword(0); 2046 } 2047 break; 2048 case 'w': 2049 if(isvar(opP->con1)){ 2050 /* check for DBcc instruction */ 2051 if((the_ins.opcode[0] & 0xf0f8) ==0x50c8){ 2052 /* size varies if patch */ 2053 /* needed for long form */ 2054 add_frag(adds(opP->con1), 2055 offs(opP->con1), 2056 TAB(DBCC, SZ_UNDEF)); 2057 break; 2058 } 2059 } 2060 opP->con1->e_exp.X_add_number += 2; 2061 add_fix('w', opP->con1, 1); 2062 addword(0); 2063 break; 2064 case 'c': 2065 if(opP->con1->e_siz){ 2066 switch(opP->con1->e_siz){ 2067 case 2: 2068 opP->con1->e_exp.X_add_number += 2; 2069 add_fix('w', opP->con1, 1); 2070 addword(0); 2071 break; 2072 case 3: 2073 the_ins.opcode[the_ins.numo-1] |= 0x40; 2074 opP->con1->e_exp.X_add_number += 4; 2075 add_fix('l', opP->con1, 1); 2076 addword(0); 2077 addword(0); 2078 break; 2079 default: 2080 as_bad("Bad size for offset, must be word " 2081 "or long"); 2082 break; 2083 } 2084 } 2085 else if(subs(opP->con1)){ 2086 /* We can't relax it */ 2087 the_ins.opcode[the_ins.numo-1] |= 0x40; 2088 add_fix('l', opP->con1, 1); 2089 addword(0); 2090 addword(0); 2091 } 2092 else if(adds(opP->con1)){ 2093 add_frag(adds(opP->con1), 2094 offs(opP->con1), 2095 TAB(FBRANCH, SZ_UNDEF)); 2096 } 2097 else{ 2098 the_ins.opcode[the_ins.numo-1] |= 0x40; 2099 opP->con1->e_exp.X_add_number += 4; 2100 add_fix('l', opP->con1, 1); 2101 addword(0); 2102 addword(0); 2103 } 2104 break; 2105 default: 2106 as_fatal("Internal error: operand type B%c unknown", 2107 s[1]); 2108 } 2109 break; 2110 2111 case 'C': /* Ignore it */ 2112 break; 2113 2114 case 'd': /* JF this is a kludge */ 2115 if(opP->mode==AOFF) { 2116 install_operand('s',opP->reg-ADDR); 2117 } else { 2118 char *tmpP; 2119 2120 tmpP=opP->con1->e_end-2; 2121 opP->con1->e_beg++; 2122 opP->con1->e_end-=4; /* point to the , */ 2123 baseo=m68k_reg_parse(&tmpP); 2124 if(baseo<ADDR+0 || baseo>ADDR+7) { 2125 as_bad("Unknown address reg, using A0"); 2126 baseo=0; 2127 } else baseo-=ADDR; 2128 install_operand('s',baseo); 2129 } 2130 tmpreg=get_num(opP->con1,80); 2131 if(!issword(tmpreg)) { 2132 as_warn("Expression out of range, using 0"); 2133 tmpreg=0; 2134 } 2135 addword(tmpreg); 2136 break; 2137 2138 case 'D': 2139 install_operand(s[1],opP->reg-DATA); 2140 break; 2141 2142 case 'F': 2143 install_operand(s[1],opP->reg-FPREG); 2144 break; 2145 2146 case 'I': 2147 tmpreg=1+opP->reg-COPNUM; 2148 if(tmpreg==8) 2149 tmpreg=0; 2150 install_operand(s[1],tmpreg); 2151 break; 2152 2153 case 'J': /* JF foo */ 2154 switch(opP->reg) { 2155 case SFC: 2156 tmpreg=0; 2157 break; 2158 case DFC: 2159 tmpreg=0x001; 2160 break; 2161 case CACR: 2162 tmpreg=0x002; 2163 break; 2164 case USP: 2165 tmpreg=0x800; 2166 break; 2167 case VBR: 2168 tmpreg=0x801; 2169 break; 2170 case CAAR: 2171 tmpreg=0x802; 2172 break; 2173 case MSP: 2174 tmpreg=0x803; 2175 break; 2176 case ISP: 2177 tmpreg=0x804; 2178 break; 2179#ifdef BUILTIN_MMUS 2180 case TC: 2181 tmpreg=0x003; 2182 break; 2183 case ITT0: 2184 tmpreg=0x004; 2185 break; 2186 case ITT1: 2187 tmpreg=0x005; 2188 break; 2189 case DTT0: 2190 tmpreg=0x006; 2191 break; 2192 case DTT1: 2193 tmpreg=0x007; 2194 break; 2195 case MMUSR: 2196 tmpreg=0x805; 2197 break; 2198 case URP: 2199 tmpreg=0x806; 2200 break; 2201 case SRP: 2202 tmpreg=0x807; 2203 break; 2204#endif /* BUILTIN_MMUS */ 2205 default: 2206 abort(); 2207 } 2208 install_operand(s[1],tmpreg); 2209 break; 2210#ifdef NeXT_MOD 2211 case '0': 2212 tmpreg=opP->reg-ADDR; 2213 install_operand(s[1],tmpreg); 2214 break; 2215#endif /* NeXT_MOD */ 2216 2217 case 'k': 2218 tmpreg=get_num(opP->con1,55); 2219 install_operand(s[1],tmpreg&0x7f); 2220 break; 2221 2222 case 'l': 2223 tmpreg=opP->reg; 2224 if(s[1]=='w') { 2225 if(tmpreg&0x7FF0000) 2226 as_bad("Floating point register in register list"); 2227 insop(reverse_16_bits(tmpreg)); 2228 } else { 2229 if(tmpreg&0x700FFFF) 2230 as_bad("Wrong register in floating-point reglist"); 2231 install_operand(s[1],reverse_8_bits(tmpreg>>16)); 2232 } 2233 break; 2234 2235 case 'L': 2236 tmpreg=opP->reg; 2237 if(s[1]=='w') { 2238 if(tmpreg&0x7FF0000) 2239 as_bad("Floating point register in register list"); 2240 insop(tmpreg); 2241 } else if(s[1]=='8') { 2242 if(tmpreg&0x0FFFFFF) 2243 as_bad("incorrect register in reglist"); 2244 install_operand(s[1],tmpreg>>24); 2245 } else { 2246 if(tmpreg&0x700FFFF) 2247 as_bad("wrong register in floating-point reglist"); 2248 else 2249 install_operand(s[1],tmpreg>>16); 2250 } 2251 break; 2252 2253 case 'M': 2254 install_operand(s[1],get_num(opP->con1,60)); 2255 break; 2256 2257 case 'O': 2258 tmpreg= (opP->mode==DREG) 2259 ? (int)(0x20+opP->reg-DATA) 2260 : (get_num(opP->con1,40)&0x1F); 2261 install_operand(s[1],tmpreg); 2262 break; 2263 2264 case 'Q': 2265 tmpreg=get_num(opP->con1,10); 2266 if(tmpreg==8) 2267 tmpreg=0; 2268 install_operand(s[1],tmpreg); 2269 break; 2270 2271 case 'R': 2272 /* This depends on the fact that ADDR registers are 2273 eight more than their corresponding DATA regs, so 2274 the result will have the ADDR_REG bit set */ 2275 install_operand(s[1],opP->reg-DATA); 2276 break; 2277 2278 case 's': 2279 if(opP->reg==FPI) tmpreg=0x1; 2280 else if(opP->reg==FPS) tmpreg=0x2; 2281 else if(opP->reg==FPC) tmpreg=0x4; 2282 else abort(); 2283 install_operand(s[1],tmpreg); 2284 break; 2285 2286 case 'S': /* Ignore it */ 2287 break; 2288 2289 case 'T': 2290 install_operand(s[1],get_num(opP->con1,30)); 2291 break; 2292 2293 case 'U': /* Ignore it */ 2294 break; 2295 2296#if defined(m68851) || defined(BUILTIN_MMUS) 2297 /* JF: These are out of order, I fear. */ 2298 case 'f': 2299 switch (opP->reg) { 2300 case SFC: 2301 tmpreg=0; 2302 break; 2303 case DFC: 2304 tmpreg=1; 2305 break; 2306 default: 2307 abort(); 2308 } 2309 install_operand(s[1],tmpreg); 2310 break; 2311#endif 2312 2313#ifdef BUILTIN_MMUS 2314 case 'a': 2315 switch (opP->reg) { 2316 case SRP: 2317 tmpreg=2; 2318 break; 2319 case CRP: 2320 tmpreg=3; 2321 break; 2322 case TC: 2323 tmpreg=0; 2324 break; 2325 default: 2326 abort(); 2327 } 2328 install_operand(s[1],tmpreg); 2329 break; 2330 case 'b': 2331 switch (opP->reg) { 2332 case MMUSR: 2333 tmpreg=0; 2334 break; 2335 default: 2336 abort(); 2337 } 2338 install_operand(s[1],tmpreg); 2339 break; 2340 case 'c': 2341 switch (opP->reg) { 2342 case IC: 2343 tmpreg=2; 2344 break; 2345 case DC: 2346 tmpreg=1; 2347 break; 2348 case BC: 2349 tmpreg=3; 2350 break; 2351 default: 2352 abort(); 2353 } 2354 install_operand(s[1],tmpreg); 2355 break; 2356 case 'e': 2357 switch (opP->reg) { 2358 case TT0: 2359 tmpreg=2; 2360 break; 2361 case TT1: 2362 tmpreg=3; 2363 break; 2364 default: 2365 abort(); 2366 } 2367 install_operand(s[1],tmpreg); 2368 break; 2369#endif 2370 2371#ifdef m68851 2372 case 'P': 2373 switch(opP->reg) { 2374 case TC: 2375 tmpreg=0; 2376 break; 2377 case CAL: 2378 tmpreg=4; 2379 break; 2380 case VAL: 2381 tmpreg=5; 2382 break; 2383 case SCC: 2384 tmpreg=6; 2385 break; 2386 case AC: 2387 tmpreg=7; 2388 break; 2389 default: 2390 abort(); 2391 } 2392 install_operand(s[1],tmpreg); 2393 break; 2394 2395 case 'V': 2396 if (opP->reg == VAL) 2397 break; 2398 abort(); 2399 2400 case 'W': 2401 switch(opP->reg) { 2402 2403 case DRP: 2404 tmpreg=1; 2405 break; 2406 case SRP: 2407 tmpreg=2; 2408 break; 2409 case CRP: 2410 tmpreg=3; 2411 break; 2412 default: 2413 abort(); 2414 } 2415 install_operand(s[1],tmpreg); 2416 break; 2417 2418 case 'X': 2419 switch (opP->reg) { 2420 case BAD: case BAD+1: case BAD+2: case BAD+3: 2421 case BAD+4: case BAD+5: case BAD+6: case BAD+7: 2422 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2); 2423 break; 2424 2425 case BAC: case BAC+1: case BAC+2: case BAC+3: 2426 case BAC+4: case BAC+5: case BAC+6: case BAC+7: 2427 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2); 2428 break; 2429 2430 default: 2431 abort(); 2432 } 2433 install_operand(s[1], tmpreg); 2434 break; 2435 case 'Y': 2436 if (opP->reg == PSR) 2437 break; 2438 abort(); 2439 2440 case 'Z': 2441 if (opP->reg == PCSR) 2442 break; 2443 abort(); 2444#endif /* m68851 */ 2445 default: 2446 as_fatal("Internal error: Operand type %c unknown",s[0]); 2447 } 2448 } 2449 /* By the time whe get here (FINALLY) the_ins contains the complete 2450 instruction, ready to be emitted. . . */ 2451} 2452 2453static 2454int 2455get_regs( 2456int i, 2457struct m68k_op *opP, 2458char *str) 2459{ 2460 /* 26, 25, 24, 23-16, 15-8, 0-7 */ 2461 /* Low order 24 bits encoded fpc,fps,fpi,fp7-fp0,a7-a0,d7-d0 */ 2462 uint32_t cur_regs = 0; 2463 int reg1, 2464 reg2; 2465 2466#define ADD_REG(x) { if(x==FPI) cur_regs|=(1<<24);\ 2467 else if(x==FPS) cur_regs|=(1<<25);\ 2468 else if(x==FPC) cur_regs|=(1<<26);\ 2469 else cur_regs|=(1<<(x-1)); } 2470 2471 reg1=i; 2472 for(;;) { 2473 if(*str=='/') { 2474 ADD_REG(reg1); 2475 str++; 2476 } else if(*str=='-') { 2477 str++; 2478 reg2=m68k_reg_parse(&str); 2479 if(reg2<DATA || reg2>=FPREG+8 || reg1==FPI || reg1==FPS || reg1==FPC) { 2480 opP->error="unknown register in register list"; 2481 return FAIL; 2482 } 2483 while(reg1<=reg2) { 2484 ADD_REG(reg1); 2485 reg1++; 2486 } 2487 if(*str=='\0') 2488 break; 2489 } else if(*str=='\0') { 2490 ADD_REG(reg1); 2491 break; 2492 } else { 2493 opP->error="unknow character in register list"; 2494 return FAIL; 2495 } 2496/* DJA -- Bug Fix. Did't handle d1-d2/a1 until the following instruction was added */ 2497 if (*str=='/') 2498 str ++; 2499 reg1=m68k_reg_parse(&str); 2500 if((reg1<DATA || reg1>=FPREG+8) && !(reg1==FPI || reg1==FPS || reg1==FPC)) { 2501 opP->error="unknown register in register list"; 2502 return FAIL; 2503 } 2504 } 2505 opP->reg=cur_regs; 2506 return OK; 2507} 2508 2509static 2510int 2511reverse_16_bits( 2512int in) 2513{ 2514 int out=0; 2515 int n; 2516 2517 static int mask[16] = { 25180x0001,0x0002,0x0004,0x0008,0x0010,0x0020,0x0040,0x0080, 25190x0100,0x0200,0x0400,0x0800,0x1000,0x2000,0x4000,0x8000 2520 }; 2521 for(n=0;n<16;n++) { 2522 if(in&mask[n]) 2523 out|=mask[15-n]; 2524 } 2525 return out; 2526} 2527 2528static 2529int 2530reverse_8_bits( 2531int in) 2532{ 2533 int out=0; 2534 int n; 2535 2536 static int mask[8] = { 25370x0001,0x0002,0x0004,0x0008,0x0010,0x0020,0x0040,0x0080, 2538 }; 2539 2540 for(n=0;n<8;n++) { 2541 if(in&mask[n]) 2542 out|=mask[7-n]; 2543 } 2544 return out; 2545} 2546 2547static 2548void 2549install_operand( 2550int mode, 2551int val) 2552{ 2553 switch(mode) { 2554 case 's': 2555 the_ins.opcode[0]|=val & 0xFF; /* JF FF is for M kludge */ 2556 break; 2557 case 'd': 2558 the_ins.opcode[0]|=val<<9; 2559 break; 2560 case '1': 2561 the_ins.opcode[1]|=val<<12; 2562 break; 2563 case '2': 2564 the_ins.opcode[1]|=val<<6; 2565 break; 2566 case '3': 2567 the_ins.opcode[1]|=val; 2568 break; 2569 case '4': 2570 the_ins.opcode[2]|=val<<12; 2571 break; 2572 case '5': 2573 the_ins.opcode[2]|=val<<6; 2574 break; 2575 case '6': 2576 /* DANGER! This is a hack to force cas2l and cas2w cmds 2577 to be three words long! */ 2578 the_ins.numo++; 2579 the_ins.opcode[2]|=val; 2580 break; 2581 case '7': 2582 the_ins.opcode[1]|=val<<7; 2583 break; 2584 case '8': 2585 the_ins.opcode[1]|=val<<10; 2586 break; 2587#if defined(m68851) || defined(BUILTIN_MMUS) 2588 case '9': 2589 the_ins.opcode[1]|=val<<5; 2590 break; 2591#endif 2592#ifdef BUILTIN_MMUS 2593 case 'S': 2594 the_ins.opcode[0]|=val<<6; 2595 break; 2596#endif 2597 case 't': 2598 the_ins.opcode[1]|=(val<<10)|(val<<7); 2599 break; 2600 case 'D': 2601 the_ins.opcode[1]|=(val<<12)|val; 2602 break; 2603 case 'g': 2604 the_ins.opcode[0]|=val=0xff; 2605 break; 2606 case 'i': 2607 the_ins.opcode[0]|=val<<9; 2608 break; 2609 case 'C': 2610 the_ins.opcode[1]|=val; 2611 break; 2612 case 'j': 2613 the_ins.opcode[1]|=val; 2614 the_ins.numo++; /* What a hack */ 2615 break; 2616 case 'k': 2617 the_ins.opcode[1]|=val<<4; 2618 break; 2619 case 'b': 2620 case 'w': 2621 case 'l': 2622 break; 2623 case 'c': 2624 default: 2625 abort(); 2626 } 2627} 2628 2629static 2630void 2631install_gen_operand( 2632int mode, 2633int val) 2634{ 2635 switch(mode) { 2636 case 's': 2637 the_ins.opcode[0]|=val; 2638 break; 2639 case 'd': 2640 /* This is a kludge!!! */ 2641 the_ins.opcode[0]|=(val&0x07)<<9|(val&0x38)<<3; 2642 break; 2643 case 'b': 2644 case 'w': 2645 case 'l': 2646 case 'f': 2647 case 'F': 2648 case 'x': 2649 case 'p': 2650 the_ins.opcode[0]|=val; 2651 break; 2652 /* more stuff goes here */ 2653 default: 2654 abort(); 2655 } 2656} 2657 2658static 2659char * 2660crack_operand( 2661char *str, 2662struct m68k_op *opP) 2663{ 2664 register int parens; 2665 register int c; 2666 register char *beg_str; 2667 2668 if(!str) { 2669 return str; 2670 } 2671 beg_str=str; 2672 for(parens=0;*str && (parens>0 || notend(str));str++) { 2673 if(*str == '"') { 2674 str++; 2675 while(*str && *str != '"') 2676 str++; 2677 if(*str != '"'){ /* ERROR */ 2678 opP->error="Missing \""; 2679 return str; 2680 } 2681 } 2682 else{ 2683 if(*str=='(') 2684 parens++; 2685 else if(*str==')') { 2686 if(!parens) { /* ERROR */ 2687 opP->error="Extra )"; 2688 return str; 2689 } 2690 --parens; 2691 } 2692 } 2693 } 2694 if(!*str && parens) { /* ERROR */ 2695 opP->error="Missing )"; 2696 return str; 2697 } 2698 c= *str; 2699 *str='\0'; 2700 if(m68k_ip_op(beg_str,opP)==FAIL) { 2701 *str=c; 2702 return str; 2703 } 2704 *str=c; 2705 if(c=='}') 2706 c= *++str; /* JF bitfield hack */ 2707 if(c) { 2708 c= *++str; 2709 if(!c) 2710 as_bad("Missing operand"); 2711 } 2712 return str; 2713} 2714 2715/* See the comment up above where the #define notend(... is */ 2716#if 0 2717notend(s) 2718char *s; 2719{ 2720 if(*s==',') return 0; 2721 if(*s=='{' || *s=='}') 2722 return 0; 2723 if(*s!=':') return 1; 2724 /* This kludge here is for the division cmd, which is a kludge */ 2725 if(index("aAdD#",s[1])) return 0; 2726 return 1; 2727} 2728#endif /* 0 */ 2729 2730#ifdef NeXT_MOD 2731static char *file_030, *file_040; 2732static uint32_t line_030, line_040; 2733#endif /* NeXT_MOD */ 2734 2735/* This is the guts of the machine-dependent assembler. STR points to a 2736 machine dependent instruction. This funciton is supposed to emit 2737 the frags/bytes it assembles to. 2738 */ 2739void 2740md_assemble( 2741char *str) 2742{ 2743 char *er; 2744 short *fromP; 2745 char *toP = NULL; 2746 int m,n; 2747 char *to_beg_P; 2748 int shorts_this_frag; 2749 2750 n = 0; 2751 memset((char *)(&the_ins), '\0', sizeof(the_ins)); 2752 m68_ip(str); 2753 er=the_ins.error; 2754 if(!er) { 2755 for(n=the_ins.numargs;n;--n) 2756 if(the_ins.operands[n].error) { 2757 er=the_ins.operands[n].error; 2758 break; 2759 } 2760 } 2761 if(er) { 2762 as_bad("\"%s\" -- Statement '%s' ignored",er,str); 2763 return; 2764 } 2765 2766#ifdef NeXT_MOD 2767 if(the_ins.cpus != NULL && !force_cpusubtype_ALL){ 2768 if(md_cpusubtype == CPU_SUBTYPE_MC680x0_ALL){ 2769 switch(*the_ins.cpus){ 2770 case '2': 2771 as_bad("implementation specific instruction for the MC68020" 2772 " and -force_cpusubtype_ALL not specified"); 2773 break; 2774 case '3': 2775 if(archflag_cpusubtype == CPU_SUBTYPE_MC68040) 2776 as_bad("030 instruction not allowed with -arch m68040"); 2777 else{ 2778 file_030 = logical_input_file ? 2779 logical_input_file : physical_input_file; 2780 line_030 = logical_input_line ? 2781 logical_input_line : physical_input_line; 2782 md_cpusubtype = CPU_SUBTYPE_MC68030_ONLY; 2783 } 2784 break; 2785 case '4': 2786 if(archflag_cpusubtype == CPU_SUBTYPE_MC68030_ONLY) 2787 as_bad("040 instruction not allowed with -arch m68030"); 2788 else{ 2789 file_040 = logical_input_file ? 2790 logical_input_file : physical_input_file; 2791 line_040 = logical_input_line ? 2792 logical_input_line : physical_input_line; 2793 md_cpusubtype = CPU_SUBTYPE_MC68040; 2794 } 2795 break; 2796 } 2797 } 2798 else{ 2799 switch(*the_ins.cpus){ 2800 case '2': 2801 as_bad("implementation specific instruction for the MC68020" 2802 " and -force_cpusubtype_ALL not specified"); 2803 break; 2804 case '3': 2805 if(archflag_cpusubtype == CPU_SUBTYPE_MC68040) 2806 as_bad("030 instruction not allowed with -arch m68040"); 2807 else{ 2808 if(md_cpusubtype != CPU_SUBTYPE_MC680x0_ALL && 2809 md_cpusubtype != CPU_SUBTYPE_MC68030_ONLY) 2810 as_bad("more than one implementation specific " 2811 "instruction seen and -force_cpusubtype_ALL " 2812 " not specified (first 040 instruction in: " 2813 "%s at line %u)", file_040, line_040); 2814 md_cpusubtype = CPU_SUBTYPE_MC68030_ONLY; 2815 } 2816 break; 2817 case '4': 2818 if(archflag_cpusubtype == CPU_SUBTYPE_MC68030_ONLY) 2819 as_bad("040 instruction not allowed with -arch m68030"); 2820 else{ 2821 if(md_cpusubtype != CPU_SUBTYPE_MC680x0_ALL && 2822 md_cpusubtype != CPU_SUBTYPE_MC68040) 2823 as_bad("more than one implementation specific " 2824 "instruction seen and -force_cpusubtype_ALL " 2825 "not specified (first 030 instruction in: " 2826 "%s at line %u)", file_030, line_030); 2827 md_cpusubtype = CPU_SUBTYPE_MC68040; 2828 } 2829 break; 2830 } 2831 } 2832 } 2833#endif /* NeXT_MOD */ 2834 2835#ifdef NeXT_MOD /* generate stabs for debugging assembly code */ 2836 /* 2837 * If the -g flag is present generate a line number stab for the 2838 * instruction. 2839 * 2840 * See the detailed comments about stabs in read_a_source_file() for a 2841 * description of what is going on here. 2842 */ 2843 if(flagseen['g'] && frchain_now->frch_nsect == text_nsect){ 2844 (void)symbol_new( 2845 "", 2846 68 /* N_SLINE */, 2847 text_nsect, 2848 logical_input_line /* n_desc, line number */, 2849 obstack_next_free(&frags) - frag_now->fr_literal, 2850 frag_now); 2851 } 2852#endif /* NeXT_MOD */ 2853 2854#ifdef NeXT_MOD /* mark sections containing instructions */ 2855 /* 2856 * We are putting a machine instruction in this section so mark it as 2857 * containg some machine instructions. 2858 */ 2859 frchain_now->frch_section.flags |= S_ATTR_SOME_INSTRUCTIONS; 2860#endif /* NeXT_MOD */ 2861 2862 if(the_ins.nfrag==0) { /* No frag hacking involved; just put it out */ 2863 toP=frag_more(2*the_ins.numo); 2864 fromP= &the_ins.opcode[0]; 2865 for(m=the_ins.numo;m;--m) { 2866 md_number_to_chars(toP,(int32_t)(*fromP),2); 2867 toP+=2; 2868 fromP++; 2869 } 2870 /* put out symbol-dependent info */ 2871 for(m=0;m<the_ins.nrel;m++) { 2872 switch(the_ins.reloc[m].wid) { 2873 case 'B': 2874 n=1; 2875 break; 2876 case 'b': 2877 n=1; 2878 break; 2879 case '3': 2880#ifdef NeXT_MOD 2881 /* This is a bug fix that is not in the 1.36 2882 * version of GAS for this construct: 2883 * fmovemx #foo,a0@- 2884 * foo = 0xffff; 2885 * Where the width of the relocation should be 2886 * one byte (the low 8 bits of the second word) 2887 * for the floating point register mask. Other- * wise the next byte after this instruction 2888 * gets trashed by this relocation. 2889 */ 2890 n=1; 2891#else /* !defined(NeXT_MOD) */ 2892 n=2; 2893#endif /* NeXT_MOD */ 2894 break; 2895 case 'w': 2896 n=2; 2897 break; 2898 case 'l': 2899 n=4; 2900 break; 2901 default: 2902 as_fatal("Don't know how to figure width of %c in md_assemble()",the_ins.reloc[m].wid); 2903 } 2904 2905 fix_new(frag_now, 2906 (toP - frag_now->fr_literal) - 2907 the_ins.numo * 2 + the_ins.reloc[m].n, 2908 n, 2909 the_ins.reloc[m].add, 2910 the_ins.reloc[m].sub, 2911 the_ins.reloc[m].off, 2912 the_ins.reloc[m].pcrel, 2913 0,0); 2914 } 2915 return; 2916 } 2917 2918 /* There's some frag hacking */ 2919 for(n=0,fromP= &the_ins.opcode[0];n<the_ins.nfrag;n++) { 2920 int wid; 2921 2922 if(n==0) wid=2*the_ins.fragb[n].fragoff; 2923 else wid=2*(the_ins.numo-the_ins.fragb[n-1].fragoff); 2924 toP=frag_more(wid); 2925 to_beg_P=toP; 2926 shorts_this_frag=0; 2927 for(m=wid/2;m;--m) { 2928 md_number_to_chars(toP,(int32_t)(*fromP),2); 2929 toP+=2; 2930 fromP++; 2931 shorts_this_frag++; 2932 } 2933 for(m=0;m<the_ins.nrel;m++) { 2934 if((the_ins.reloc[m].n)>= 2*shorts_this_frag /* 2*the_ins.fragb[n].fragoff */) { 2935 the_ins.reloc[m].n-= 2*shorts_this_frag /* 2*the_ins.fragb[n].fragoff */; 2936 break; 2937 } 2938 wid=the_ins.reloc[m].wid; 2939 if(wid==0) 2940 continue; 2941 the_ins.reloc[m].wid=0; 2942 wid = (wid=='b') ? 1 : (wid=='w') ? 2 : (wid=='l') ? 4 : 4000; 2943 2944 fix_new(frag_now, 2945 (toP - frag_now->fr_literal) - 2946 the_ins.numo * 2 + the_ins.reloc[m].n, 2947 wid, 2948 the_ins.reloc[m].add, 2949 the_ins.reloc[m].sub, 2950 the_ins.reloc[m].off, 2951 the_ins.reloc[m].pcrel, 2952 0,0); 2953 } 2954 know(the_ins.fragb[n].fadd); 2955 (void)frag_var(rs_machine_dependent,10,0,(relax_substateT)(the_ins.fragb[n].fragty), 2956 the_ins.fragb[n].fadd,the_ins.fragb[n].foff,to_beg_P); 2957 } 2958 n=(the_ins.numo-the_ins.fragb[n-1].fragoff); 2959 shorts_this_frag=0; 2960 if(n) { 2961 toP=frag_more(n*sizeof(short)); 2962 while(n--) { 2963 md_number_to_chars(toP,(int32_t)(*fromP),2); 2964 toP+=2; 2965 fromP++; 2966 shorts_this_frag++; 2967 } 2968 } 2969 for(m=0;m<the_ins.nrel;m++) { 2970 int wid; 2971 2972 wid=the_ins.reloc[m].wid; 2973 if(wid==0) 2974 continue; 2975 the_ins.reloc[m].wid=0; 2976 wid = (wid=='b') ? 1 : (wid=='w') ? 2 : (wid=='l') ? 4 : 4000; 2977 2978 fix_new(frag_now, 2979 (the_ins.reloc[m].n + toP-frag_now->fr_literal) - 2980 /* the_ins.numo */ shorts_this_frag * 2, 2981 wid, 2982 the_ins.reloc[m].add, 2983 the_ins.reloc[m].sub, 2984 the_ins.reloc[m].off, 2985 the_ins.reloc[m].pcrel, 2986 0,0); 2987 } 2988} 2989 2990/* This function is called once, at assembler startup time. This should 2991 set up all the tables, etc that the MD part of the assembler needs 2992 */ 2993void 2994md_begin( 2995void) 2996{ 2997/* 2998 * md_begin -- set up hash tables with 68000 instructions. 2999 * similar to what the vax assembler does. ---phr 3000 */ 3001 /* RMS claims the thing to do is take the m68k-opcode.h table, and make 3002 a copy of it at runtime, adding in the information we want but isn't 3003 there. I think it'd be better to have an awk script hack the table 3004 at compile time. Or even just xstr the table and use it as-is. But 3005 my lord ghod hath spoken, so we do it this way. Excuse the ugly var 3006 names. */ 3007 3008 register struct m68k_opcode *ins; 3009 register struct m68_incant *hack, 3010 *slak; 3011 const char *retval = 0; /* empty string, or error msg text */ 3012 register int i; 3013 register char c; 3014 3015 if ((op_hash = hash_new()) == NULL) 3016 as_fatal("Virtual memory exhausted"); 3017 3018 obstack_begin(&robyn,4000); 3019 for (ins = (struct m68k_opcode *)m68k_opcodes; ins < endop; ins++) { 3020 hack=slak=(struct m68_incant *)obstack_alloc(&robyn,sizeof(struct m68_incant)); 3021 do { 3022 slak->m_operands=ins->args; 3023 slak->m_opnum=strlen(slak->m_operands)/2; 3024 slak->m_opcode=ins->opcode; 3025 /* This is kludgey */ 3026 slak->m_codenum=((ins->match)&0xffffL) ? 2 : 1; 3027#ifdef NeXT_MOD 3028 slak->m_cpus = ins->cpus; 3029#endif /* NeXT_MOD */ 3030 if((ins+1)!=endop && !strcmp(ins->name,(ins+1)->name)) { 3031 slak->m_next=(struct m68_incant *) 3032obstack_alloc(&robyn,sizeof(struct m68_incant)); 3033 ins++; 3034 } else 3035 slak->m_next=0; 3036 slak=slak->m_next; 3037 } while(slak); 3038 3039 retval = hash_insert (op_hash, ins->name,(char *)hack); 3040 /* Didn't his mommy tell him about null pointers? */ 3041 if(retval && *retval) 3042 as_fatal("Internal Error: Can't hash %s: %s",ins->name,retval); 3043 } 3044 3045 for (i = 0; i < (int)sizeof(mklower_table) ; i++) 3046 mklower_table[i] = (isupper(c = (char) i)) ? tolower(c) : c; 3047 3048 for (i = 0 ; i < (int)sizeof(notend_table) ; i++) { 3049 notend_table[i] = 0; 3050 alt_notend_table[i] = 0; 3051 } 3052 notend_table[','] = 1; 3053 notend_table['{'] = 1; 3054 notend_table['}'] = 1; 3055 alt_notend_table['a'] = 1; 3056 alt_notend_table['A'] = 1; 3057 alt_notend_table['d'] = 1; 3058 alt_notend_table['D'] = 1; 3059 alt_notend_table['#'] = 1; 3060 alt_notend_table['f'] = 1; 3061 alt_notend_table['F'] = 1; 3062} 3063 3064#if 0 3065#define notend(s) ((*s == ',' || *s == '}' || *s == '{' \ 3066 || (*s == ':' && index("aAdD#", s[1]))) \ 3067 ? 0 : 1) 3068#endif 3069 3070/* This funciton is called once, before the assembler exits. It is 3071 supposed to do any final cleanup for this part of the assembler. 3072 */ 3073void 3074md_end( 3075void) 3076{ 3077} 3078 3079/* Equal to MAX_PRECISION in atof-ieee.c */ 3080#define MAX_LITTLENUMS 6 3081 3082/* Turn a string in input_line_pointer into a floating point constant of type 3083 type, and store the appropriate bytes in *litP. The number of LITTLENUMS 3084 emitted is stored in *sizeP . An error message is returned, or NULL on OK. 3085 */ 3086char * 3087md_atof( 3088int type, 3089char *litP, 3090int *sizeP) 3091{ 3092 int prec; 3093 LITTLENUM_TYPE words[MAX_LITTLENUMS]; 3094 LITTLENUM_TYPE *wordP; 3095 char *t; 3096 3097 switch(type) { 3098 case 'f': 3099 case 'F': 3100 case 's': 3101 case 'S': 3102 prec = 2; 3103 break; 3104 3105 case 'd': 3106 case 'D': 3107 case 'r': 3108 case 'R': 3109 prec = 4; 3110 break; 3111 3112 case 'x': 3113 case 'X': 3114 prec = 6; 3115 break; 3116 3117 case 'p': 3118 case 'P': 3119 prec = 6; 3120 break; 3121 3122 default: 3123 *sizeP=0; 3124 return "Bad call to MD_ATOF()"; 3125 } 3126 t=atof_ieee(input_line_pointer,type,words); 3127 if(t) 3128 input_line_pointer=t; 3129 3130 *sizeP=prec * sizeof(LITTLENUM_TYPE); 3131 for(wordP=words;prec--;) { 3132 md_number_to_chars(litP,(int32_t)(*wordP++),sizeof(LITTLENUM_TYPE)); 3133 litP+=sizeof(LITTLENUM_TYPE); 3134 } 3135 return ""; /* Someone should teach Dean about null pointers */ 3136} 3137 3138/* Turn an integer of n bytes (in val) into a stream of bytes appropriate 3139 for use in the a.out file, and stores them in the array pointed to by buf. 3140 This knows about the endian-ness of the target machine and does 3141 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte) 3142 2 (short) and 4 (long) Floating numbers are put out as a series of 3143 LITTLENUMS (shorts, here at least) 3144 */ 3145void 3146md_number_to_chars( 3147char *buf, 3148signed_expr_t val, 3149int n) 3150{ 3151 switch(n) { 3152 case 1: 3153 *buf++=val; 3154 break; 3155 case 2: 3156 *buf++=(val>>8); 3157 *buf++=val; 3158 break; 3159 case 4: 3160 *buf++=(val>>24); 3161 *buf++=(val>>16); 3162 *buf++=(val>>8); 3163 *buf++=val; 3164 break; 3165 default: 3166 abort(); 3167 } 3168} 3169 3170void 3171md_number_to_imm( 3172unsigned char *buf, 3173signed_expr_t val, 3174int n, 3175fixS *fixP, 3176int nsect) 3177{ 3178 switch(n) { 3179 case 1: 3180 *buf++=val; 3181 break; 3182 case 2: 3183 *buf++=(val>>8); 3184 *buf++=val; 3185 break; 3186 case 4: 3187 *buf++=(val>>24); 3188 *buf++=(val>>16); 3189 *buf++=(val>>8); 3190 *buf++=val; 3191 break; 3192 default: 3193 abort(); 3194 } 3195} 3196 3197/* 3198 * Force truly undefined symbols to their maximum size, and generally set up 3199 * the frag list to be relaxed. It is the caller's responsiblity to set the 3200 * current section, frchain_now, to the corresponding nsect specified so that 3201 * calls to fix_new() will make fixes for this section. 3202 */ 3203int 3204md_estimate_size_before_relax( 3205fragS *fragP, 3206int nsect) 3207{ 3208 int old_fix; 3209 3210 old_fix = fragP->fr_fix; 3211 3212 /* 3213 * Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. 3214 */ 3215 switch(fragP->fr_subtype){ 3216 case TAB(DBCC, SZ_UNDEF): 3217 if(fragP->fr_symbol->sy_nlist.n_sect == nsect){ 3218 fragP->fr_subtype = TAB(DBCC, SHORT); 3219 fragP->fr_var += 2; 3220 break; 3221 } 3222 /* 3223 * Only DBcc 68000 instructions can come here. 3224 * Change dbcc into dbcc/jmp absl long. 3225 */ 3226 fragP->fr_opcode[2] = 0x00; /* branch offset = 4 */ 3227 fragP->fr_opcode[3] = 0x04; 3228 fragP->fr_opcode[4] = 0x60; /* put in bra pc+6 */ 3229 fragP->fr_opcode[5] = 0x06; 3230 fragP->fr_opcode[6] = 0x4e; /* put in jmp long (0x4ef9) */ 3231 fragP->fr_opcode[7] = 0xf9; 3232 fragP->fr_fix += 6; /* account for bra/jmp instructions */ 3233 fix_new(fragP, 3234 fragP->fr_fix, 3235 4, 3236 fragP->fr_symbol, 3237 0, 3238 fragP->fr_offset, 3239 0, 3240 0, 3241 0); 3242 fragP->fr_fix += 4; /* account for jmp instruction displacement */ 3243 frag_wane(fragP); 3244 break; 3245 3246 case TAB(BCC68000, SZ_UNDEF): 3247 if(fragP->fr_symbol->sy_nlist.n_sect == nsect){ 3248 fragP->fr_subtype = TAB(BCC68000, BYTE); 3249 break; 3250 } 3251 /* 3252 * Only Bcc 68000 instructions can come here. 3253 * Change bcc into b!cc/jmp absl long. 3254 */ 3255 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */ 3256 fragP->fr_opcode[1] = 0x6; /* branch offset = 6 */ 3257 fragP->fr_opcode[2] = 0x4e; /* put in jmp long (0x4ef9) */ 3258 fragP->fr_opcode[3] = 0xf9; 3259 fragP->fr_fix += 2; /* account for jmp instruction */ 3260 fix_new(fragP, 3261 fragP->fr_fix, 3262 4, 3263 fragP->fr_symbol, 3264 0, 3265 fragP->fr_offset, 3266 0, 3267 0, 3268 0); 3269 fragP->fr_fix += 4; /* account for jmp instruction displacement */ 3270 frag_wane(fragP); 3271 break; 3272 3273 case TAB(BRANCH, SZ_UNDEF): 3274 if(fragP->fr_symbol->sy_nlist.n_sect == nsect){ 3275 /* 3276 * The NeXT linker has the ability to scatter blocks of 3277 * sections between labels. This requires that brances to 3278 * labels that survive to the link phase must be able to 3279 * be relocated. 3280 */ 3281 if(fragP->fr_symbol->sy_name[0] != 'L' || flagseen ['L']){ 3282 fix_new(fragP, 3283 fragP->fr_fix, 3284 4, 3285 fragP->fr_symbol, 3286 0, 3287 fragP->fr_offset + 4, 3288 1, 3289 1, 3290 0); 3291 fragP->fr_fix += 4; 3292 fragP->fr_opcode[1] = 0xff; 3293 frag_wane(fragP); 3294 break; 3295 } 3296 else 3297 fragP->fr_subtype = TAB(BRANCH, BYTE); 3298 break; 3299 } 3300 else if(flagseen['m']){ 3301 if(fragP->fr_opcode[0] == 0x61){ 3302 fragP->fr_opcode[0] = 0x4E; 3303 fragP->fr_opcode[1] = 0xB9; /* JBSR with ABSL LONG offset */ 3304 fix_new(fragP, 3305 fragP->fr_fix, 3306 4, 3307 fragP->fr_symbol, 3308 0, 3309 fragP->fr_offset, 3310 0, 3311 0, 3312 0); 3313 fragP->fr_fix += 4; 3314 frag_wane(fragP); 3315 } 3316 else if(fragP->fr_opcode[0] == 0x60){ 3317 fragP->fr_opcode[0] = 0x4E; 3318 fragP->fr_opcode[1] = 0xF9; /* JMP with ABSL LONG offset */ 3319 fix_new(fragP, 3320 fragP->fr_fix, 3321 4, 3322 fragP->fr_symbol, 3323 0, 3324 fragP->fr_offset, 3325 0, 3326 0, 3327 0); 3328 fragP->fr_fix += 4; 3329 frag_wane(fragP); 3330 } 3331 else{ 3332 as_warn("Long branch offset to extern symbol not " 3333 "supported."); 3334 } 3335 break; 3336 } 3337 else{ 3338 /* Symbol is still undefined. Make it simple */ 3339 fix_new(fragP, 3340 fragP->fr_fix, 3341 4, 3342 fragP->fr_symbol, 3343 0, 3344 fragP->fr_offset + 4, 3345 1, 3346 1, 3347 0); 3348 fragP->fr_fix += 4; 3349 fragP->fr_opcode[1] = 0xff; 3350 frag_wane(fragP); 3351 break; 3352 } 3353 break; 3354 3355 case TAB(FBRANCH, SZ_UNDEF): 3356 if(fragP->fr_symbol->sy_nlist.n_sect == nsect){ 3357 /* 3358 * The NeXT linker has the ability to scatter blocks of 3359 * sections between labels. This requires that brances to 3360 * labels that survive to the link phase must be able to 3361 * be relocated. 3362 */ 3363 if(fragP->fr_symbol->sy_name[0] != 'L' || flagseen ['L']) { 3364 fix_new(fragP, 3365 fragP->fr_fix, 3366 4, 3367 fragP->fr_symbol, 3368 0, 3369 fragP->fr_offset + 4, 3370 1, 3371 1, 3372 0); 3373 fragP->fr_fix += 4; 3374 fragP->fr_opcode[1] |= 0x40; 3375 frag_wane(fragP); 3376 break; 3377 } 3378 else{ 3379 fragP->fr_subtype = TAB(FBRANCH, SHORT); 3380 fragP->fr_var += 2; 3381 } 3382 } 3383 else { 3384 /* Symbol is still undefined. Make it long */ 3385 fix_new(fragP, 3386 fragP->fr_fix, 3387 4, 3388 fragP->fr_symbol, 3389 0, 3390 fragP->fr_offset + 4, 3391 1, 3392 1, 3393 0); 3394 fragP->fr_fix += 4; 3395 fragP->fr_opcode[1] |= 0x40; 3396 frag_wane(fragP); 3397 break; 3398 } 3399 break; 3400 3401 case TAB(PCREL, SZ_UNDEF): 3402 if(fragP->fr_symbol->sy_nlist.n_sect == nsect){ 3403 /* 3404 * The NeXT linker has the ability to scatter blocks of 3405 * sections between labels. This requires that brances to 3406 * labels that survive to the link phase must be able to 3407 * be relocated. 3408 */ 3409 if(fragP->fr_symbol->sy_name[0] != 'L' || flagseen ['L']) { 3410 /* 3411 * The thing to do here is force it to ABSOLUTE LONG, since 3412 * PCREL is really trying to shorten an ABSOLUTE address 3413 * anyway. 3414 */ 3415 if((fragP->fr_opcode[1] & 0x3F) != 0x3A) 3416 as_bad("Internal error (long PC-relative operand) for " 3417 "insn 0x%04x at 0x%llx", fragP->fr_opcode[0], 3418 fragP->fr_address); 3419 fragP->fr_opcode[1] &= ~0x3F; 3420 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */ 3421 fix_new(fragP, 3422 fragP->fr_fix, 3423 4, 3424 fragP->fr_symbol, 3425 0, 3426 fragP->fr_offset, 3427 0, 3428 0, 3429 0); 3430 fragP->fr_fix += 4; 3431 frag_wane(fragP); 3432 } 3433 else{ 3434 fragP->fr_subtype = TAB(PCREL, SHORT); 3435 fragP->fr_var += 2; 3436 } 3437 } 3438 else { 3439 /* Symbol is still undefined. Make it long */ 3440 if((fragP->fr_opcode[1] & 0x3F) != 0x3A) 3441 as_bad("Internal error (long PC-relative operand) for " 3442 "insn 0x%04x at 0x%llx", fragP->fr_opcode[0], 3443 fragP->fr_address); 3444 fragP->fr_opcode[1] &= ~0x3F; 3445 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */ 3446 fix_new(fragP, 3447 fragP->fr_fix, 3448 4, 3449 fragP->fr_symbol, 3450 0, 3451 fragP->fr_offset, 3452 1, 3453 1, 3454 0); 3455 fragP->fr_fix += 4; 3456 frag_wane(fragP); 3457 break; 3458 } 3459 break; 3460 3461 default: 3462 break; 3463 } 3464 3465 /* 3466 * Now that SZ_UNDEF are taken care of, check others 3467 */ 3468 switch(fragP->fr_subtype) { 3469 case TAB(BCC68000, BYTE): 3470 case TAB(BRANCH, BYTE): 3471 /* 3472 * We can't do a short jump to the next instruction, 3473 * so we force word mode. 3474 */ 3475 if(fragP->fr_symbol != NULL && 3476 fragP->fr_symbol->sy_value == 0 && 3477 fragP->fr_symbol->sy_frag == fragP->fr_next) { 3478 fragP->fr_subtype = TAB(TABTYPE(fragP->fr_subtype), SHORT); 3479 fragP->fr_var += 2; 3480 } 3481 break; 3482 default: 3483 break; 3484 } 3485 return(fragP->fr_var + fragP->fr_fix - old_fix); 3486} 3487 3488/* 3489 * *fragP has been relaxed to its final size, and now needs to have 3490 * the bytes inside it modified to conform to the new size. There is UGLY 3491 * MAGIC here interms of changing the addressing mode of some instructions 3492 * and using other instructions in place of the original in the case of the 3493 * 68000 and 68010 where long pc-relative forms don't exist. 3494 */ 3495void 3496md_convert_frag( 3497fragS *fragP) 3498{ 3499 int32_t disp; 3500 int32_t ext; 3501 char *buffer_address; 3502 int object_address; 3503 3504 ext = 0; 3505 3506 /* Address in gas core of the place to store the displacement. */ 3507 buffer_address = fragP->fr_fix + fragP->fr_literal; 3508 3509 /* Address in object code of the displacement. */ 3510 object_address = fragP->fr_fix + fragP->fr_address; 3511 3512 know(fragP->fr_symbol); 3513 3514 /* The displacement of the address, from current location. */ 3515 disp = (fragP->fr_symbol->sy_value + fragP->fr_offset) - object_address; 3516 3517 switch(fragP->fr_subtype){ 3518 case TAB(BCC68000, BYTE): 3519 case TAB(BRANCH, BYTE): 3520 know(issbyte(disp)); 3521 if(disp == 0){ 3522 /* Replace this with a nop. */ 3523 fragP->fr_opcode[0] = 0x4e; 3524 fragP->fr_opcode[1] = 0x71; 3525 } 3526 else{ 3527 fragP->fr_opcode[1] = disp; 3528 } 3529 ext = 0; 3530 break; 3531 3532 case TAB(DBCC, SHORT): 3533 know(issword(disp)); 3534 ext=2; 3535 break; 3536 3537 case TAB(BCC68000, SHORT): 3538 case TAB(BRANCH, SHORT): 3539 know(issword(disp)); 3540 fragP->fr_opcode[1] = 0x00; 3541 ext = 2; 3542 break; 3543 3544 case TAB(BRANCH,LONG): 3545 if(flagseen['m']){ 3546 if(fragP->fr_opcode[0] == 0x61){ 3547 fragP->fr_opcode[0] = 0x4E; 3548 fragP->fr_opcode[1] = 0xB9; /* JBSR with ABSL LONG offset */ 3549 fix_new(fragP, 3550 fragP->fr_fix, 3551 4, 3552 fragP->fr_symbol, 3553 0, 3554 fragP->fr_offset, 3555 0, 3556 0, 3557 0); 3558 fragP->fr_fix += 4; 3559 ext = 0; 3560 } 3561 else if(fragP->fr_opcode[0] == 0x60){ 3562 fragP->fr_opcode[0]= 0x4E; 3563 fragP->fr_opcode[1]= 0xF9; /* JMP with ABSL LONG offset */ 3564 fix_new(fragP, 3565 fragP->fr_fix, 3566 4, 3567 fragP->fr_symbol, 3568 0, 3569 fragP->fr_offset, 3570 0, 3571 0, 3572 0); 3573 fragP->fr_fix += 4; 3574 ext = 0; 3575 } 3576 else{ 3577 as_bad("Long branch offset not supported."); 3578 } 3579 } 3580 else{ 3581 fragP->fr_opcode[1] = 0xff; 3582 ext = 4; 3583 } 3584 break; 3585 3586 case TAB(BCC68000, LONG): 3587 /* 3588 * Only Bcc 68000 instructions can come here. 3589 * Change bcc into b!cc/jmp absl long. 3590 */ 3591 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */ 3592 fragP->fr_opcode[1] = 0x6; /* branch offset = 6 */ 3593 fragP->fr_opcode[2] = 0x4e; /* put in jmp long (0x4ef9) */ 3594 fragP->fr_opcode[3] = 0xf9; 3595 fragP->fr_fix += 2; /* account for jmp instruction */ 3596 fix_new(fragP, 3597 fragP->fr_fix, 3598 4, 3599 fragP->fr_symbol, 3600 0, 3601 fragP->fr_offset, 3602 0, 3603 0, 3604 0); 3605 fragP->fr_fix += 4; /* account for jmp instruction's displacement */ 3606 ext = 0; 3607 break; 3608 3609 case TAB(DBCC, LONG): 3610 /* 3611 * Only DBcc 68000 instructions can come here. 3612 * Change dbcc into dbcc/jmp absl long. 3613 */ 3614 fragP->fr_opcode[2] = 0x00; /* branch offset = 4 */ 3615 fragP->fr_opcode[3] = 0x04; 3616 fragP->fr_opcode[4] = 0x60; /* put in bra pc+6 */ 3617 fragP->fr_opcode[5] = 0x06; 3618 fragP->fr_opcode[6] = 0x4e; /* put in jmp long (0x4ef9) */ 3619 fragP->fr_opcode[7] = 0xf9; 3620 fragP->fr_fix += 6; /* account for bra/jmp instructions */ 3621 fix_new(fragP, 3622 fragP->fr_fix, 3623 4, 3624 fragP->fr_symbol, 3625 0, 3626 fragP->fr_offset, 3627 0, 3628 0, 3629 0); 3630 fragP->fr_fix += 4; /* account for jmp instruction's displacement */ 3631 ext = 0; 3632 break; 3633 3634 case TAB(FBRANCH, SHORT): 3635 know((fragP->fr_opcode[1] & 0x40) == 0); 3636 ext = 2; 3637 break; 3638 3639 case TAB(FBRANCH, LONG): 3640 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */ 3641 ext = 4; 3642 break; 3643 3644 case TAB(PCREL,SHORT): 3645 ext = 2; 3646 break; 3647 3648 case TAB(PCREL,LONG): 3649 /* 3650 * The thing to do here is force it to ABSOLUTE LONG, since 3651 * PCREL is really trying to shorten an ABSOLUTE address anyway. 3652 */ 3653 if((fragP->fr_opcode[1] & 0x3F) != 0x3A) 3654 as_bad("Internal error (long PC-relative operand) for insn " 3655 "0x%04x at 0x%llx", fragP->fr_opcode[0], 3656 fragP->fr_address); 3657 fragP->fr_opcode[1] &= ~0x3F; 3658 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */ 3659 fix_new(fragP, 3660 fragP->fr_fix, 3661 4, 3662 fragP->fr_symbol, 3663 0, 3664 fragP->fr_offset, 3665 0, 3666 0, 3667 0); 3668 fragP->fr_fix += 4; /* account for the instruction's displacement */ 3669 ext = 0; 3670 break; 3671 3672 default: 3673 break; 3674 } 3675 3676 if(ext != 0){ 3677 md_number_to_chars(buffer_address, (int32_t)disp, (int)ext); 3678 fragP->fr_fix += ext; 3679 } 3680} 3681 3682/* Different values of OK tell what its OK to return. Things that aren't OK are an error (what a shock, no?) 3683 3684 0: Everything is OK 3685 10: Absolute 1:8 only 3686 20: Absolute 0:7 only 3687 30: absolute 0:15 only 3688 40: Absolute 0:31 only 3689 50: absolute 0:127 only 3690 55: absolute -64:63 only 3691 60: absolute -128:127 only 3692 70: absolute 0:4095 only 3693 80: No bignums 3694 3695*/ 3696static 3697int 3698get_num( 3699struct m68k_exp *exp, 3700int ok) 3701{ 3702#ifdef TEST2 3703 int32_t l = 0; 3704 3705 if(!exp->e_beg) 3706 return 0; 3707 if(*exp->e_beg=='0') { 3708 if(exp->e_beg[1]=='x') 3709 sscanf(exp->e_beg+2,"%x",&l); 3710 else 3711 sscanf(exp->e_beg+1,"%O",&l); 3712 return l; 3713 } 3714 return atol(exp->e_beg); 3715#else /* !defined(TEST2) */ 3716 char *save_in; 3717 char c_save; 3718 3719 if(!exp) { 3720 /* Can't do anything */ 3721 return 0; 3722 } 3723 if(!exp->e_beg || !exp->e_end) { 3724 seg(exp)=SEG_ABSOLUTE; 3725 adds(exp)=0; 3726 subs(exp)=0; 3727 offs(exp)= (ok==10) ? 1 : 0; 3728 as_warn("Null expression defaults to %lld", offs(exp)); 3729 return 0; 3730 } 3731 3732 exp->e_siz=0; 3733 if(/* ok!=80 && */exp->e_end[-1]==':' && (exp->e_end-exp->e_beg)>=2) { 3734 switch(exp->e_end[0]) { 3735 case 's': 3736 case 'b': 3737 exp->e_siz=1; 3738 break; 3739 case 'w': 3740 exp->e_siz=2; 3741 break; 3742 case 'l': 3743 exp->e_siz=3; 3744 break; 3745 default: 3746 as_bad("Unknown size for expression \"%c\"",exp->e_end[0]); 3747 } 3748 exp->e_end-=2; 3749 } 3750 c_save=exp->e_end[1]; 3751 exp->e_end[1]='\0'; 3752 save_in=input_line_pointer; 3753 input_line_pointer=exp->e_beg; 3754#ifdef NeXT_MOD /* feature to try to make expressions absolute */ 3755 (void) expression (&(exp->e_exp)); 3756 /* DJA -- we will try to make an absolute number here */ 3757 switch(try_to_make_absolute(&(exp->e_exp))) { 3758#else /* !defined(NeXT_MOD) */ 3759 switch(expression(&(exp->e_exp))) { 3760#endif /* NeXT_MOD */ 3761 case SEG_NONE: 3762 /* Do the same thing the VAX asm does */ 3763 seg(exp)=SEG_ABSOLUTE; 3764 adds(exp)=0; 3765 subs(exp)=0; 3766 offs(exp)=0; 3767 if(ok==10) { 3768 as_warn("expression out of range: defaulting to 1"); 3769 offs(exp)=1; 3770 } 3771 break; 3772 case SEG_ABSOLUTE: 3773 switch(ok) { 3774 case 10: 3775 if(offs(exp)<1 || offs(exp)>8) { 3776 as_warn("expression out of range: defaulting to 1"); 3777 offs(exp)=1; 3778 } 3779 break; 3780 case 20: 3781 if(offs(exp)<0 || offs(exp)>7) 3782 goto outrange; 3783 break; 3784 case 30: 3785 if(offs(exp)<0 || offs(exp)>15) 3786 goto outrange; 3787 break; 3788 case 40: 3789 if(offs(exp)<0 || offs(exp)>32) 3790 goto outrange; 3791 break; 3792 case 50: 3793 if(offs(exp)<0 || offs(exp)>127) 3794 goto outrange; 3795 break; 3796 case 55: 3797 if(offs(exp)<-64 || offs(exp)>63) 3798 goto outrange; 3799 break; 3800 case 60: 3801 if(offs(exp)<-128 || offs(exp)>127) 3802 goto outrange; 3803 break; 3804 case 70: 3805 if(offs(exp)<0 || offs(exp)>4095) { 3806 outrange: 3807 as_warn("expression out of range: defaulting to 0"); 3808 offs(exp)=0; 3809 } 3810 break; 3811 default: 3812 break; 3813 } 3814 break; 3815 case SEG_SECT: 3816 case SEG_UNKNOWN: 3817 case SEG_DIFFSECT: 3818 if(ok>=10 && ok<=70) { 3819 seg(exp)=SEG_ABSOLUTE; 3820 adds(exp)=0; 3821 subs(exp)=0; 3822 offs(exp)= (ok==10) ? 1 : 0; 3823 as_warn("Can't deal with expression \"%s\": defaulting " 3824 "to %lld", exp->e_beg, offs(exp)); 3825 } 3826 break; 3827 case SEG_BIG: 3828#ifndef NeXT_MOD /* fix for bug #8331 */ /* This hack is already done by expr */ 3829 if(ok==80 && offs(exp)<0) { /* HACK! Turn it into a long */ 3830 LITTLENUM_TYPE words[6]; 3831 3832 gen_to_words(words,2,8L);/* These numbers are magic! */ 3833 seg(exp)=SEG_ABSOLUTE; 3834 adds(exp)=0; 3835 subs(exp)=0; 3836 offs(exp)=words[1]|(words[0]<<16); 3837 } else if(ok!=0) { 3838#else /* defined(NeXT_MOD) */ 3839 if(ok!=0) { 3840#endif /* NeXT_MOD */ 3841 seg(exp)=SEG_ABSOLUTE; 3842 adds(exp)=0; 3843 subs(exp)=0; 3844 offs(exp)= (ok==10) ? 1 : 0; 3845 as_warn("Can't deal with expression \"%s\": defaulting " 3846 "to %lld", exp->e_beg, offs(exp)); 3847 } 3848 break; 3849 default: 3850 abort(); 3851 } 3852 if(input_line_pointer!=exp->e_end+1) 3853 as_bad("Ignoring junk after expression"); 3854 exp->e_end[1]=c_save; 3855 input_line_pointer=save_in; 3856 if(exp->e_siz) { 3857 switch(exp->e_siz) { 3858 case 1: 3859 if(!isbyte(offs(exp))) 3860 as_warn("expression doesn't fit in BYTE"); 3861 break; 3862 case 2: 3863 if(!isword(offs(exp))) 3864 as_warn("expression doesn't fit in WORD"); 3865 break; 3866 } 3867 } 3868 return offs(exp); 3869 3870#endif /* !defined(TEST2) */ 3871} 3872 3873/* These are the back-ends for the various machine dependent pseudo-ops. */ 3874void demand_empty_rest_of_line(); /* Hate those extra verbose names */ 3875 3876static 3877void 3878s_even( 3879uintptr_t value) 3880{ 3881 register int power_of_2_alignment; 3882 register int32_t temp_fill; 3883 char fill; 3884 3885 /* power of 2 alignment, 2^1 or 2 byte (even) alignment */ 3886 power_of_2_alignment = 1; 3887 temp_fill = get_absolute_expression (); 3888 md_number_to_chars(&fill, temp_fill, 1); 3889 frag_align(power_of_2_alignment, &fill, 1, 0); 3890 /* 3891 * If this alignment is larger than any previous alignment then this 3892 * becomes the section's alignment. 3893 */ 3894 if(frchain_now->frch_section.align < 3895 (uint32_t)power_of_2_alignment) 3896 frchain_now->frch_section.align = power_of_2_alignment; 3897 demand_empty_rest_of_line(); 3898} 3899 3900static 3901void 3902s_proc( 3903uintptr_t value) 3904{ 3905 demand_empty_rest_of_line(); 3906} 3907 3908/* s_space is defined in read.c .skip is simply an alias to it. */ 3909 3910int 3911md_parse_option( 3912char **argP, 3913int *cntP, 3914char ***vecP) 3915{ 3916 switch(**argP) { 3917 case 'm': 3918 /* Gas simply ignores this option! */ 3919 (*argP)++; 3920 if(**argP=='c') 3921 (*argP)++; 3922 if(!strcmp(*argP,"68000")) 3923 flagseen['m']=2; 3924 else if(!strcmp(*argP,"68010")) { 3925 flagseen['m']=1; 3926 } else if(!strcmp(*argP,"68020")) 3927 flagseen['m']=0; 3928 else 3929 as_warn("Unknown -m option ignored"); 3930 while(**argP) 3931 (*argP)++; 3932 break; 3933 3934 default: 3935 return 0; 3936 } 3937 return 1; 3938} 3939 3940 3941#ifdef TEST2 3942 3943/* TEST2: Test md_assemble() */ 3944 3945static 3946int 3947is_label( 3948char *str) 3949{ 3950 while(*str == ' ') 3951 str++; 3952 while(*str && *str != ' ') 3953 str++; 3954 if(str[-1] == ':' || str[1] == '=') 3955 return(1); 3956 return(0); 3957} 3958 3959void 3960main( 3961int argc, 3962char *argv[], 3963char *envp[]) 3964{ 3965 char buf[120]; 3966 char *cp; 3967 int n; 3968 3969 m68_ip_begin(); 3970 for(;;){ 3971 if(!gets(buf) || !*buf) 3972 break; 3973 if(buf[0] == '|' || buf[1] == '.') 3974 continue; 3975 for(cp = buf; *cp; cp++) 3976 if(*cp == '\t') 3977 *cp = ' '; 3978 if(is_label(buf)) 3979 continue; 3980 memset(&the_ins, '\0', sizeof(the_ins)); 3981 m68_ip(buf); 3982 if(the_ins.error){ 3983 printf("Error %s in %s\n", the_ins.error, buf); 3984 } 3985 else{ 3986 printf("Opcode(%d.%s): ", the_ins.numo, the_ins.args); 3987 for(n = 0; n < the_ins.numo; n++) 3988 printf(" 0x%x", the_ins.opcode[n] & 0xffff); 3989 printf(" "); 3990 print_the_insn(&the_ins.opcode[0], stdout); 3991 (void)putchar('\n'); 3992 } 3993 for(n = 0; n < strlen(the_ins.args) / 2; n++){ 3994 if(the_ins.operands[n].error){ 3995 printf("op%d Error %s in %s\n", 3996 n, the_ins.operands[n].error, buf); 3997 continue; 3998 } 3999 printf("mode %d, reg %d, ", 4000 the_ins.operands[n].mode, the_ins.operands[n].reg); 4001 if(the_ins.operands[n].con1) 4002 printf("con1: '%.*s', ", 4003 1 + the_ins.operands[n].con1->e_end - 4004 the_ins.operands[n].con1->e_beg, 4005 the_ins.operands[n].con1->e_beg); 4006 printf("ireg %d, isiz %d, imul %d, ", 4007 the_ins.operands[n].ireg, 4008 the_ins.operands[n].isiz, 4009 the_ins.operands[n].imul); 4010 if(the_ins.operands[n].con2) 4011 printf("con2: '%.*s',", 4012 1 + the_ins.operands[n].con2->e_end - 4013 the_ins.operands[n].con2->e_beg, 4014 the_ins.operands[n].con2->e_beg); 4015 (void)putchar('\n'); 4016 } 4017 } 4018 m68_ip_end(); 4019} 4020#endif /* TEST2 */ 4021