1264095Semaste/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note 2264095Semaste * 3264095Semaste * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. 4264095Semaste * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 5264095Semaste */ 6264095Semaste 7264095Semaste#ifndef QAIC_ACCEL_H_ 8264095Semaste#define QAIC_ACCEL_H_ 9264095Semaste 10264095Semaste#include "drm.h" 11264095Semaste 12264095Semaste#if defined(__cplusplus) 13264095Semasteextern "C" { 14264095Semaste#endif 15264095Semaste 16264095Semaste/* The length(4K) includes len and count fields of qaic_manage_msg */ 17264095Semaste#define QAIC_MANAGE_MAX_MSG_LENGTH SZ_4K 18264095Semaste 19264095Semaste/* semaphore flags */ 20264095Semaste#define QAIC_SEM_INSYNCFENCE 2 21264095Semaste#define QAIC_SEM_OUTSYNCFENCE 1 22264095Semaste 23264095Semaste/* Semaphore commands */ 24264095Semaste#define QAIC_SEM_NOP 0 25264095Semaste#define QAIC_SEM_INIT 1 26264095Semaste#define QAIC_SEM_INC 2 27264095Semaste#define QAIC_SEM_DEC 3 28264095Semaste#define QAIC_SEM_WAIT_EQUAL 4 29264095Semaste#define QAIC_SEM_WAIT_GT_EQ 5 /* Greater than or equal */ 30264095Semaste#define QAIC_SEM_WAIT_GT_0 6 /* Greater than 0 */ 31264095Semaste 32264095Semaste#define QAIC_TRANS_UNDEFINED 0 33264095Semaste#define QAIC_TRANS_PASSTHROUGH_FROM_USR 1 34264095Semaste#define QAIC_TRANS_PASSTHROUGH_TO_USR 2 35264095Semaste#define QAIC_TRANS_PASSTHROUGH_FROM_DEV 3 36264095Semaste#define QAIC_TRANS_PASSTHROUGH_TO_DEV 4 37264095Semaste#define QAIC_TRANS_DMA_XFER_FROM_USR 5 38264095Semaste#define QAIC_TRANS_DMA_XFER_TO_DEV 6 39264095Semaste#define QAIC_TRANS_ACTIVATE_FROM_USR 7 40264095Semaste#define QAIC_TRANS_ACTIVATE_FROM_DEV 8 41264095Semaste#define QAIC_TRANS_ACTIVATE_TO_DEV 9 42264095Semaste#define QAIC_TRANS_DEACTIVATE_FROM_USR 10 43264095Semaste#define QAIC_TRANS_DEACTIVATE_FROM_DEV 11 44264095Semaste#define QAIC_TRANS_STATUS_FROM_USR 12 45264095Semaste#define QAIC_TRANS_STATUS_TO_USR 13 46264095Semaste#define QAIC_TRANS_STATUS_FROM_DEV 14 47264095Semaste#define QAIC_TRANS_STATUS_TO_DEV 15 48264095Semaste#define QAIC_TRANS_TERMINATE_FROM_DEV 16 49264095Semaste#define QAIC_TRANS_TERMINATE_TO_DEV 17 50264095Semaste#define QAIC_TRANS_DMA_XFER_CONT 18 51264095Semaste#define QAIC_TRANS_VALIDATE_PARTITION_FROM_DEV 19 52264095Semaste#define QAIC_TRANS_VALIDATE_PARTITION_TO_DEV 20 53264095Semaste 54264095Semaste/** 55264095Semaste * struct qaic_manage_trans_hdr - Header for a transaction in a manage message. 56264095Semaste * @type: In. Identifies this transaction. See QAIC_TRANS_* defines. 57264095Semaste * @len: In. Length of this transaction, including this header. 58264095Semaste */ 59264095Semastestruct qaic_manage_trans_hdr { 60264095Semaste __u32 type; 61264095Semaste __u32 len; 62264095Semaste}; 63271880Semaste 64264095Semaste/** 65264095Semaste * struct qaic_manage_trans_passthrough - Defines a passthrough transaction. 66264095Semaste * @hdr: In. Header to identify this transaction. 67264095Semaste * @data: In. Payload of this ransaction. Opaque to the driver. Userspace must 68264095Semaste * encode in little endian and align/pad to 64-bit. 69264095Semaste */ 70264095Semastestruct qaic_manage_trans_passthrough { 71264095Semaste struct qaic_manage_trans_hdr hdr; 72264095Semaste __u8 data[]; 73264095Semaste}; 74271880Semaste 75271880Semaste/** 76271880Semaste * struct qaic_manage_trans_dma_xfer - Defines a DMA transfer transaction. 77271880Semaste * @hdr: In. Header to identify this transaction. 78271880Semaste * @tag: In. Identified this transfer in other transactions. Opaque to the 79271880Semaste * driver. 80271880Semaste * @pad: Structure padding. 81271880Semaste * @addr: In. Address of the data to DMA to the device. 82264095Semaste * @size: In. Length of the data to DMA to the device. 83264095Semaste */ 84264095Semastestruct qaic_manage_trans_dma_xfer { 85264095Semaste struct qaic_manage_trans_hdr hdr; 86264095Semaste __u32 tag; 87264095Semaste __u32 pad; 88264095Semaste __u64 addr; 89264095Semaste __u64 size; 90264095Semaste}; 91264095Semaste 92264095Semaste/** 93264095Semaste * struct qaic_manage_trans_activate_to_dev - Defines an activate request. 94264095Semaste * @hdr: In. Header to identify this transaction. 95264095Semaste * @queue_size: In. Number of elements for DBC request and response queues. 96264095Semaste * @eventfd: Unused. 97264095Semaste * @options: In. Device specific options for this activate. 98264095Semaste * @pad: Structure padding. Must be 0. 99264095Semaste */ 100264095Semastestruct qaic_manage_trans_activate_to_dev { 101264095Semaste struct qaic_manage_trans_hdr hdr; 102264095Semaste __u32 queue_size; 103264095Semaste __u32 eventfd; 104264095Semaste __u32 options; 105264095Semaste __u32 pad; 106264095Semaste}; 107264095Semaste 108264095Semaste/** 109264095Semaste * struct qaic_manage_trans_activate_from_dev - Defines an activate response. 110264095Semaste * @hdr: Out. Header to identify this transaction. 111264095Semaste * @status: Out. Return code of the request from the device. 112264095Semaste * @dbc_id: Out. Id of the assigned DBC for successful request. 113264095Semaste * @options: Out. Device specific options for this activate. 114264095Semaste */ 115264095Semastestruct qaic_manage_trans_activate_from_dev { 116264095Semaste struct qaic_manage_trans_hdr hdr; 117264095Semaste __u32 status; 118264095Semaste __u32 dbc_id; 119264095Semaste __u64 options; 120264095Semaste}; 121264095Semaste 122264095Semaste/** 123264095Semaste * struct qaic_manage_trans_deactivate - Defines a deactivate request. 124264095Semaste * @hdr: In. Header to identify this transaction. 125264095Semaste * @dbc_id: In. Id of assigned DBC. 126264095Semaste * @pad: Structure padding. Must be 0. 127264095Semaste */ 128264095Semastestruct qaic_manage_trans_deactivate { 129264095Semaste struct qaic_manage_trans_hdr hdr; 130264095Semaste __u32 dbc_id; 131264095Semaste __u32 pad; 132264095Semaste}; 133264095Semaste 134264095Semaste/** 135264095Semaste * struct qaic_manage_trans_status_to_dev - Defines a status request. 136264095Semaste * @hdr: In. Header to identify this transaction. 137264095Semaste */ 138264095Semastestruct qaic_manage_trans_status_to_dev { 139264095Semaste struct qaic_manage_trans_hdr hdr; 140264095Semaste}; 141264095Semaste 142264095Semaste/** 143264095Semaste * struct qaic_manage_trans_status_from_dev - Defines a status response. 144264095Semaste * @hdr: Out. Header to identify this transaction. 145264095Semaste * @major: Out. NNC protocol version major number. 146264095Semaste * @minor: Out. NNC protocol version minor number. 147264095Semaste * @status: Out. Return code from device. 148264095Semaste * @status_flags: Out. Flags from device. Bit 0 indicates if CRCs are required. 149264095Semaste */ 150264095Semastestruct qaic_manage_trans_status_from_dev { 151264095Semaste struct qaic_manage_trans_hdr hdr; 152264095Semaste __u16 major; 153264095Semaste __u16 minor; 154264095Semaste __u32 status; 155264095Semaste __u64 status_flags; 156264095Semaste}; 157264095Semaste 158264095Semaste/** 159264095Semaste * struct qaic_manage_msg - Defines a message to the device. 160264095Semaste * @len: In. Length of all the transactions contained within this message. 161264095Semaste * @count: In. Number of transactions in this message. 162264095Semaste * @data: In. Address to an array where the transactions can be found. 163264095Semaste */ 164264095Semastestruct qaic_manage_msg { 165264095Semaste __u32 len; 166264095Semaste __u32 count; 167264095Semaste __u64 data; 168264095Semaste}; 169264095Semaste 170264095Semaste/** 171264095Semaste * struct qaic_create_bo - Defines a request to create a buffer object. 172264095Semaste * @size: In. Size of the buffer in bytes. 173264095Semaste * @handle: Out. GEM handle for the BO. 174264095Semaste * @pad: Structure padding. Must be 0. 175264095Semaste */ 176264095Semastestruct qaic_create_bo { 177264095Semaste __u64 size; 178264095Semaste __u32 handle; 179264095Semaste __u32 pad; 180264095Semaste}; 181264095Semaste 182264095Semaste/** 183264095Semaste * struct qaic_mmap_bo - Defines a request to prepare a BO for mmap(). 184264095Semaste * @handle: In. Handle of the GEM BO to prepare for mmap(). 185264095Semaste * @pad: Structure padding. Must be 0. 186264095Semaste * @offset: Out. Offset value to provide to mmap(). 187264095Semaste */ 188264095Semastestruct qaic_mmap_bo { 189264095Semaste __u32 handle; 190264095Semaste __u32 pad; 191264095Semaste __u64 offset; 192264095Semaste}; 193264095Semaste 194264095Semaste/** 195264095Semaste * struct qaic_sem - Defines a semaphore command for a BO slice. 196264095Semaste * @val: In. Only lower 12 bits are valid. 197264095Semaste * @index: In. Only lower 5 bits are valid. 198264095Semaste * @presync: In. 1 if presync operation, 0 if postsync. 199264095Semaste * @cmd: In. One of QAIC_SEM_*. 200264095Semaste * @flags: In. Bitfield. See QAIC_SEM_INSYNCFENCE and QAIC_SEM_OUTSYNCFENCE 201264095Semaste * @pad: Structure padding. Must be 0. 202264095Semaste */ 203264095Semastestruct qaic_sem { 204264095Semaste __u16 val; 205264095Semaste __u8 index; 206264095Semaste __u8 presync; 207264095Semaste __u8 cmd; 208264095Semaste __u8 flags; 209264095Semaste __u16 pad; 210264095Semaste}; 211264095Semaste 212264095Semaste/** 213264095Semaste * struct qaic_attach_slice_entry - Defines a single BO slice. 214264095Semaste * @size: In. Size of this slice in bytes. 215264095Semaste * @sem0: In. Semaphore command 0. Must be 0 is not valid. 216264095Semaste * @sem1: In. Semaphore command 1. Must be 0 is not valid. 217264095Semaste * @sem2: In. Semaphore command 2. Must be 0 is not valid. 218264095Semaste * @sem3: In. Semaphore command 3. Must be 0 is not valid. 219264095Semaste * @dev_addr: In. Device address this slice pushes to or pulls from. 220264095Semaste * @db_addr: In. Address of the doorbell to ring. 221264095Semaste * @db_data: In. Data to write to the doorbell. 222264095Semaste * @db_len: In. Size of the doorbell data in bits - 32, 16, or 8. 0 is for 223264095Semaste * inactive doorbells. 224264095Semaste * @offset: In. Start of this slice as an offset from the start of the BO. 225264095Semaste */ 226264095Semastestruct qaic_attach_slice_entry { 227264095Semaste __u64 size; 228264095Semaste struct qaic_sem sem0; 229264095Semaste struct qaic_sem sem1; 230264095Semaste struct qaic_sem sem2; 231264095Semaste struct qaic_sem sem3; 232264095Semaste __u64 dev_addr; 233264095Semaste __u64 db_addr; 234264095Semaste __u32 db_data; 235264095Semaste __u32 db_len; 236264095Semaste __u64 offset; 237264095Semaste}; 238264095Semaste 239264095Semaste/** 240264095Semaste * struct qaic_attach_slice_hdr - Defines metadata for a set of BO slices. 241264095Semaste * @count: In. Number of slices for this BO. 242264095Semaste * @dbc_id: In. Associate the sliced BO with this DBC. 243264095Semaste * @handle: In. GEM handle of the BO to slice. 244264095Semaste * @dir: In. Direction of data flow. 1 = DMA_TO_DEVICE, 2 = DMA_FROM_DEVICE 245264095Semaste * @size: Deprecated. This value is ignored and size of @handle is used instead. 246264095Semaste */ 247264095Semastestruct qaic_attach_slice_hdr { 248264095Semaste __u32 count; 249264095Semaste __u32 dbc_id; 250264095Semaste __u32 handle; 251264095Semaste __u32 dir; 252264095Semaste __u64 size; 253264095Semaste}; 254264095Semaste 255264095Semaste/** 256264095Semaste * struct qaic_attach_slice - Defines a set of BO slices. 257264095Semaste * @hdr: In. Metadata of the set of slices. 258264095Semaste * @data: In. Pointer to an array containing the slice definitions. 259264095Semaste */ 260264095Semastestruct qaic_attach_slice { 261264095Semaste struct qaic_attach_slice_hdr hdr; 262264095Semaste __u64 data; 263264095Semaste}; 264264095Semaste 265264095Semaste/** 266264095Semaste * struct qaic_execute_entry - Defines a BO to submit to the device. 267264095Semaste * @handle: In. GEM handle of the BO to commit to the device. 268264095Semaste * @dir: In. Direction of data. 1 = to device, 2 = from device. 269264095Semaste */ 270264095Semastestruct qaic_execute_entry { 271264095Semaste __u32 handle; 272264095Semaste __u32 dir; 273264095Semaste}; 274264095Semaste 275264095Semaste/** 276264095Semaste * struct qaic_partial_execute_entry - Defines a BO to resize and submit. 277264095Semaste * @handle: In. GEM handle of the BO to commit to the device. 278264095Semaste * @dir: In. Direction of data. 1 = to device, 2 = from device. 279264095Semaste * @resize: In. New size of the BO. Must be <= the original BO size. 280264095Semaste * @resize as 0 would be interpreted as no DMA transfer is 281264095Semaste * involved. 282264095Semaste */ 283264095Semastestruct qaic_partial_execute_entry { 284264095Semaste __u32 handle; 285264095Semaste __u32 dir; 286264095Semaste __u64 resize; 287264095Semaste}; 288264095Semaste 289264095Semaste/** 290264095Semaste * struct qaic_execute_hdr - Defines metadata for BO submission. 291264095Semaste * @count: In. Number of BOs to submit. 292264095Semaste * @dbc_id: In. DBC to submit the BOs on. 293264095Semaste */ 294264095Semastestruct qaic_execute_hdr { 295264095Semaste __u32 count; 296264095Semaste __u32 dbc_id; 297264095Semaste}; 298264095Semaste 299264095Semaste/** 300264095Semaste * struct qaic_execute - Defines a list of BOs to submit to the device. 301264095Semaste * @hdr: In. BO list metadata. 302264095Semaste * @data: In. Pointer to an array of BOs to submit. 303264095Semaste */ 304264095Semastestruct qaic_execute { 305264095Semaste struct qaic_execute_hdr hdr; 306264095Semaste __u64 data; 307264095Semaste}; 308264095Semaste 309264095Semaste/** 310264095Semaste * struct qaic_wait - Defines a blocking wait for BO execution. 311264095Semaste * @handle: In. GEM handle of the BO to wait on. 312264095Semaste * @timeout: In. Maximum time in ms to wait for the BO. 313264095Semaste * @dbc_id: In. DBC the BO is submitted to. 314264095Semaste * @pad: Structure padding. Must be 0. 315264095Semaste */ 316264095Semastestruct qaic_wait { 317264095Semaste __u32 handle; 318264095Semaste __u32 timeout; 319264095Semaste __u32 dbc_id; 320264095Semaste __u32 pad; 321264095Semaste}; 322264095Semaste 323264095Semaste/** 324264095Semaste * struct qaic_perf_stats_hdr - Defines metadata for getting BO perf info. 325264095Semaste * @count: In. Number of BOs requested. 326264095Semaste * @pad: Structure padding. Must be 0. 327264095Semaste * @dbc_id: In. DBC the BO are associated with. 328264095Semaste */ 329264095Semastestruct qaic_perf_stats_hdr { 330264095Semaste __u16 count; 331264095Semaste __u16 pad; 332264095Semaste __u32 dbc_id; 333264095Semaste}; 334264095Semaste 335264095Semaste/** 336264095Semaste * struct qaic_perf_stats - Defines a request for getting BO perf info. 337264095Semaste * @hdr: In. Request metadata 338264095Semaste * @data: In. Pointer to array of stats structures that will receive the data. 339264095Semaste */ 340264095Semastestruct qaic_perf_stats { 341264095Semaste struct qaic_perf_stats_hdr hdr; 342264095Semaste __u64 data; 343264095Semaste}; 344264095Semaste 345264095Semaste/** 346264095Semaste * struct qaic_perf_stats_entry - Defines a BO perf info. 347264095Semaste * @handle: In. GEM handle of the BO to get perf stats for. 348264095Semaste * @queue_level_before: Out. Number of elements in the queue before this BO 349264095Semaste * was submitted. 350264095Semaste * @num_queue_element: Out. Number of elements added to the queue to submit 351264095Semaste * this BO. 352264095Semaste * @submit_latency_us: Out. Time taken by the driver to submit this BO. 353264095Semaste * @device_latency_us: Out. Time taken by the device to execute this BO. 354264095Semaste * @pad: Structure padding. Must be 0. 355264095Semaste */ 356264095Semastestruct qaic_perf_stats_entry { 357264095Semaste __u32 handle; 358264095Semaste __u32 queue_level_before; 359264095Semaste __u32 num_queue_element; 360264095Semaste __u32 submit_latency_us; 361264095Semaste __u32 device_latency_us; 362264095Semaste __u32 pad; 363264095Semaste}; 364264095Semaste 365264095Semaste/** 366264095Semaste * struct qaic_detach_slice - Detaches slicing configuration from BO. 367264095Semaste * @handle: In. GEM handle of the BO to detach slicing configuration. 368264095Semaste * @pad: Structure padding. Must be 0. 369264095Semaste */ 370struct qaic_detach_slice { 371 __u32 handle; 372 __u32 pad; 373}; 374 375#define DRM_QAIC_MANAGE 0x00 376#define DRM_QAIC_CREATE_BO 0x01 377#define DRM_QAIC_MMAP_BO 0x02 378#define DRM_QAIC_ATTACH_SLICE_BO 0x03 379#define DRM_QAIC_EXECUTE_BO 0x04 380#define DRM_QAIC_PARTIAL_EXECUTE_BO 0x05 381#define DRM_QAIC_WAIT_BO 0x06 382#define DRM_QAIC_PERF_STATS_BO 0x07 383#define DRM_QAIC_DETACH_SLICE_BO 0x08 384 385#define DRM_IOCTL_QAIC_MANAGE DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_MANAGE, struct qaic_manage_msg) 386#define DRM_IOCTL_QAIC_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_CREATE_BO, struct qaic_create_bo) 387#define DRM_IOCTL_QAIC_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_MMAP_BO, struct qaic_mmap_bo) 388#define DRM_IOCTL_QAIC_ATTACH_SLICE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_ATTACH_SLICE_BO, struct qaic_attach_slice) 389#define DRM_IOCTL_QAIC_EXECUTE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_EXECUTE_BO, struct qaic_execute) 390#define DRM_IOCTL_QAIC_PARTIAL_EXECUTE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_PARTIAL_EXECUTE_BO, struct qaic_execute) 391#define DRM_IOCTL_QAIC_WAIT_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_WAIT_BO, struct qaic_wait) 392#define DRM_IOCTL_QAIC_PERF_STATS_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_PERF_STATS_BO, struct qaic_perf_stats) 393#define DRM_IOCTL_QAIC_DETACH_SLICE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_DETACH_SLICE_BO, struct qaic_detach_slice) 394 395#if defined(__cplusplus) 396} 397#endif 398 399#endif /* QAIC_ACCEL_H_ */ 400