1189251Ssam/* SPDX-License-Identifier: GPL-2.0-or-later */ 2189251Ssam#ifndef __SOUND_CS4231_REGS_H 3252726Srpaulo#define __SOUND_CS4231_REGS_H 4189251Ssam 5252726Srpaulo/* 6252726Srpaulo * Copyright (c) by Jaroslav Kysela <perex@perex.cz> 7189251Ssam * Definitions for CS4231 & InterWave chips & compatible chips registers 8189251Ssam */ 9189251Ssam 10189251Ssam/* IO ports */ 11189251Ssam 12214734Srpaulo#define CS4231P(x) (c_d_c_CS4231##x) 13189251Ssam 14189251Ssam#define c_d_c_CS4231REGSEL 0 15189251Ssam#define c_d_c_CS4231REG 1 16189251Ssam#define c_d_c_CS4231STATUS 2 17189251Ssam#define c_d_c_CS4231PIO 3 18189251Ssam 19189251Ssam/* codec registers */ 20189251Ssam 21189251Ssam#define CS4231_LEFT_INPUT 0x00 /* left input control */ 22189251Ssam#define CS4231_RIGHT_INPUT 0x01 /* right input control */ 23189251Ssam#define CS4231_AUX1_LEFT_INPUT 0x02 /* left AUX1 input control */ 24252726Srpaulo#define CS4231_AUX1_RIGHT_INPUT 0x03 /* right AUX1 input control */ 25252726Srpaulo#define CS4231_AUX2_LEFT_INPUT 0x04 /* left AUX2 input control */ 26189251Ssam#define CS4231_AUX2_RIGHT_INPUT 0x05 /* right AUX2 input control */ 27189251Ssam#define CS4231_LEFT_OUTPUT 0x06 /* left output control register */ 28189251Ssam#define CS4231_RIGHT_OUTPUT 0x07 /* right output control register */ 29189251Ssam#define CS4231_PLAYBK_FORMAT 0x08 /* clock and data format - playback - bits 7-0 MCE */ 30189251Ssam#define CS4231_IFACE_CTRL 0x09 /* interface control - bits 7-2 MCE */ 31189251Ssam#define CS4231_PIN_CTRL 0x0a /* pin control */ 32189251Ssam#define CS4231_TEST_INIT 0x0b /* test and initialization */ 33189251Ssam#define CS4231_MISC_INFO 0x0c /* miscellaneous information */ 34189251Ssam#define CS4231_LOOPBACK 0x0d /* loopback control */ 35189251Ssam#define CS4231_PLY_UPR_CNT 0x0e /* playback upper base count */ 36189251Ssam#define CS4231_PLY_LWR_CNT 0x0f /* playback lower base count */ 37189251Ssam#define CS4231_ALT_FEATURE_1 0x10 /* alternate #1 feature enable */ 38189251Ssam#define AD1845_AF1_MIC_LEFT 0x10 /* alternate #1 feature + MIC left */ 39189251Ssam#define CS4231_ALT_FEATURE_2 0x11 /* alternate #2 feature enable */ 40189251Ssam#define AD1845_AF2_MIC_RIGHT 0x11 /* alternate #2 feature + MIC right */ 41189251Ssam#define CS4231_LEFT_LINE_IN 0x12 /* left line input control */ 42189251Ssam#define CS4231_RIGHT_LINE_IN 0x13 /* right line input control */ 43189251Ssam#define CS4231_TIMER_LOW 0x14 /* timer low byte */ 44189251Ssam#define CS4231_TIMER_HIGH 0x15 /* timer high byte */ 45252726Srpaulo#define CS4231_LEFT_MIC_INPUT 0x16 /* left MIC input control register (InterWave only) */ 46252726Srpaulo#define AD1845_UPR_FREQ_SEL 0x16 /* upper byte of frequency select */ 47252726Srpaulo#define CS4231_RIGHT_MIC_INPUT 0x17 /* right MIC input control register (InterWave only) */ 48252726Srpaulo#define AD1845_LWR_FREQ_SEL 0x17 /* lower byte of frequency select */ 49189251Ssam#define CS4236_EXT_REG 0x17 /* extended register access */ 50189251Ssam#define CS4231_IRQ_STATUS 0x18 /* irq status register */ 51189251Ssam#define CS4231_LINE_LEFT_OUTPUT 0x19 /* left line output control register (InterWave only) */ 52189251Ssam#define CS4231_VERSION 0x19 /* CS4231(A) - version values */ 53189251Ssam#define CS4231_MONO_CTRL 0x1a /* mono input/output control */ 54189251Ssam#define CS4231_LINE_RIGHT_OUTPUT 0x1b /* right line output control register (InterWave only) */ 55189251Ssam#define AD1845_PWR_DOWN 0x1b /* power down control */ 56189251Ssam#define CS4235_LEFT_MASTER 0x1b /* left master output control */ 57189251Ssam#define CS4231_REC_FORMAT 0x1c /* clock and data format - record - bits 7-0 MCE */ 58189251Ssam#define AD1845_CLOCK 0x1d /* crystal clock select and total power down */ 59189251Ssam#define CS4235_RIGHT_MASTER 0x1d /* right master output control */ 60189251Ssam#define CS4231_REC_UPR_CNT 0x1e /* record upper count */ 61189251Ssam#define CS4231_REC_LWR_CNT 0x1f /* record lower count */ 62189251Ssam 63189251Ssam/* definitions for codec register select port - CODECP( REGSEL ) */ 64189251Ssam 65189251Ssam#define CS4231_INIT 0x80 /* CODEC is initializing */ 66252726Srpaulo#define CS4231_MCE 0x40 /* mode change enable */ 67252726Srpaulo#define CS4231_TRD 0x20 /* transfer request disable */ 68189251Ssam 69189251Ssam/* definitions for codec status register - CODECP( STATUS ) */ 70189251Ssam 71189251Ssam#define CS4231_GLOBALIRQ 0x01 /* IRQ is active */ 72252726Srpaulo 73252726Srpaulo/* definitions for codec irq status */ 74252726Srpaulo 75252726Srpaulo#define CS4231_PLAYBACK_IRQ 0x10 76252726Srpaulo#define CS4231_RECORD_IRQ 0x20 77252726Srpaulo#define CS4231_TIMER_IRQ 0x40 78252726Srpaulo#define CS4231_ALL_IRQS 0x70 79252726Srpaulo#define CS4231_REC_UNDERRUN 0x08 80252726Srpaulo#define CS4231_REC_OVERRUN 0x04 81252726Srpaulo#define CS4231_PLY_OVERRUN 0x02 82252726Srpaulo#define CS4231_PLY_UNDERRUN 0x01 83252726Srpaulo 84252726Srpaulo/* definitions for CS4231_LEFT_INPUT and CS4231_RIGHT_INPUT registers */ 85252726Srpaulo 86252726Srpaulo#define CS4231_ENABLE_MIC_GAIN 0x20 87252726Srpaulo 88252726Srpaulo#define CS4231_MIXS_LINE 0x00 89252726Srpaulo#define CS4231_MIXS_AUX1 0x40 90252726Srpaulo#define CS4231_MIXS_MIC 0x80 91252726Srpaulo#define CS4231_MIXS_ALL 0xc0 92252726Srpaulo 93252726Srpaulo/* definitions for clock and data format register - CS4231_PLAYBK_FORMAT */ 94252726Srpaulo 95252726Srpaulo#define CS4231_LINEAR_8 0x00 /* 8-bit unsigned data */ 96252726Srpaulo#define CS4231_ALAW_8 0x60 /* 8-bit A-law companded */ 97252726Srpaulo#define CS4231_ULAW_8 0x20 /* 8-bit U-law companded */ 98252726Srpaulo#define CS4231_LINEAR_16 0x40 /* 16-bit twos complement data - little endian */ 99189251Ssam#define CS4231_LINEAR_16_BIG 0xc0 /* 16-bit twos complement data - big endian */ 100189251Ssam#define CS4231_ADPCM_16 0xa0 /* 16-bit ADPCM */ 101189251Ssam#define CS4231_STEREO 0x10 /* stereo mode */ 102189251Ssam/* bits 3-1 define frequency divisor */ 103189251Ssam#define CS4231_XTAL1 0x00 /* 24.576 crystal */ 104189251Ssam#define CS4231_XTAL2 0x01 /* 16.9344 crystal */ 105189251Ssam 106189251Ssam/* definitions for interface control register - CS4231_IFACE_CTRL */ 107189251Ssam 108189251Ssam#define CS4231_RECORD_PIO 0x80 /* record PIO enable */ 109189251Ssam#define CS4231_PLAYBACK_PIO 0x40 /* playback PIO enable */ 110189251Ssam#define CS4231_CALIB_MODE 0x18 /* calibration mode bits */ 111189251Ssam#define CS4231_AUTOCALIB 0x08 /* auto calibrate */ 112189251Ssam#define CS4231_SINGLE_DMA 0x04 /* use single DMA channel */ 113189251Ssam#define CS4231_RECORD_ENABLE 0x02 /* record enable */ 114189251Ssam#define CS4231_PLAYBACK_ENABLE 0x01 /* playback enable */ 115189251Ssam 116189251Ssam/* definitions for pin control register - CS4231_PIN_CTRL */ 117189251Ssam 118189251Ssam#define CS4231_IRQ_ENABLE 0x02 /* enable IRQ */ 119189251Ssam#define CS4231_XCTL1 0x40 /* external control #1 */ 120189251Ssam#define CS4231_XCTL0 0x80 /* external control #0 */ 121189251Ssam 122189251Ssam/* definitions for test and init register - CS4231_TEST_INIT */ 123189251Ssam 124189251Ssam#define CS4231_CALIB_IN_PROGRESS 0x20 /* auto calibrate in progress */ 125189251Ssam#define CS4231_DMA_REQUEST 0x10 /* DMA request in progress */ 126189251Ssam 127189251Ssam/* definitions for misc control register - CS4231_MISC_INFO */ 128189251Ssam 129189251Ssam#define CS4231_MODE2 0x40 /* MODE 2 */ 130189251Ssam#define CS4231_IW_MODE3 0x6c /* MODE 3 - InterWave enhanced mode */ 131189251Ssam#define CS4231_4236_MODE3 0xe0 /* MODE 3 - CS4236+ enhanced mode */ 132189251Ssam 133189251Ssam/* definitions for alternate feature 1 register - CS4231_ALT_FEATURE_1 */ 134189251Ssam 135189251Ssam#define CS4231_DACZ 0x01 /* zero DAC when underrun */ 136189251Ssam#define CS4231_TIMER_ENABLE 0x40 /* codec timer enable */ 137189251Ssam#define CS4231_OLB 0x80 /* output level bit */ 138189251Ssam 139189251Ssam/* definitions for Extended Registers - CS4236+ */ 140189251Ssam 141189251Ssam#define CS4236_REG(i23val) (((i23val << 2) & 0x10) | ((i23val >> 4) & 0x0f)) 142252726Srpaulo#define CS4236_I23VAL(reg) ((((reg)&0xf) << 4) | (((reg)&0x10) >> 2) | 0x8) 143189251Ssam 144189251Ssam#define CS4236_LEFT_LINE 0x08 /* left LINE alternate volume */ 145189251Ssam#define CS4236_RIGHT_LINE 0x18 /* right LINE alternate volume */ 146189251Ssam#define CS4236_LEFT_MIC 0x28 /* left MIC volume */ 147189251Ssam#define CS4236_RIGHT_MIC 0x38 /* right MIC volume */ 148189251Ssam#define CS4236_LEFT_MIX_CTRL 0x48 /* synthesis and left input mixer control */ 149189251Ssam#define CS4236_RIGHT_MIX_CTRL 0x58 /* right input mixer control */ 150189251Ssam#define CS4236_LEFT_FM 0x68 /* left FM volume */ 151189251Ssam#define CS4236_RIGHT_FM 0x78 /* right FM volume */ 152189251Ssam#define CS4236_LEFT_DSP 0x88 /* left DSP serial port volume */ 153189251Ssam#define CS4236_RIGHT_DSP 0x98 /* right DSP serial port volume */ 154189251Ssam#define CS4236_RIGHT_LOOPBACK 0xa8 /* right loopback monitor volume */ 155189251Ssam#define CS4236_DAC_MUTE 0xb8 /* DAC mute and IFSE enable */ 156189251Ssam#define CS4236_ADC_RATE 0xc8 /* indenpendent ADC sample frequency */ 157189251Ssam#define CS4236_DAC_RATE 0xd8 /* indenpendent DAC sample frequency */ 158189251Ssam#define CS4236_LEFT_MASTER 0xe8 /* left master digital audio volume */ 159189251Ssam#define CS4236_RIGHT_MASTER 0xf8 /* right master digital audio volume */ 160189251Ssam#define CS4236_LEFT_WAVE 0x0c /* left wavetable serial port volume */ 161189251Ssam#define CS4236_RIGHT_WAVE 0x1c /* right wavetable serial port volume */ 162189251Ssam#define CS4236_VERSION 0x9c /* chip version and ID */ 163189251Ssam 164189251Ssam/* definitions for extended registers - OPTI93X */ 165189251Ssam#define OPTi931_AUX_LEFT_INPUT 0x10 166189251Ssam#define OPTi931_AUX_RIGHT_INPUT 0x11 167189251Ssam#define OPTi93X_MIC_LEFT_INPUT 0x14 168189251Ssam#define OPTi93X_MIC_RIGHT_INPUT 0x15 169189251Ssam#define OPTi93X_OUT_LEFT 0x16 170189251Ssam#define OPTi93X_OUT_RIGHT 0x17 171189251Ssam 172189251Ssam#endif /* __SOUND_CS4231_REGS_H */ 173189251Ssam