1139724Simp/* SPDX-License-Identifier: GPL-2.0 */ 24Srgrimes#ifndef __LINUX_SPI_EEPROM_H 34Srgrimes#define __LINUX_SPI_EEPROM_H 44Srgrimes 58876Srgrimes#include <linux/memory.h> 64Srgrimes 74Srgrimes/* 84Srgrimes * Put one of these structures in platform_data for SPI EEPROMS handled 94Srgrimes * by the "at25" driver. On SPI, most EEPROMS understand the same core 104Srgrimes * command set. If you need to support EEPROMs that don't yet fit, add 118876Srgrimes * flags to support those protocol options. These values all come from 128876Srgrimes * the chip datasheets. 134Srgrimes */ 144Srgrimesstruct spi_eeprom { 158876Srgrimes u32 byte_len; 164Srgrimes char name[10]; 178876Srgrimes u32 page_size; /* for writes */ 184Srgrimes u16 flags; 194Srgrimes#define EE_ADDR1 0x0001 /* 8 bit addrs */ 204Srgrimes#define EE_ADDR2 0x0002 /* 16 bit addrs */ 214Srgrimes#define EE_ADDR3 0x0004 /* 24 bit addrs */ 228876Srgrimes#define EE_READONLY 0x0008 /* disallow writes */ 234Srgrimes 244Srgrimes /* 254Srgrimes * Certain EEPROMS have a size that is larger than the number of address 26620Srgrimes * bytes would allow (e.g. like M95040 from ST that has 512 Byte size 27115683Sobrien * but uses only one address byte (A0 to A7) for addressing.) For 28115683Sobrien * the extra address bit (A8, A16 or A24) bit 3 of the instruction byte 29115683Sobrien * is used. This instruction bit is normally defined as don't care for 302056Swollman * other AT25 like chips. 312056Swollman */ 32131952Smarcel#define EE_INSTR_BIT3_IS_ADDR 0x0010 3375357Sjhb 3478426Sjhb void *context; 35974Sdg}; 3630789Sbde 3779573Sbsd#endif /* __LINUX_SPI_EEPROM_H */ 38103680Sjhb