11558Srgrimes/* SPDX-License-Identifier: GPL-2.0 */ 21558Srgrimes/* 31558Srgrimes * Copyright (c) 2017 MediaTek Inc. 41558Srgrimes * Author: Yong Wu <yong.wu@mediatek.com> 51558Srgrimes */ 61558Srgrimes#ifndef _DT_BINDINGS_MEMORY_MT2712_LARB_PORT_H_ 71558Srgrimes#define _DT_BINDINGS_MEMORY_MT2712_LARB_PORT_H_ 81558Srgrimes 91558Srgrimes#include <dt-bindings/memory/mtk-memory-port.h> 101558Srgrimes 111558Srgrimes#define M4U_LARB0_ID 0 121558Srgrimes#define M4U_LARB1_ID 1 131558Srgrimes#define M4U_LARB2_ID 2 141558Srgrimes#define M4U_LARB3_ID 3 151558Srgrimes#define M4U_LARB4_ID 4 161558Srgrimes#define M4U_LARB5_ID 5 171558Srgrimes#define M4U_LARB6_ID 6 181558Srgrimes#define M4U_LARB7_ID 7 191558Srgrimes#define M4U_LARB8_ID 8 201558Srgrimes#define M4U_LARB9_ID 9 211558Srgrimes 221558Srgrimes/* larb0 */ 231558Srgrimes#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) 241558Srgrimes#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1) 251558Srgrimes#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2) 261558Srgrimes#define M4U_PORT_DISP_OD_R MTK_M4U_ID(M4U_LARB0_ID, 3) 271558Srgrimes#define M4U_PORT_DISP_OD_W MTK_M4U_ID(M4U_LARB0_ID, 4) 281558Srgrimes#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5) 291558Srgrimes#define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 6) 301558Srgrimes#define M4U_PORT_DISP_RDMA2 MTK_M4U_ID(M4U_LARB0_ID, 7) 311558Srgrimes 321558Srgrimes/* larb1 */ 331558Srgrimes#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB1_ID, 0) 3437663Scharnier#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB1_ID, 1) 351558Srgrimes#define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB1_ID, 2) 361558Srgrimes#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB1_ID, 3) 372999Swollman#define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB1_ID, 4) 381558Srgrimes#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB1_ID, 5) 39105267Scharnier#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB1_ID, 6) 401558Srgrimes#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB1_ID, 7) 4137663Scharnier#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB1_ID, 8) 42105267Scharnier#define M4U_PORT_HW_VDEC_TILE MTK_M4U_ID(M4U_LARB1_ID, 9) 4337663Scharnier#define M4U_PORT_HW_IMG_RESZ_EXT MTK_M4U_ID(M4U_LARB1_ID, 10) 441558Srgrimes 45105267Scharnier/* larb2 */ 46105267Scharnier#define M4U_PORT_CAM_DMA0 MTK_M4U_ID(M4U_LARB2_ID, 0) 47105267Scharnier#define M4U_PORT_CAM_DMA1 MTK_M4U_ID(M4U_LARB2_ID, 1) 481558Srgrimes#define M4U_PORT_CAM_DMA2 MTK_M4U_ID(M4U_LARB2_ID, 2) 49192934Srmacklem 50192934Srmacklem/* larb3 */ 51192934Srmacklem#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0) 521558Srgrimes#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1) 531558Srgrimes#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2) 54192934Srmacklem#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3) 551558Srgrimes#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4) 561558Srgrimes#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 5) 571558Srgrimes#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 6) 58109363Smbr#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 7) 591558Srgrimes#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 8) 6074462Salfred 6174462Salfred/* larb4 */ 621558Srgrimes#define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB4_ID, 0) 639336Sdfr#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 1) 64192934Srmacklem#define M4U_PORT_DISP_WDMA1 MTK_M4U_ID(M4U_LARB4_ID, 2) 6583653Speter#define M4U_PORT_DISP_OD1_R MTK_M4U_ID(M4U_LARB4_ID, 3) 661558Srgrimes#define M4U_PORT_DISP_OD1_W MTK_M4U_ID(M4U_LARB4_ID, 4) 67192934Srmacklem#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 5) 68192934Srmacklem#define M4U_PORT_MDP_WROT1 MTK_M4U_ID(M4U_LARB4_ID, 6) 691558Srgrimes 701558Srgrimes/* larb5 */ 711558Srgrimes#define M4U_PORT_DISP_OVL2 MTK_M4U_ID(M4U_LARB5_ID, 0) 7237663Scharnier#define M4U_PORT_DISP_WDMA2 MTK_M4U_ID(M4U_LARB5_ID, 1) 731558Srgrimes#define M4U_PORT_MDP_RDMA2 MTK_M4U_ID(M4U_LARB5_ID, 2) 741558Srgrimes#define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB5_ID, 3) 75149433Spjd 76103949Smike/* larb6 */ 771558Srgrimes#define M4U_PORT_JPGDEC_WDMA_0 MTK_M4U_ID(M4U_LARB6_ID, 0) 781558Srgrimes#define M4U_PORT_JPGDEC_WDMA_1 MTK_M4U_ID(M4U_LARB6_ID, 1) 791558Srgrimes#define M4U_PORT_JPGDEC_BSDMA_0 MTK_M4U_ID(M4U_LARB6_ID, 2) 801558Srgrimes#define M4U_PORT_JPGDEC_BSDMA_1 MTK_M4U_ID(M4U_LARB6_ID, 3) 811558Srgrimes 821558Srgrimes/* larb7 */ 831558Srgrimes#define M4U_PORT_MDP_RDMA3 MTK_M4U_ID(M4U_LARB7_ID, 0) 841558Srgrimes#define M4U_PORT_MDP_WROT2 MTK_M4U_ID(M4U_LARB7_ID, 1) 85158857Srodrigc 861558Srgrimes/* larb8 */ 871558Srgrimes#define M4U_PORT_VDO MTK_M4U_ID(M4U_LARB8_ID, 0) 881558Srgrimes#define M4U_PORT_NR MTK_M4U_ID(M4U_LARB8_ID, 1) 891558Srgrimes#define M4U_PORT_WR_CHANNEL0 MTK_M4U_ID(M4U_LARB8_ID, 2) 901558Srgrimes 911558Srgrimes/* larb9 */ 921558Srgrimes#define M4U_PORT_TVD MTK_M4U_ID(M4U_LARB9_ID, 0) 931558Srgrimes#define M4U_PORT_WR_CHANNEL1 MTK_M4U_ID(M4U_LARB9_ID, 1) 941558Srgrimes 951558Srgrimes#endif 961558Srgrimes