1184902Srwatson// SPDX-License-Identifier: GPL-2.0-only 2191273Srwatson/* 3184902Srwatson * Driver for Atmel AT32 and AT91 SPI Controllers 4184902Srwatson * 5184902Srwatson * Copyright (C) 2006 Atmel Corporation 6184902Srwatson */ 7184902Srwatson 8184902Srwatson#include <linux/kernel.h> 9184902Srwatson#include <linux/clk.h> 10184902Srwatson#include <linux/module.h> 11184902Srwatson#include <linux/platform_device.h> 12184902Srwatson#include <linux/delay.h> 13184902Srwatson#include <linux/dma-mapping.h> 14184902Srwatson#include <linux/dmaengine.h> 15184902Srwatson#include <linux/err.h> 16184902Srwatson#include <linux/interrupt.h> 17184902Srwatson#include <linux/spi/spi.h> 18184902Srwatson#include <linux/slab.h> 19184902Srwatson#include <linux/of.h> 20184902Srwatson 21184902Srwatson#include <linux/io.h> 22184902Srwatson#include <linux/gpio/consumer.h> 23184902Srwatson#include <linux/pinctrl/consumer.h> 24184902Srwatson#include <linux/pm_runtime.h> 25184902Srwatson#include <linux/iopoll.h> 26184902Srwatson#include <trace/events/spi.h> 27184902Srwatson 28184902Srwatson/* SPI register offsets */ 29244265Srwatson#define SPI_CR 0x0000 30184902Srwatson#define SPI_MR 0x0004 31184902Srwatson#define SPI_RDR 0x0008 32184902Srwatson#define SPI_TDR 0x000c 33184902Srwatson#define SPI_SR 0x0010 34184902Srwatson#define SPI_IER 0x0014 35184902Srwatson#define SPI_IDR 0x0018 36191273Srwatson#define SPI_IMR 0x001c 37191273Srwatson#define SPI_CSR0 0x0030 38191273Srwatson#define SPI_CSR1 0x0034 39191273Srwatson#define SPI_CSR2 0x0038 40191273Srwatson#define SPI_CSR3 0x003c 41191273Srwatson#define SPI_FMR 0x0040 42184902Srwatson#define SPI_FLR 0x0044 43184902Srwatson#define SPI_VERSION 0x00fc 44184902Srwatson#define SPI_RPR 0x0100 45184902Srwatson#define SPI_RCR 0x0104 46184902Srwatson#define SPI_TPR 0x0108 47184902Srwatson#define SPI_TCR 0x010c 48184902Srwatson#define SPI_RNPR 0x0110 49184902Srwatson#define SPI_RNCR 0x0114 50184902Srwatson#define SPI_TNPR 0x0118 51184902Srwatson#define SPI_TNCR 0x011c 52184902Srwatson#define SPI_PTCR 0x0120 53184902Srwatson#define SPI_PTSR 0x0124 54184902Srwatson 55184902Srwatson/* Bitfields in CR */ 56184902Srwatson#define SPI_SPIEN_OFFSET 0 57184902Srwatson#define SPI_SPIEN_SIZE 1 58184902Srwatson#define SPI_SPIDIS_OFFSET 1 59184902Srwatson#define SPI_SPIDIS_SIZE 1 60184902Srwatson#define SPI_SWRST_OFFSET 7 61184902Srwatson#define SPI_SWRST_SIZE 1 62184902Srwatson#define SPI_LASTXFER_OFFSET 24 63184902Srwatson#define SPI_LASTXFER_SIZE 1 64184902Srwatson#define SPI_TXFCLR_OFFSET 16 65184902Srwatson#define SPI_TXFCLR_SIZE 1 66184902Srwatson#define SPI_RXFCLR_OFFSET 17 67184902Srwatson#define SPI_RXFCLR_SIZE 1 68184902Srwatson#define SPI_FIFOEN_OFFSET 30 69184902Srwatson#define SPI_FIFOEN_SIZE 1 70184902Srwatson#define SPI_FIFODIS_OFFSET 31 71184902Srwatson#define SPI_FIFODIS_SIZE 1 72184902Srwatson 73184902Srwatson/* Bitfields in MR */ 74184902Srwatson#define SPI_MSTR_OFFSET 0 75184902Srwatson#define SPI_MSTR_SIZE 1 76184902Srwatson#define SPI_PS_OFFSET 1 77184902Srwatson#define SPI_PS_SIZE 1 78184902Srwatson#define SPI_PCSDEC_OFFSET 2 79184902Srwatson#define SPI_PCSDEC_SIZE 1 80184902Srwatson#define SPI_FDIV_OFFSET 3 81184902Srwatson#define SPI_FDIV_SIZE 1 82184902Srwatson#define SPI_MODFDIS_OFFSET 4 83184902Srwatson#define SPI_MODFDIS_SIZE 1 84184902Srwatson#define SPI_WDRBT_OFFSET 5 85184902Srwatson#define SPI_WDRBT_SIZE 1 86184902Srwatson#define SPI_LLB_OFFSET 7 87184902Srwatson#define SPI_LLB_SIZE 1 88184902Srwatson#define SPI_PCS_OFFSET 16 89184902Srwatson#define SPI_PCS_SIZE 4 90184902Srwatson#define SPI_DLYBCS_OFFSET 24 91184902Srwatson#define SPI_DLYBCS_SIZE 8 92184902Srwatson 93184902Srwatson/* Bitfields in RDR */ 94184902Srwatson#define SPI_RD_OFFSET 0 95184902Srwatson#define SPI_RD_SIZE 16 96184902Srwatson 97184902Srwatson/* Bitfields in TDR */ 98184902Srwatson#define SPI_TD_OFFSET 0 99184902Srwatson#define SPI_TD_SIZE 16 100184902Srwatson 101184902Srwatson/* Bitfields in SR */ 102184902Srwatson#define SPI_RDRF_OFFSET 0 103184902Srwatson#define SPI_RDRF_SIZE 1 104184902Srwatson#define SPI_TDRE_OFFSET 1 105184902Srwatson#define SPI_TDRE_SIZE 1 106184902Srwatson#define SPI_MODF_OFFSET 2 107184902Srwatson#define SPI_MODF_SIZE 1 108184902Srwatson#define SPI_OVRES_OFFSET 3 109184902Srwatson#define SPI_OVRES_SIZE 1 110184902Srwatson#define SPI_ENDRX_OFFSET 4 111184902Srwatson#define SPI_ENDRX_SIZE 1 112184902Srwatson#define SPI_ENDTX_OFFSET 5 113184902Srwatson#define SPI_ENDTX_SIZE 1 114184902Srwatson#define SPI_RXBUFF_OFFSET 6 115184902Srwatson#define SPI_RXBUFF_SIZE 1 116184902Srwatson#define SPI_TXBUFE_OFFSET 7 117184902Srwatson#define SPI_TXBUFE_SIZE 1 118184902Srwatson#define SPI_NSSR_OFFSET 8 119184902Srwatson#define SPI_NSSR_SIZE 1 120184902Srwatson#define SPI_TXEMPTY_OFFSET 9 121184902Srwatson#define SPI_TXEMPTY_SIZE 1 122184902Srwatson#define SPI_SPIENS_OFFSET 16 123184902Srwatson#define SPI_SPIENS_SIZE 1 124184902Srwatson#define SPI_TXFEF_OFFSET 24 125184902Srwatson#define SPI_TXFEF_SIZE 1 126184902Srwatson#define SPI_TXFFF_OFFSET 25 127184902Srwatson#define SPI_TXFFF_SIZE 1 128184902Srwatson#define SPI_TXFTHF_OFFSET 26 129184902Srwatson#define SPI_TXFTHF_SIZE 1 130184902Srwatson#define SPI_RXFEF_OFFSET 27 131184902Srwatson#define SPI_RXFEF_SIZE 1 132184902Srwatson#define SPI_RXFFF_OFFSET 28 133184902Srwatson#define SPI_RXFFF_SIZE 1 134184902Srwatson#define SPI_RXFTHF_OFFSET 29 135184902Srwatson#define SPI_RXFTHF_SIZE 1 136184902Srwatson#define SPI_TXFPTEF_OFFSET 30 137184902Srwatson#define SPI_TXFPTEF_SIZE 1 138184902Srwatson#define SPI_RXFPTEF_OFFSET 31 139184902Srwatson#define SPI_RXFPTEF_SIZE 1 140184902Srwatson 141184902Srwatson/* Bitfields in CSR0 */ 142184902Srwatson#define SPI_CPOL_OFFSET 0 143184902Srwatson#define SPI_CPOL_SIZE 1 144184902Srwatson#define SPI_NCPHA_OFFSET 1 145184902Srwatson#define SPI_NCPHA_SIZE 1 146184902Srwatson#define SPI_CSAAT_OFFSET 3 147184902Srwatson#define SPI_CSAAT_SIZE 1 148184902Srwatson#define SPI_BITS_OFFSET 4 149184902Srwatson#define SPI_BITS_SIZE 4 150184902Srwatson#define SPI_SCBR_OFFSET 8 151184902Srwatson#define SPI_SCBR_SIZE 8 152184902Srwatson#define SPI_DLYBS_OFFSET 16 153184902Srwatson#define SPI_DLYBS_SIZE 8 154184902Srwatson#define SPI_DLYBCT_OFFSET 24 155184902Srwatson#define SPI_DLYBCT_SIZE 8 156184902Srwatson 157184902Srwatson/* Bitfields in RCR */ 158184902Srwatson#define SPI_RXCTR_OFFSET 0 159184902Srwatson#define SPI_RXCTR_SIZE 16 160184902Srwatson 161184902Srwatson/* Bitfields in TCR */ 162184902Srwatson#define SPI_TXCTR_OFFSET 0 163184902Srwatson#define SPI_TXCTR_SIZE 16 164184902Srwatson 165184902Srwatson/* Bitfields in RNCR */ 166184902Srwatson#define SPI_RXNCR_OFFSET 0 167184902Srwatson#define SPI_RXNCR_SIZE 16 168184902Srwatson 169184902Srwatson/* Bitfields in TNCR */ 170184902Srwatson#define SPI_TXNCR_OFFSET 0 171184902Srwatson#define SPI_TXNCR_SIZE 16 172184902Srwatson 173184902Srwatson/* Bitfields in PTCR */ 174184902Srwatson#define SPI_RXTEN_OFFSET 0 175184902Srwatson#define SPI_RXTEN_SIZE 1 176184902Srwatson#define SPI_RXTDIS_OFFSET 1 177184902Srwatson#define SPI_RXTDIS_SIZE 1 178184902Srwatson#define SPI_TXTEN_OFFSET 8 179184902Srwatson#define SPI_TXTEN_SIZE 1 180184902Srwatson#define SPI_TXTDIS_OFFSET 9 181184902Srwatson#define SPI_TXTDIS_SIZE 1 182184902Srwatson 183184902Srwatson/* Bitfields in FMR */ 184184902Srwatson#define SPI_TXRDYM_OFFSET 0 185184902Srwatson#define SPI_TXRDYM_SIZE 2 186184902Srwatson#define SPI_RXRDYM_OFFSET 4 187184902Srwatson#define SPI_RXRDYM_SIZE 2 188184902Srwatson#define SPI_TXFTHRES_OFFSET 16 189184902Srwatson#define SPI_TXFTHRES_SIZE 6 190184902Srwatson#define SPI_RXFTHRES_OFFSET 24 191184902Srwatson#define SPI_RXFTHRES_SIZE 6 192184902Srwatson 193184902Srwatson/* Bitfields in FLR */ 194184902Srwatson#define SPI_TXFL_OFFSET 0 195184902Srwatson#define SPI_TXFL_SIZE 6 196184902Srwatson#define SPI_RXFL_OFFSET 16 197184902Srwatson#define SPI_RXFL_SIZE 6 198184902Srwatson 199184902Srwatson/* Constants for BITS */ 200184902Srwatson#define SPI_BITS_8_BPT 0 201184902Srwatson#define SPI_BITS_9_BPT 1 202184902Srwatson#define SPI_BITS_10_BPT 2 203184902Srwatson#define SPI_BITS_11_BPT 3 204184902Srwatson#define SPI_BITS_12_BPT 4 205184902Srwatson#define SPI_BITS_13_BPT 5 206184902Srwatson#define SPI_BITS_14_BPT 6 207184902Srwatson#define SPI_BITS_15_BPT 7 208184902Srwatson#define SPI_BITS_16_BPT 8 209184902Srwatson#define SPI_ONE_DATA 0 210184902Srwatson#define SPI_TWO_DATA 1 211184902Srwatson#define SPI_FOUR_DATA 2 212184902Srwatson 213184902Srwatson/* Bit manipulation macros */ 214184902Srwatson#define SPI_BIT(name) \ 215184902Srwatson (1 << SPI_##name##_OFFSET) 216184902Srwatson#define SPI_BF(name, value) \ 217184902Srwatson (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET) 218184902Srwatson#define SPI_BFEXT(name, value) \ 219184902Srwatson (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1)) 220184902Srwatson#define SPI_BFINS(name, value, old) \ 221184902Srwatson (((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \ 222184902Srwatson | SPI_BF(name, value)) 223184902Srwatson 224184902Srwatson/* Register access macros */ 225184902Srwatson#define spi_readl(port, reg) \ 226184902Srwatson readl_relaxed((port)->regs + SPI_##reg) 227184902Srwatson#define spi_writel(port, reg, value) \ 228184902Srwatson writel_relaxed((value), (port)->regs + SPI_##reg) 229184902Srwatson#define spi_writew(port, reg, value) \ 230184902Srwatson writew_relaxed((value), (port)->regs + SPI_##reg) 231184902Srwatson 232184902Srwatson/* use PIO for small transfers, avoiding DMA setup/teardown overhead and 233184902Srwatson * cache operations; better heuristics consider wordsize and bitrate. 234184902Srwatson */ 235184902Srwatson#define DMA_MIN_BYTES 16 236184902Srwatson 237184902Srwatson#define AUTOSUSPEND_TIMEOUT 2000 238184902Srwatson 239184902Srwatsonstruct atmel_spi_caps { 240184902Srwatson bool is_spi2; 241184902Srwatson bool has_wdrbt; 242184902Srwatson bool has_dma_support; 243184902Srwatson bool has_pdc_support; 244184902Srwatson}; 245184902Srwatson 246184902Srwatson/* 247184902Srwatson * The core SPI transfer engine just talks to a register bank to set up 248184902Srwatson * DMA transfers; transfer queue progress is driven by IRQs. The clock 249184902Srwatson * framework provides the base clock, subdivided for each spi_device. 250184902Srwatson */ 251184902Srwatsonstruct atmel_spi { 252184902Srwatson spinlock_t lock; 253184902Srwatson unsigned long flags; 254184902Srwatson 255184902Srwatson phys_addr_t phybase; 256184902Srwatson void __iomem *regs; 257184902Srwatson int irq; 258184902Srwatson struct clk *clk; 259184902Srwatson struct platform_device *pdev; 260184902Srwatson unsigned long spi_clk; 261184902Srwatson 262184902Srwatson struct spi_transfer *current_transfer; 263184902Srwatson int current_remaining_bytes; 264184902Srwatson int done_status; 265184902Srwatson dma_addr_t dma_addr_rx_bbuf; 266184902Srwatson dma_addr_t dma_addr_tx_bbuf; 267184902Srwatson void *addr_rx_bbuf; 268184902Srwatson void *addr_tx_bbuf; 269184902Srwatson 270184902Srwatson struct completion xfer_completion; 271184902Srwatson 272184902Srwatson struct atmel_spi_caps caps; 273184902Srwatson 274184902Srwatson bool use_dma; 275184902Srwatson bool use_pdc; 276184902Srwatson 277184902Srwatson bool keep_cs; 278184902Srwatson 279184902Srwatson u32 fifo_size; 280184902Srwatson bool last_polarity; 281184902Srwatson u8 native_cs_free; 282184902Srwatson u8 native_cs_for_gpio; 283184902Srwatson}; 284184902Srwatson 285184902Srwatson/* Controller-specific per-slave state */ 286184902Srwatsonstruct atmel_spi_device { 287184902Srwatson u32 csr; 288184902Srwatson}; 289184902Srwatson 290184902Srwatson#define SPI_MAX_DMA_XFER 65535 /* true for both PDC and DMA */ 291184902Srwatson#define INVALID_DMA_ADDRESS 0xffffffff 292184902Srwatson 293184902Srwatson/* 294184902Srwatson * This frequency can be anything supported by the controller, but to avoid 295184902Srwatson * unnecessary delay, the highest possible frequency is chosen. 296184902Srwatson * 297184902Srwatson * This frequency is the highest possible which is not interfering with other 298184902Srwatson * chip select registers (see Note for Serial Clock Bit Rate configuration in 299184902Srwatson * Atmel-11121F-ATARM-SAMA5D3-Series-Datasheet_02-Feb-16, page 1283) 300184902Srwatson */ 301184902Srwatson#define DUMMY_MSG_FREQUENCY 0x02 302184902Srwatson/* 303184902Srwatson * 8 bits is the minimum data the controller is capable of sending. 304184902Srwatson * 305184902Srwatson * This message can be anything as it should not be treated by any SPI device. 306184902Srwatson */ 307184902Srwatson#define DUMMY_MSG 0xAA 308184902Srwatson 309184902Srwatson/* 310184902Srwatson * Version 2 of the SPI controller has 311184902Srwatson * - CR.LASTXFER 312184902Srwatson * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero) 313184902Srwatson * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs) 314184902Srwatson * - SPI_CSRx.CSAAT 315184902Srwatson * - SPI_CSRx.SBCR allows faster clocking 316184902Srwatson */ 317184902Srwatsonstatic bool atmel_spi_is_v2(struct atmel_spi *as) 318184902Srwatson{ 319184902Srwatson return as->caps.is_spi2; 320184902Srwatson} 321184902Srwatson 322184902Srwatson/* 323184902Srwatson * Send a dummy message. 324184902Srwatson * 325184902Srwatson * This is sometimes needed when using a CS GPIO to force clock transition when 326184902Srwatson * switching between devices with different polarities. 327184902Srwatson */ 328184902Srwatsonstatic void atmel_spi_send_dummy(struct atmel_spi *as, struct spi_device *spi, int chip_select) 329184902Srwatson{ 330184902Srwatson u32 status; 331184902Srwatson u32 csr; 332184902Srwatson 333184902Srwatson /* 334184902Srwatson * Set a clock frequency to allow sending message on SPI bus. 335184902Srwatson * The frequency here can be anything, but is needed for 336184902Srwatson * the controller to send the data. 337184902Srwatson */ 338184902Srwatson csr = spi_readl(as, CSR0 + 4 * chip_select); 339184902Srwatson csr = SPI_BFINS(SCBR, DUMMY_MSG_FREQUENCY, csr); 340184902Srwatson spi_writel(as, CSR0 + 4 * chip_select, csr); 341184902Srwatson 342184902Srwatson /* 343184902Srwatson * Read all data coming from SPI bus, needed to be able to send 344184902Srwatson * the message. 345184902Srwatson */ 346184902Srwatson spi_readl(as, RDR); 347184902Srwatson while (spi_readl(as, SR) & SPI_BIT(RDRF)) { 348184902Srwatson spi_readl(as, RDR); 349184902Srwatson cpu_relax(); 350184902Srwatson } 351184902Srwatson 352184902Srwatson spi_writel(as, TDR, DUMMY_MSG); 353184902Srwatson 354184902Srwatson readl_poll_timeout_atomic(as->regs + SPI_SR, status, 355184902Srwatson (status & SPI_BIT(TXEMPTY)), 1, 1000); 356184902Srwatson} 357184902Srwatson 358184902Srwatson 359184902Srwatson/* 360184902Srwatson * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby 361184902Srwatson * they assume that spi slave device state will not change on deselect, so 362184902Srwatson * that automagic deselection is OK. ("NPCSx rises if no data is to be 363184902Srwatson * transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer 364184902Srwatson * controllers have CSAAT and friends. 365184902Srwatson * 366184902Srwatson * Even controller newer than ar91rm9200, using GPIOs can make sens as 367184902Srwatson * it lets us support active-high chipselects despite the controller's 368184902Srwatson * belief that only active-low devices/systems exists. 369184902Srwatson * 370184902Srwatson * However, at91rm9200 has a second erratum whereby nCS0 doesn't work 371184902Srwatson * right when driven with GPIO. ("Mode Fault does not allow more than one 372184902Srwatson * Master on Chip Select 0.") No workaround exists for that ... so for 373184902Srwatson * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH, 374184902Srwatson * and (c) will trigger that first erratum in some cases. 375184902Srwatson * 376184902Srwatson * When changing the clock polarity, the SPI controller waits for the next 377184902Srwatson * transmission to enforce the default clock state. This may be an issue when 378184902Srwatson * using a GPIO as Chip Select: the clock level is applied only when the first 379184902Srwatson * packet is sent, once the CS has already been asserted. The workaround is to 380184902Srwatson * avoid this by sending a first (dummy) message before toggling the CS state. 381184902Srwatson */ 382184902Srwatsonstatic void cs_activate(struct atmel_spi *as, struct spi_device *spi) 383184902Srwatson{ 384184902Srwatson struct atmel_spi_device *asd = spi->controller_state; 385184902Srwatson bool new_polarity; 386184902Srwatson int chip_select; 387184902Srwatson u32 mr; 388184902Srwatson 389184902Srwatson if (spi_get_csgpiod(spi, 0)) 390184902Srwatson chip_select = as->native_cs_for_gpio; 391184902Srwatson else 392184902Srwatson chip_select = spi_get_chipselect(spi, 0); 393184902Srwatson 394184902Srwatson if (atmel_spi_is_v2(as)) { 395184902Srwatson spi_writel(as, CSR0 + 4 * chip_select, asd->csr); 396184902Srwatson /* For the low SPI version, there is a issue that PDC transfer 397184902Srwatson * on CS1,2,3 needs SPI_CSR0.BITS config as SPI_CSR1,2,3.BITS 398184902Srwatson */ 399184902Srwatson spi_writel(as, CSR0, asd->csr); 400184902Srwatson if (as->caps.has_wdrbt) { 401184902Srwatson spi_writel(as, MR, 402184902Srwatson SPI_BF(PCS, ~(0x01 << chip_select)) 403184902Srwatson | SPI_BIT(WDRBT) 404184902Srwatson | SPI_BIT(MODFDIS) 405184902Srwatson | SPI_BIT(MSTR)); 406184902Srwatson } else { 407184902Srwatson spi_writel(as, MR, 408184902Srwatson SPI_BF(PCS, ~(0x01 << chip_select)) 409184902Srwatson | SPI_BIT(MODFDIS) 410184902Srwatson | SPI_BIT(MSTR)); 411184902Srwatson } 412184902Srwatson 413184902Srwatson mr = spi_readl(as, MR); 414184902Srwatson 415184902Srwatson /* 416184902Srwatson * Ensures the clock polarity is valid before we actually 417184902Srwatson * assert the CS to avoid spurious clock edges to be 418184902Srwatson * processed by the spi devices. 419184902Srwatson */ 420184902Srwatson if (spi_get_csgpiod(spi, 0)) { 421184902Srwatson new_polarity = (asd->csr & SPI_BIT(CPOL)) != 0; 422184902Srwatson if (new_polarity != as->last_polarity) { 423184902Srwatson /* 424184902Srwatson * Need to disable the GPIO before sending the dummy 425184902Srwatson * message because it is already set by the spi core. 426184902Srwatson */ 427184902Srwatson gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), 0); 428184902Srwatson atmel_spi_send_dummy(as, spi, chip_select); 429184902Srwatson as->last_polarity = new_polarity; 430184902Srwatson gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), 1); 431184902Srwatson } 432184902Srwatson } 433184902Srwatson } else { 434184902Srwatson u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0; 435184902Srwatson int i; 436184902Srwatson u32 csr; 437184902Srwatson 438184902Srwatson /* Make sure clock polarity is correct */ 439184902Srwatson for (i = 0; i < spi->controller->num_chipselect; i++) { 440184902Srwatson csr = spi_readl(as, CSR0 + 4 * i); 441184902Srwatson if ((csr ^ cpol) & SPI_BIT(CPOL)) 442184902Srwatson spi_writel(as, CSR0 + 4 * i, 443184902Srwatson csr ^ SPI_BIT(CPOL)); 444184902Srwatson } 445184902Srwatson 446184902Srwatson mr = spi_readl(as, MR); 447184902Srwatson mr = SPI_BFINS(PCS, ~(1 << chip_select), mr); 448184902Srwatson spi_writel(as, MR, mr); 449184902Srwatson } 450184902Srwatson 451184902Srwatson dev_dbg(&spi->dev, "activate NPCS, mr %08x\n", mr); 452184902Srwatson} 453184902Srwatson 454184902Srwatsonstatic void cs_deactivate(struct atmel_spi *as, struct spi_device *spi) 455184902Srwatson{ 456184902Srwatson int chip_select; 457184902Srwatson u32 mr; 458184902Srwatson 459184902Srwatson if (spi_get_csgpiod(spi, 0)) 460184902Srwatson chip_select = as->native_cs_for_gpio; 461184902Srwatson else 462184902Srwatson chip_select = spi_get_chipselect(spi, 0); 463184902Srwatson 464184902Srwatson /* only deactivate *this* device; sometimes transfers to 465184902Srwatson * another device may be active when this routine is called. 466184902Srwatson */ 467184902Srwatson mr = spi_readl(as, MR); 468184902Srwatson if (~SPI_BFEXT(PCS, mr) & (1 << chip_select)) { 469184902Srwatson mr = SPI_BFINS(PCS, 0xf, mr); 470184902Srwatson spi_writel(as, MR, mr); 471184902Srwatson } 472184902Srwatson 473184902Srwatson dev_dbg(&spi->dev, "DEactivate NPCS, mr %08x\n", mr); 474184902Srwatson 475184902Srwatson if (!spi_get_csgpiod(spi, 0)) 476184902Srwatson spi_writel(as, CR, SPI_BIT(LASTXFER)); 477184902Srwatson} 478184902Srwatson 479184902Srwatsonstatic void atmel_spi_lock(struct atmel_spi *as) __acquires(&as->lock) 480184902Srwatson{ 481184902Srwatson spin_lock_irqsave(&as->lock, as->flags); 482184902Srwatson} 483184902Srwatson 484184902Srwatsonstatic void atmel_spi_unlock(struct atmel_spi *as) __releases(&as->lock) 485184902Srwatson{ 486184902Srwatson spin_unlock_irqrestore(&as->lock, as->flags); 487184902Srwatson} 488184902Srwatson 489184902Srwatsonstatic inline bool atmel_spi_is_vmalloc_xfer(struct spi_transfer *xfer) 490184902Srwatson{ 491184902Srwatson return is_vmalloc_addr(xfer->tx_buf) || is_vmalloc_addr(xfer->rx_buf); 492184902Srwatson} 493184902Srwatson 494184902Srwatsonstatic inline bool atmel_spi_use_dma(struct atmel_spi *as, 495184902Srwatson struct spi_transfer *xfer) 496184902Srwatson{ 497184902Srwatson return as->use_dma && xfer->len >= DMA_MIN_BYTES; 498184902Srwatson} 499184902Srwatson 500184902Srwatsonstatic bool atmel_spi_can_dma(struct spi_controller *host, 501184902Srwatson struct spi_device *spi, 502184902Srwatson struct spi_transfer *xfer) 503184902Srwatson{ 504184902Srwatson struct atmel_spi *as = spi_controller_get_devdata(host); 505184902Srwatson 506184902Srwatson if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) 507184902Srwatson return atmel_spi_use_dma(as, xfer) && 508184902Srwatson !atmel_spi_is_vmalloc_xfer(xfer); 509184902Srwatson else 510184902Srwatson return atmel_spi_use_dma(as, xfer); 511184902Srwatson 512184902Srwatson} 513184902Srwatson 514184902Srwatsonstatic int atmel_spi_dma_slave_config(struct atmel_spi *as, u8 bits_per_word) 515184902Srwatson{ 516184902Srwatson struct spi_controller *host = platform_get_drvdata(as->pdev); 517184902Srwatson struct dma_slave_config slave_config; 518184902Srwatson int err = 0; 519184902Srwatson 520184902Srwatson if (bits_per_word > 8) { 521184902Srwatson slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 522184902Srwatson slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 523184902Srwatson } else { 524184902Srwatson slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 525184902Srwatson slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 526184902Srwatson } 527184902Srwatson 528184902Srwatson slave_config.dst_addr = (dma_addr_t)as->phybase + SPI_TDR; 529184902Srwatson slave_config.src_addr = (dma_addr_t)as->phybase + SPI_RDR; 530184902Srwatson slave_config.src_maxburst = 1; 531184902Srwatson slave_config.dst_maxburst = 1; 532184902Srwatson slave_config.device_fc = false; 533184902Srwatson 534184902Srwatson /* 535184902Srwatson * This driver uses fixed peripheral select mode (PS bit set to '0' in 536184902Srwatson * the Mode Register). 537184902Srwatson * So according to the datasheet, when FIFOs are available (and 538184902Srwatson * enabled), the Transmit FIFO operates in Multiple Data Mode. 539184902Srwatson * In this mode, up to 2 data, not 4, can be written into the Transmit 540184902Srwatson * Data Register in a single access. 541184902Srwatson * However, the first data has to be written into the lowest 16 bits and 542184902Srwatson * the second data into the highest 16 bits of the Transmit 543184902Srwatson * Data Register. For 8bit data (the most frequent case), it would 544184902Srwatson * require to rework tx_buf so each data would actually fit 16 bits. 545184902Srwatson * So we'd rather write only one data at the time. Hence the transmit 546184902Srwatson * path works the same whether FIFOs are available (and enabled) or not. 547184902Srwatson */ 548184902Srwatson if (dmaengine_slave_config(host->dma_tx, &slave_config)) { 549184902Srwatson dev_err(&as->pdev->dev, 550184902Srwatson "failed to configure tx dma channel\n"); 551184902Srwatson err = -EINVAL; 552184902Srwatson } 553184902Srwatson 554184902Srwatson /* 555184902Srwatson * This driver configures the spi controller for host mode (MSTR bit 556184902Srwatson * set to '1' in the Mode Register). 557184902Srwatson * So according to the datasheet, when FIFOs are available (and 558184902Srwatson * enabled), the Receive FIFO operates in Single Data Mode. 559184902Srwatson * So the receive path works the same whether FIFOs are available (and 560184902Srwatson * enabled) or not. 561184902Srwatson */ 562184902Srwatson if (dmaengine_slave_config(host->dma_rx, &slave_config)) { 563184902Srwatson dev_err(&as->pdev->dev, 564184902Srwatson "failed to configure rx dma channel\n"); 565184902Srwatson err = -EINVAL; 566184902Srwatson } 567184902Srwatson 568186647Srwatson return err; 569184902Srwatson} 570184902Srwatson 571184902Srwatsonstatic int atmel_spi_configure_dma(struct spi_controller *host, 572184902Srwatson struct atmel_spi *as) 573184902Srwatson{ 574184902Srwatson struct device *dev = &as->pdev->dev; 575184902Srwatson int err; 576184902Srwatson 577184902Srwatson host->dma_tx = dma_request_chan(dev, "tx"); 578184902Srwatson if (IS_ERR(host->dma_tx)) { 579184902Srwatson err = PTR_ERR(host->dma_tx); 580184902Srwatson dev_dbg(dev, "No TX DMA channel, DMA is disabled\n"); 581184902Srwatson goto error_clear; 582184902Srwatson } 583184902Srwatson 584184902Srwatson host->dma_rx = dma_request_chan(dev, "rx"); 585184902Srwatson if (IS_ERR(host->dma_rx)) { 586184902Srwatson err = PTR_ERR(host->dma_rx); 587184902Srwatson /* 588184902Srwatson * No reason to check EPROBE_DEFER here since we have already 589184902Srwatson * requested tx channel. 590184902Srwatson */ 591184902Srwatson dev_dbg(dev, "No RX DMA channel, DMA is disabled\n"); 592184902Srwatson goto error; 593186647Srwatson } 594186647Srwatson 595189279Srwatson err = atmel_spi_dma_slave_config(as, 8); 596189279Srwatson if (err) 597191273Srwatson goto error; 598191273Srwatson 599195740Srwatson dev_info(&as->pdev->dev, 600243750Srwatson "Using %s (tx) and %s (rx) for DMA transfers\n", 601243750Srwatson dma_chan_name(host->dma_tx), 602243750Srwatson dma_chan_name(host->dma_rx)); 603243750Srwatson 604244265Srwatson return 0; 605184902Srwatsonerror: 606184902Srwatson if (!IS_ERR(host->dma_rx)) 607184902Srwatson dma_release_channel(host->dma_rx); 608184902Srwatson if (!IS_ERR(host->dma_tx)) 609184902Srwatson dma_release_channel(host->dma_tx); 610184902Srwatsonerror_clear: 611184902Srwatson host->dma_tx = host->dma_rx = NULL; 612184902Srwatson return err; 613184902Srwatson} 614184902Srwatson 615184902Srwatsonstatic void atmel_spi_stop_dma(struct spi_controller *host) 616184902Srwatson{ 617184902Srwatson if (host->dma_rx) 618184902Srwatson dmaengine_terminate_all(host->dma_rx); 619184902Srwatson if (host->dma_tx) 620184902Srwatson dmaengine_terminate_all(host->dma_tx); 621184902Srwatson} 622184902Srwatson 623184902Srwatsonstatic void atmel_spi_release_dma(struct spi_controller *host) 624184902Srwatson{ 625184902Srwatson if (host->dma_rx) { 626184902Srwatson dma_release_channel(host->dma_rx); 627184902Srwatson host->dma_rx = NULL; 628184902Srwatson } 629184902Srwatson if (host->dma_tx) { 630184902Srwatson dma_release_channel(host->dma_tx); 631184902Srwatson host->dma_tx = NULL; 632184902Srwatson } 633184902Srwatson} 634184902Srwatson 635184902Srwatson/* This function is called by the DMA driver from tasklet context */ 636184902Srwatsonstatic void dma_callback(void *data) 637184902Srwatson{ 638184902Srwatson struct spi_controller *host = data; 639184902Srwatson struct atmel_spi *as = spi_controller_get_devdata(host); 640184902Srwatson 641184902Srwatson if (is_vmalloc_addr(as->current_transfer->rx_buf) && 642184902Srwatson IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) { 643184902Srwatson memcpy(as->current_transfer->rx_buf, as->addr_rx_bbuf, 644184902Srwatson as->current_transfer->len); 645184902Srwatson } 646184902Srwatson complete(&as->xfer_completion); 647184902Srwatson} 648184902Srwatson 649184902Srwatson/* 650184902Srwatson * Next transfer using PIO without FIFO. 651184902Srwatson */ 652184902Srwatsonstatic void atmel_spi_next_xfer_single(struct spi_controller *host, 653184902Srwatson struct spi_transfer *xfer) 654184902Srwatson{ 655184902Srwatson struct atmel_spi *as = spi_controller_get_devdata(host); 656184902Srwatson unsigned long xfer_pos = xfer->len - as->current_remaining_bytes; 657184902Srwatson 658184902Srwatson dev_vdbg(host->dev.parent, "atmel_spi_next_xfer_pio\n"); 659184902Srwatson 660184902Srwatson /* Make sure data is not remaining in RDR */ 661184902Srwatson spi_readl(as, RDR); 662184902Srwatson while (spi_readl(as, SR) & SPI_BIT(RDRF)) { 663184902Srwatson spi_readl(as, RDR); 664184902Srwatson cpu_relax(); 665184902Srwatson } 666184902Srwatson 667184902Srwatson if (xfer->bits_per_word > 8) 668184902Srwatson spi_writel(as, TDR, *(u16 *)(xfer->tx_buf + xfer_pos)); 669184902Srwatson else 670184902Srwatson spi_writel(as, TDR, *(u8 *)(xfer->tx_buf + xfer_pos)); 671184902Srwatson 672184902Srwatson dev_dbg(host->dev.parent, 673184902Srwatson " start pio xfer %p: len %u tx %p rx %p bitpw %d\n", 674184902Srwatson xfer, xfer->len, xfer->tx_buf, xfer->rx_buf, 675184902Srwatson xfer->bits_per_word); 676186647Srwatson 677186647Srwatson /* Enable relevant interrupts */ 678186647Srwatson spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES)); 679186647Srwatson} 680186647Srwatson 681186647Srwatson/* 682186647Srwatson * Next transfer using PIO with FIFO. 683186647Srwatson */ 684186647Srwatsonstatic void atmel_spi_next_xfer_fifo(struct spi_controller *host, 685186647Srwatson struct spi_transfer *xfer) 686186647Srwatson{ 687186647Srwatson struct atmel_spi *as = spi_controller_get_devdata(host); 688184902Srwatson u32 current_remaining_data, num_data; 689186647Srwatson u32 offset = xfer->len - as->current_remaining_bytes; 690186647Srwatson const u16 *words = (const u16 *)((u8 *)xfer->tx_buf + offset); 691186647Srwatson const u8 *bytes = (const u8 *)((u8 *)xfer->tx_buf + offset); 692186647Srwatson u16 td0, td1; 693186647Srwatson u32 fifomr; 694186647Srwatson 695186647Srwatson dev_vdbg(host->dev.parent, "atmel_spi_next_xfer_fifo\n"); 696186647Srwatson 697184902Srwatson /* Compute the number of data to transfer in the current iteration */ 698186647Srwatson current_remaining_data = ((xfer->bits_per_word > 8) ? 699189279Srwatson ((u32)as->current_remaining_bytes >> 1) : 700184902Srwatson (u32)as->current_remaining_bytes); 701186647Srwatson num_data = min(current_remaining_data, as->fifo_size); 702184902Srwatson 703184902Srwatson /* Flush RX and TX FIFOs */ 704184902Srwatson spi_writel(as, CR, SPI_BIT(RXFCLR) | SPI_BIT(TXFCLR)); 705186647Srwatson while (spi_readl(as, FLR)) 706184902Srwatson cpu_relax(); 707184902Srwatson 708184902Srwatson /* Set RX FIFO Threshold to the number of data to transfer */ 709184902Srwatson fifomr = spi_readl(as, FMR); 710184902Srwatson spi_writel(as, FMR, SPI_BFINS(RXFTHRES, num_data, fifomr)); 711184902Srwatson 712184902Srwatson /* Clear FIFO flags in the Status Register, especially RXFTHF */ 713184902Srwatson (void)spi_readl(as, SR); 714184902Srwatson 715184902Srwatson /* Fill TX FIFO */ 716184902Srwatson while (num_data >= 2) { 717184902Srwatson if (xfer->bits_per_word > 8) { 718186647Srwatson td0 = *words++; 719184902Srwatson td1 = *words++; 720184902Srwatson } else { 721184902Srwatson td0 = *bytes++; 722186647Srwatson td1 = *bytes++; 723184902Srwatson } 724184902Srwatson 725186647Srwatson spi_writel(as, TDR, (td1 << 16) | td0); 726186647Srwatson num_data -= 2; 727186647Srwatson } 728186647Srwatson 729186647Srwatson if (num_data) { 730184902Srwatson if (xfer->bits_per_word > 8) 731186647Srwatson td0 = *words++; 732186647Srwatson else 733184902Srwatson td0 = *bytes++; 734186647Srwatson 735189279Srwatson spi_writew(as, TDR, td0); 736184902Srwatson num_data--; 737184902Srwatson } 738184902Srwatson 739184902Srwatson dev_dbg(host->dev.parent, 740184902Srwatson " start fifo xfer %p: len %u tx %p rx %p bitpw %d\n", 741184902Srwatson xfer, xfer->len, xfer->tx_buf, xfer->rx_buf, 742184902Srwatson xfer->bits_per_word); 743186647Srwatson 744186647Srwatson /* 745186647Srwatson * Enable RX FIFO Threshold Flag interrupt to be notified about 746186647Srwatson * transfer completion. 747186647Srwatson */ 748186647Srwatson spi_writel(as, IER, SPI_BIT(RXFTHF) | SPI_BIT(OVRES)); 749186647Srwatson} 750186647Srwatson 751186647Srwatson/* 752186647Srwatson * Next transfer using PIO. 753186647Srwatson */ 754186647Srwatsonstatic void atmel_spi_next_xfer_pio(struct spi_controller *host, 755186647Srwatson struct spi_transfer *xfer) 756186647Srwatson{ 757184902Srwatson struct atmel_spi *as = spi_controller_get_devdata(host); 758186647Srwatson 759184902Srwatson if (as->fifo_size) 760184902Srwatson atmel_spi_next_xfer_fifo(host, xfer); 761184902Srwatson else 762184902Srwatson atmel_spi_next_xfer_single(host, xfer); 763184902Srwatson} 764184902Srwatson 765184902Srwatson/* 766184902Srwatson * Submit next transfer for DMA. 767186647Srwatson */ 768184902Srwatsonstatic int atmel_spi_next_xfer_dma_submit(struct spi_controller *host, 769186647Srwatson struct spi_transfer *xfer, 770186647Srwatson u32 *plen) 771186647Srwatson{ 772186647Srwatson struct atmel_spi *as = spi_controller_get_devdata(host); 773186647Srwatson struct dma_chan *rxchan = host->dma_rx; 774186647Srwatson struct dma_chan *txchan = host->dma_tx; 775186647Srwatson struct dma_async_tx_descriptor *rxdesc; 776184902Srwatson struct dma_async_tx_descriptor *txdesc; 777184902Srwatson dma_cookie_t cookie; 778184902Srwatson 779184902Srwatson dev_vdbg(host->dev.parent, "atmel_spi_next_xfer_dma_submit\n"); 780184902Srwatson 781184902Srwatson /* Check that the channels are available */ 782184902Srwatson if (!rxchan || !txchan) 783184902Srwatson return -ENODEV; 784186647Srwatson 785186647Srwatson 786184902Srwatson *plen = xfer->len; 787186647Srwatson 788189279Srwatson if (atmel_spi_dma_slave_config(as, xfer->bits_per_word)) 789184902Srwatson goto err_exit; 790184902Srwatson 791184902Srwatson /* Send both scatterlists */ 792186647Srwatson if (atmel_spi_is_vmalloc_xfer(xfer) && 793184902Srwatson IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) { 794186647Srwatson rxdesc = dmaengine_prep_slave_single(rxchan, 795184902Srwatson as->dma_addr_rx_bbuf, 796186647Srwatson xfer->len, 797186647Srwatson DMA_DEV_TO_MEM, 798184902Srwatson DMA_PREP_INTERRUPT | 799184902Srwatson DMA_CTRL_ACK); 800 } else { 801 rxdesc = dmaengine_prep_slave_sg(rxchan, 802 xfer->rx_sg.sgl, 803 xfer->rx_sg.nents, 804 DMA_DEV_TO_MEM, 805 DMA_PREP_INTERRUPT | 806 DMA_CTRL_ACK); 807 } 808 if (!rxdesc) 809 goto err_dma; 810 811 if (atmel_spi_is_vmalloc_xfer(xfer) && 812 IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) { 813 memcpy(as->addr_tx_bbuf, xfer->tx_buf, xfer->len); 814 txdesc = dmaengine_prep_slave_single(txchan, 815 as->dma_addr_tx_bbuf, 816 xfer->len, DMA_MEM_TO_DEV, 817 DMA_PREP_INTERRUPT | 818 DMA_CTRL_ACK); 819 } else { 820 txdesc = dmaengine_prep_slave_sg(txchan, 821 xfer->tx_sg.sgl, 822 xfer->tx_sg.nents, 823 DMA_MEM_TO_DEV, 824 DMA_PREP_INTERRUPT | 825 DMA_CTRL_ACK); 826 } 827 if (!txdesc) 828 goto err_dma; 829 830 dev_dbg(host->dev.parent, 831 " start dma xfer %p: len %u tx %p/%08llx rx %p/%08llx\n", 832 xfer, xfer->len, xfer->tx_buf, (unsigned long long)xfer->tx_dma, 833 xfer->rx_buf, (unsigned long long)xfer->rx_dma); 834 835 /* Enable relevant interrupts */ 836 spi_writel(as, IER, SPI_BIT(OVRES)); 837 838 /* Put the callback on the RX transfer only, that should finish last */ 839 rxdesc->callback = dma_callback; 840 rxdesc->callback_param = host; 841 842 /* Submit and fire RX and TX with TX last so we're ready to read! */ 843 cookie = rxdesc->tx_submit(rxdesc); 844 if (dma_submit_error(cookie)) 845 goto err_dma; 846 cookie = txdesc->tx_submit(txdesc); 847 if (dma_submit_error(cookie)) 848 goto err_dma; 849 rxchan->device->device_issue_pending(rxchan); 850 txchan->device->device_issue_pending(txchan); 851 852 return 0; 853 854err_dma: 855 spi_writel(as, IDR, SPI_BIT(OVRES)); 856 atmel_spi_stop_dma(host); 857err_exit: 858 return -ENOMEM; 859} 860 861static void atmel_spi_next_xfer_data(struct spi_controller *host, 862 struct spi_transfer *xfer, 863 dma_addr_t *tx_dma, 864 dma_addr_t *rx_dma, 865 u32 *plen) 866{ 867 *rx_dma = xfer->rx_dma + xfer->len - *plen; 868 *tx_dma = xfer->tx_dma + xfer->len - *plen; 869 if (*plen > host->max_dma_len) 870 *plen = host->max_dma_len; 871} 872 873static int atmel_spi_set_xfer_speed(struct atmel_spi *as, 874 struct spi_device *spi, 875 struct spi_transfer *xfer) 876{ 877 u32 scbr, csr; 878 unsigned long bus_hz; 879 int chip_select; 880 881 if (spi_get_csgpiod(spi, 0)) 882 chip_select = as->native_cs_for_gpio; 883 else 884 chip_select = spi_get_chipselect(spi, 0); 885 886 /* v1 chips start out at half the peripheral bus speed. */ 887 bus_hz = as->spi_clk; 888 if (!atmel_spi_is_v2(as)) 889 bus_hz /= 2; 890 891 /* 892 * Calculate the lowest divider that satisfies the 893 * constraint, assuming div32/fdiv/mbz == 0. 894 */ 895 scbr = DIV_ROUND_UP(bus_hz, xfer->speed_hz); 896 897 /* 898 * If the resulting divider doesn't fit into the 899 * register bitfield, we can't satisfy the constraint. 900 */ 901 if (scbr >= (1 << SPI_SCBR_SIZE)) { 902 dev_err(&spi->dev, 903 "setup: %d Hz too slow, scbr %u; min %ld Hz\n", 904 xfer->speed_hz, scbr, bus_hz/255); 905 return -EINVAL; 906 } 907 if (scbr == 0) { 908 dev_err(&spi->dev, 909 "setup: %d Hz too high, scbr %u; max %ld Hz\n", 910 xfer->speed_hz, scbr, bus_hz); 911 return -EINVAL; 912 } 913 csr = spi_readl(as, CSR0 + 4 * chip_select); 914 csr = SPI_BFINS(SCBR, scbr, csr); 915 spi_writel(as, CSR0 + 4 * chip_select, csr); 916 xfer->effective_speed_hz = bus_hz / scbr; 917 918 return 0; 919} 920 921/* 922 * Submit next transfer for PDC. 923 * lock is held, spi irq is blocked 924 */ 925static void atmel_spi_pdc_next_xfer(struct spi_controller *host, 926 struct spi_transfer *xfer) 927{ 928 struct atmel_spi *as = spi_controller_get_devdata(host); 929 u32 len; 930 dma_addr_t tx_dma, rx_dma; 931 932 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); 933 934 len = as->current_remaining_bytes; 935 atmel_spi_next_xfer_data(host, xfer, &tx_dma, &rx_dma, &len); 936 as->current_remaining_bytes -= len; 937 938 spi_writel(as, RPR, rx_dma); 939 spi_writel(as, TPR, tx_dma); 940 941 if (xfer->bits_per_word > 8) 942 len >>= 1; 943 spi_writel(as, RCR, len); 944 spi_writel(as, TCR, len); 945 946 dev_dbg(&host->dev, 947 " start xfer %p: len %u tx %p/%08llx rx %p/%08llx\n", 948 xfer, xfer->len, xfer->tx_buf, 949 (unsigned long long)xfer->tx_dma, xfer->rx_buf, 950 (unsigned long long)xfer->rx_dma); 951 952 if (as->current_remaining_bytes) { 953 len = as->current_remaining_bytes; 954 atmel_spi_next_xfer_data(host, xfer, &tx_dma, &rx_dma, &len); 955 as->current_remaining_bytes -= len; 956 957 spi_writel(as, RNPR, rx_dma); 958 spi_writel(as, TNPR, tx_dma); 959 960 if (xfer->bits_per_word > 8) 961 len >>= 1; 962 spi_writel(as, RNCR, len); 963 spi_writel(as, TNCR, len); 964 965 dev_dbg(&host->dev, 966 " next xfer %p: len %u tx %p/%08llx rx %p/%08llx\n", 967 xfer, xfer->len, xfer->tx_buf, 968 (unsigned long long)xfer->tx_dma, xfer->rx_buf, 969 (unsigned long long)xfer->rx_dma); 970 } 971 972 /* REVISIT: We're waiting for RXBUFF before we start the next 973 * transfer because we need to handle some difficult timing 974 * issues otherwise. If we wait for TXBUFE in one transfer and 975 * then starts waiting for RXBUFF in the next, it's difficult 976 * to tell the difference between the RXBUFF interrupt we're 977 * actually waiting for and the RXBUFF interrupt of the 978 * previous transfer. 979 * 980 * It should be doable, though. Just not now... 981 */ 982 spi_writel(as, IER, SPI_BIT(RXBUFF) | SPI_BIT(OVRES)); 983 spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN)); 984} 985 986/* 987 * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma: 988 * - The buffer is either valid for CPU access, else NULL 989 * - If the buffer is valid, so is its DMA address 990 */ 991static int 992atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer) 993{ 994 struct device *dev = &as->pdev->dev; 995 996 xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS; 997 if (xfer->tx_buf) { 998 /* tx_buf is a const void* where we need a void * for the dma 999 * mapping */ 1000 void *nonconst_tx = (void *)xfer->tx_buf; 1001 1002 xfer->tx_dma = dma_map_single(dev, 1003 nonconst_tx, xfer->len, 1004 DMA_TO_DEVICE); 1005 if (dma_mapping_error(dev, xfer->tx_dma)) 1006 return -ENOMEM; 1007 } 1008 if (xfer->rx_buf) { 1009 xfer->rx_dma = dma_map_single(dev, 1010 xfer->rx_buf, xfer->len, 1011 DMA_FROM_DEVICE); 1012 if (dma_mapping_error(dev, xfer->rx_dma)) { 1013 if (xfer->tx_buf) 1014 dma_unmap_single(dev, 1015 xfer->tx_dma, xfer->len, 1016 DMA_TO_DEVICE); 1017 return -ENOMEM; 1018 } 1019 } 1020 return 0; 1021} 1022 1023static void atmel_spi_dma_unmap_xfer(struct spi_controller *host, 1024 struct spi_transfer *xfer) 1025{ 1026 if (xfer->tx_dma != INVALID_DMA_ADDRESS) 1027 dma_unmap_single(host->dev.parent, xfer->tx_dma, 1028 xfer->len, DMA_TO_DEVICE); 1029 if (xfer->rx_dma != INVALID_DMA_ADDRESS) 1030 dma_unmap_single(host->dev.parent, xfer->rx_dma, 1031 xfer->len, DMA_FROM_DEVICE); 1032} 1033 1034static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as) 1035{ 1036 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); 1037} 1038 1039static void 1040atmel_spi_pump_single_data(struct atmel_spi *as, struct spi_transfer *xfer) 1041{ 1042 u8 *rxp; 1043 u16 *rxp16; 1044 unsigned long xfer_pos = xfer->len - as->current_remaining_bytes; 1045 1046 if (xfer->bits_per_word > 8) { 1047 rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos); 1048 *rxp16 = spi_readl(as, RDR); 1049 } else { 1050 rxp = ((u8 *)xfer->rx_buf) + xfer_pos; 1051 *rxp = spi_readl(as, RDR); 1052 } 1053 if (xfer->bits_per_word > 8) { 1054 if (as->current_remaining_bytes > 2) 1055 as->current_remaining_bytes -= 2; 1056 else 1057 as->current_remaining_bytes = 0; 1058 } else { 1059 as->current_remaining_bytes--; 1060 } 1061} 1062 1063static void 1064atmel_spi_pump_fifo_data(struct atmel_spi *as, struct spi_transfer *xfer) 1065{ 1066 u32 fifolr = spi_readl(as, FLR); 1067 u32 num_bytes, num_data = SPI_BFEXT(RXFL, fifolr); 1068 u32 offset = xfer->len - as->current_remaining_bytes; 1069 u16 *words = (u16 *)((u8 *)xfer->rx_buf + offset); 1070 u8 *bytes = (u8 *)((u8 *)xfer->rx_buf + offset); 1071 u16 rd; /* RD field is the lowest 16 bits of RDR */ 1072 1073 /* Update the number of remaining bytes to transfer */ 1074 num_bytes = ((xfer->bits_per_word > 8) ? 1075 (num_data << 1) : 1076 num_data); 1077 1078 if (as->current_remaining_bytes > num_bytes) 1079 as->current_remaining_bytes -= num_bytes; 1080 else 1081 as->current_remaining_bytes = 0; 1082 1083 /* Handle odd number of bytes when data are more than 8bit width */ 1084 if (xfer->bits_per_word > 8) 1085 as->current_remaining_bytes &= ~0x1; 1086 1087 /* Read data */ 1088 while (num_data) { 1089 rd = spi_readl(as, RDR); 1090 if (xfer->bits_per_word > 8) 1091 *words++ = rd; 1092 else 1093 *bytes++ = rd; 1094 num_data--; 1095 } 1096} 1097 1098/* Called from IRQ 1099 * 1100 * Must update "current_remaining_bytes" to keep track of data 1101 * to transfer. 1102 */ 1103static void 1104atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer) 1105{ 1106 if (as->fifo_size) 1107 atmel_spi_pump_fifo_data(as, xfer); 1108 else 1109 atmel_spi_pump_single_data(as, xfer); 1110} 1111 1112/* Interrupt 1113 * 1114 */ 1115static irqreturn_t 1116atmel_spi_pio_interrupt(int irq, void *dev_id) 1117{ 1118 struct spi_controller *host = dev_id; 1119 struct atmel_spi *as = spi_controller_get_devdata(host); 1120 u32 status, pending, imr; 1121 struct spi_transfer *xfer; 1122 int ret = IRQ_NONE; 1123 1124 imr = spi_readl(as, IMR); 1125 status = spi_readl(as, SR); 1126 pending = status & imr; 1127 1128 if (pending & SPI_BIT(OVRES)) { 1129 ret = IRQ_HANDLED; 1130 spi_writel(as, IDR, SPI_BIT(OVRES)); 1131 dev_warn(host->dev.parent, "overrun\n"); 1132 1133 /* 1134 * When we get an overrun, we disregard the current 1135 * transfer. Data will not be copied back from any 1136 * bounce buffer and msg->actual_len will not be 1137 * updated with the last xfer. 1138 * 1139 * We will also not process any remaning transfers in 1140 * the message. 1141 */ 1142 as->done_status = -EIO; 1143 smp_wmb(); 1144 1145 /* Clear any overrun happening while cleaning up */ 1146 spi_readl(as, SR); 1147 1148 complete(&as->xfer_completion); 1149 1150 } else if (pending & (SPI_BIT(RDRF) | SPI_BIT(RXFTHF))) { 1151 atmel_spi_lock(as); 1152 1153 if (as->current_remaining_bytes) { 1154 ret = IRQ_HANDLED; 1155 xfer = as->current_transfer; 1156 atmel_spi_pump_pio_data(as, xfer); 1157 if (!as->current_remaining_bytes) 1158 spi_writel(as, IDR, pending); 1159 1160 complete(&as->xfer_completion); 1161 } 1162 1163 atmel_spi_unlock(as); 1164 } else { 1165 WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending); 1166 ret = IRQ_HANDLED; 1167 spi_writel(as, IDR, pending); 1168 } 1169 1170 return ret; 1171} 1172 1173static irqreturn_t 1174atmel_spi_pdc_interrupt(int irq, void *dev_id) 1175{ 1176 struct spi_controller *host = dev_id; 1177 struct atmel_spi *as = spi_controller_get_devdata(host); 1178 u32 status, pending, imr; 1179 int ret = IRQ_NONE; 1180 1181 imr = spi_readl(as, IMR); 1182 status = spi_readl(as, SR); 1183 pending = status & imr; 1184 1185 if (pending & SPI_BIT(OVRES)) { 1186 1187 ret = IRQ_HANDLED; 1188 1189 spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX) 1190 | SPI_BIT(OVRES))); 1191 1192 /* Clear any overrun happening while cleaning up */ 1193 spi_readl(as, SR); 1194 1195 as->done_status = -EIO; 1196 1197 complete(&as->xfer_completion); 1198 1199 } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) { 1200 ret = IRQ_HANDLED; 1201 1202 spi_writel(as, IDR, pending); 1203 1204 complete(&as->xfer_completion); 1205 } 1206 1207 return ret; 1208} 1209 1210static int atmel_word_delay_csr(struct spi_device *spi, struct atmel_spi *as) 1211{ 1212 struct spi_delay *delay = &spi->word_delay; 1213 u32 value = delay->value; 1214 1215 switch (delay->unit) { 1216 case SPI_DELAY_UNIT_NSECS: 1217 value /= 1000; 1218 break; 1219 case SPI_DELAY_UNIT_USECS: 1220 break; 1221 default: 1222 return -EINVAL; 1223 } 1224 1225 return (as->spi_clk / 1000000 * value) >> 5; 1226} 1227 1228static void initialize_native_cs_for_gpio(struct atmel_spi *as) 1229{ 1230 int i; 1231 struct spi_controller *host = platform_get_drvdata(as->pdev); 1232 1233 if (!as->native_cs_free) 1234 return; /* already initialized */ 1235 1236 if (!host->cs_gpiods) 1237 return; /* No CS GPIO */ 1238 1239 /* 1240 * On the first version of the controller (AT91RM9200), CS0 1241 * can't be used associated with GPIO 1242 */ 1243 if (atmel_spi_is_v2(as)) 1244 i = 0; 1245 else 1246 i = 1; 1247 1248 for (; i < 4; i++) 1249 if (host->cs_gpiods[i]) 1250 as->native_cs_free |= BIT(i); 1251 1252 if (as->native_cs_free) 1253 as->native_cs_for_gpio = ffs(as->native_cs_free); 1254} 1255 1256static int atmel_spi_setup(struct spi_device *spi) 1257{ 1258 struct atmel_spi *as; 1259 struct atmel_spi_device *asd; 1260 u32 csr; 1261 unsigned int bits = spi->bits_per_word; 1262 int chip_select; 1263 int word_delay_csr; 1264 1265 as = spi_controller_get_devdata(spi->controller); 1266 1267 /* see notes above re chipselect */ 1268 if (!spi_get_csgpiod(spi, 0) && (spi->mode & SPI_CS_HIGH)) { 1269 dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n"); 1270 return -EINVAL; 1271 } 1272 1273 /* Setup() is called during spi_register_controller(aka 1274 * spi_register_master) but after all membmers of the cs_gpiod 1275 * array have been filled, so we can looked for which native 1276 * CS will be free for using with GPIO 1277 */ 1278 initialize_native_cs_for_gpio(as); 1279 1280 if (spi_get_csgpiod(spi, 0) && as->native_cs_free) { 1281 dev_err(&spi->dev, 1282 "No native CS available to support this GPIO CS\n"); 1283 return -EBUSY; 1284 } 1285 1286 if (spi_get_csgpiod(spi, 0)) 1287 chip_select = as->native_cs_for_gpio; 1288 else 1289 chip_select = spi_get_chipselect(spi, 0); 1290 1291 csr = SPI_BF(BITS, bits - 8); 1292 if (spi->mode & SPI_CPOL) 1293 csr |= SPI_BIT(CPOL); 1294 if (!(spi->mode & SPI_CPHA)) 1295 csr |= SPI_BIT(NCPHA); 1296 1297 if (!spi_get_csgpiod(spi, 0)) 1298 csr |= SPI_BIT(CSAAT); 1299 csr |= SPI_BF(DLYBS, 0); 1300 1301 word_delay_csr = atmel_word_delay_csr(spi, as); 1302 if (word_delay_csr < 0) 1303 return word_delay_csr; 1304 1305 /* DLYBCT adds delays between words. This is useful for slow devices 1306 * that need a bit of time to setup the next transfer. 1307 */ 1308 csr |= SPI_BF(DLYBCT, word_delay_csr); 1309 1310 asd = spi->controller_state; 1311 if (!asd) { 1312 asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL); 1313 if (!asd) 1314 return -ENOMEM; 1315 1316 spi->controller_state = asd; 1317 } 1318 1319 asd->csr = csr; 1320 1321 dev_dbg(&spi->dev, 1322 "setup: bpw %u mode 0x%x -> csr%d %08x\n", 1323 bits, spi->mode, spi_get_chipselect(spi, 0), csr); 1324 1325 if (!atmel_spi_is_v2(as)) 1326 spi_writel(as, CSR0 + 4 * chip_select, csr); 1327 1328 return 0; 1329} 1330 1331static void atmel_spi_set_cs(struct spi_device *spi, bool enable) 1332{ 1333 struct atmel_spi *as = spi_controller_get_devdata(spi->controller); 1334 /* the core doesn't really pass us enable/disable, but CS HIGH vs CS LOW 1335 * since we already have routines for activate/deactivate translate 1336 * high/low to active/inactive 1337 */ 1338 enable = (!!(spi->mode & SPI_CS_HIGH) == enable); 1339 1340 if (enable) { 1341 cs_activate(as, spi); 1342 } else { 1343 cs_deactivate(as, spi); 1344 } 1345 1346} 1347 1348static int atmel_spi_one_transfer(struct spi_controller *host, 1349 struct spi_device *spi, 1350 struct spi_transfer *xfer) 1351{ 1352 struct atmel_spi *as; 1353 u8 bits; 1354 u32 len; 1355 struct atmel_spi_device *asd; 1356 int timeout; 1357 int ret; 1358 unsigned int dma_timeout; 1359 long ret_timeout; 1360 1361 as = spi_controller_get_devdata(host); 1362 1363 asd = spi->controller_state; 1364 bits = (asd->csr >> 4) & 0xf; 1365 if (bits != xfer->bits_per_word - 8) { 1366 dev_dbg(&spi->dev, 1367 "you can't yet change bits_per_word in transfers\n"); 1368 return -ENOPROTOOPT; 1369 } 1370 1371 /* 1372 * DMA map early, for performance (empties dcache ASAP) and 1373 * better fault reporting. 1374 */ 1375 if (as->use_pdc) { 1376 if (atmel_spi_dma_map_xfer(as, xfer) < 0) 1377 return -ENOMEM; 1378 } 1379 1380 atmel_spi_set_xfer_speed(as, spi, xfer); 1381 1382 as->done_status = 0; 1383 as->current_transfer = xfer; 1384 as->current_remaining_bytes = xfer->len; 1385 while (as->current_remaining_bytes) { 1386 reinit_completion(&as->xfer_completion); 1387 1388 if (as->use_pdc) { 1389 atmel_spi_lock(as); 1390 atmel_spi_pdc_next_xfer(host, xfer); 1391 atmel_spi_unlock(as); 1392 } else if (atmel_spi_use_dma(as, xfer)) { 1393 len = as->current_remaining_bytes; 1394 ret = atmel_spi_next_xfer_dma_submit(host, 1395 xfer, &len); 1396 if (ret) { 1397 dev_err(&spi->dev, 1398 "unable to use DMA, fallback to PIO\n"); 1399 as->done_status = ret; 1400 break; 1401 } else { 1402 as->current_remaining_bytes -= len; 1403 if (as->current_remaining_bytes < 0) 1404 as->current_remaining_bytes = 0; 1405 } 1406 } else { 1407 atmel_spi_lock(as); 1408 atmel_spi_next_xfer_pio(host, xfer); 1409 atmel_spi_unlock(as); 1410 } 1411 1412 dma_timeout = msecs_to_jiffies(spi_controller_xfer_timeout(host, xfer)); 1413 ret_timeout = wait_for_completion_timeout(&as->xfer_completion, dma_timeout); 1414 if (!ret_timeout) { 1415 dev_err(&spi->dev, "spi transfer timeout\n"); 1416 as->done_status = -EIO; 1417 } 1418 1419 if (as->done_status) 1420 break; 1421 } 1422 1423 if (as->done_status) { 1424 if (as->use_pdc) { 1425 dev_warn(host->dev.parent, 1426 "overrun (%u/%u remaining)\n", 1427 spi_readl(as, TCR), spi_readl(as, RCR)); 1428 1429 /* 1430 * Clean up DMA registers and make sure the data 1431 * registers are empty. 1432 */ 1433 spi_writel(as, RNCR, 0); 1434 spi_writel(as, TNCR, 0); 1435 spi_writel(as, RCR, 0); 1436 spi_writel(as, TCR, 0); 1437 for (timeout = 1000; timeout; timeout--) 1438 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY)) 1439 break; 1440 if (!timeout) 1441 dev_warn(host->dev.parent, 1442 "timeout waiting for TXEMPTY"); 1443 while (spi_readl(as, SR) & SPI_BIT(RDRF)) 1444 spi_readl(as, RDR); 1445 1446 /* Clear any overrun happening while cleaning up */ 1447 spi_readl(as, SR); 1448 1449 } else if (atmel_spi_use_dma(as, xfer)) { 1450 atmel_spi_stop_dma(host); 1451 } 1452 } 1453 1454 if (as->use_pdc) 1455 atmel_spi_dma_unmap_xfer(host, xfer); 1456 1457 if (as->use_pdc) 1458 atmel_spi_disable_pdc_transfer(as); 1459 1460 return as->done_status; 1461} 1462 1463static void atmel_spi_cleanup(struct spi_device *spi) 1464{ 1465 struct atmel_spi_device *asd = spi->controller_state; 1466 1467 if (!asd) 1468 return; 1469 1470 spi->controller_state = NULL; 1471 kfree(asd); 1472} 1473 1474static inline unsigned int atmel_get_version(struct atmel_spi *as) 1475{ 1476 return spi_readl(as, VERSION) & 0x00000fff; 1477} 1478 1479static void atmel_get_caps(struct atmel_spi *as) 1480{ 1481 unsigned int version; 1482 1483 version = atmel_get_version(as); 1484 1485 as->caps.is_spi2 = version > 0x121; 1486 as->caps.has_wdrbt = version >= 0x210; 1487 as->caps.has_dma_support = version >= 0x212; 1488 as->caps.has_pdc_support = version < 0x212; 1489} 1490 1491static void atmel_spi_init(struct atmel_spi *as) 1492{ 1493 spi_writel(as, CR, SPI_BIT(SWRST)); 1494 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ 1495 1496 /* It is recommended to enable FIFOs first thing after reset */ 1497 if (as->fifo_size) 1498 spi_writel(as, CR, SPI_BIT(FIFOEN)); 1499 1500 if (as->caps.has_wdrbt) { 1501 spi_writel(as, MR, SPI_BIT(WDRBT) | SPI_BIT(MODFDIS) 1502 | SPI_BIT(MSTR)); 1503 } else { 1504 spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS)); 1505 } 1506 1507 if (as->use_pdc) 1508 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS)); 1509 spi_writel(as, CR, SPI_BIT(SPIEN)); 1510} 1511 1512static int atmel_spi_probe(struct platform_device *pdev) 1513{ 1514 struct resource *regs; 1515 int irq; 1516 struct clk *clk; 1517 int ret; 1518 struct spi_controller *host; 1519 struct atmel_spi *as; 1520 1521 /* Select default pin state */ 1522 pinctrl_pm_select_default_state(&pdev->dev); 1523 1524 irq = platform_get_irq(pdev, 0); 1525 if (irq < 0) 1526 return irq; 1527 1528 clk = devm_clk_get(&pdev->dev, "spi_clk"); 1529 if (IS_ERR(clk)) 1530 return PTR_ERR(clk); 1531 1532 /* setup spi core then atmel-specific driver state */ 1533 host = spi_alloc_host(&pdev->dev, sizeof(*as)); 1534 if (!host) 1535 return -ENOMEM; 1536 1537 /* the spi->mode bits understood by this driver: */ 1538 host->use_gpio_descriptors = true; 1539 host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1540 host->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16); 1541 host->dev.of_node = pdev->dev.of_node; 1542 host->bus_num = pdev->id; 1543 host->num_chipselect = 4; 1544 host->setup = atmel_spi_setup; 1545 host->flags = (SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX | 1546 SPI_CONTROLLER_GPIO_SS); 1547 host->transfer_one = atmel_spi_one_transfer; 1548 host->set_cs = atmel_spi_set_cs; 1549 host->cleanup = atmel_spi_cleanup; 1550 host->auto_runtime_pm = true; 1551 host->max_dma_len = SPI_MAX_DMA_XFER; 1552 host->can_dma = atmel_spi_can_dma; 1553 platform_set_drvdata(pdev, host); 1554 1555 as = spi_controller_get_devdata(host); 1556 1557 spin_lock_init(&as->lock); 1558 1559 as->pdev = pdev; 1560 as->regs = devm_platform_get_and_ioremap_resource(pdev, 0, ®s); 1561 if (IS_ERR(as->regs)) { 1562 ret = PTR_ERR(as->regs); 1563 goto out_unmap_regs; 1564 } 1565 as->phybase = regs->start; 1566 as->irq = irq; 1567 as->clk = clk; 1568 1569 init_completion(&as->xfer_completion); 1570 1571 atmel_get_caps(as); 1572 1573 as->use_dma = false; 1574 as->use_pdc = false; 1575 if (as->caps.has_dma_support) { 1576 ret = atmel_spi_configure_dma(host, as); 1577 if (ret == 0) { 1578 as->use_dma = true; 1579 } else if (ret == -EPROBE_DEFER) { 1580 goto out_unmap_regs; 1581 } 1582 } else if (as->caps.has_pdc_support) { 1583 as->use_pdc = true; 1584 } 1585 1586 if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) { 1587 as->addr_rx_bbuf = dma_alloc_coherent(&pdev->dev, 1588 SPI_MAX_DMA_XFER, 1589 &as->dma_addr_rx_bbuf, 1590 GFP_KERNEL | GFP_DMA); 1591 if (!as->addr_rx_bbuf) { 1592 as->use_dma = false; 1593 } else { 1594 as->addr_tx_bbuf = dma_alloc_coherent(&pdev->dev, 1595 SPI_MAX_DMA_XFER, 1596 &as->dma_addr_tx_bbuf, 1597 GFP_KERNEL | GFP_DMA); 1598 if (!as->addr_tx_bbuf) { 1599 as->use_dma = false; 1600 dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER, 1601 as->addr_rx_bbuf, 1602 as->dma_addr_rx_bbuf); 1603 } 1604 } 1605 if (!as->use_dma) 1606 dev_info(host->dev.parent, 1607 " can not allocate dma coherent memory\n"); 1608 } 1609 1610 if (as->caps.has_dma_support && !as->use_dma) 1611 dev_info(&pdev->dev, "Atmel SPI Controller using PIO only\n"); 1612 1613 if (as->use_pdc) { 1614 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pdc_interrupt, 1615 0, dev_name(&pdev->dev), host); 1616 } else { 1617 ret = devm_request_irq(&pdev->dev, irq, atmel_spi_pio_interrupt, 1618 0, dev_name(&pdev->dev), host); 1619 } 1620 if (ret) 1621 goto out_unmap_regs; 1622 1623 /* Initialize the hardware */ 1624 ret = clk_prepare_enable(clk); 1625 if (ret) 1626 goto out_free_irq; 1627 1628 as->spi_clk = clk_get_rate(clk); 1629 1630 as->fifo_size = 0; 1631 if (!of_property_read_u32(pdev->dev.of_node, "atmel,fifo-size", 1632 &as->fifo_size)) { 1633 dev_info(&pdev->dev, "Using FIFO (%u data)\n", as->fifo_size); 1634 } 1635 1636 atmel_spi_init(as); 1637 1638 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT); 1639 pm_runtime_use_autosuspend(&pdev->dev); 1640 pm_runtime_set_active(&pdev->dev); 1641 pm_runtime_enable(&pdev->dev); 1642 1643 ret = devm_spi_register_controller(&pdev->dev, host); 1644 if (ret) 1645 goto out_free_dma; 1646 1647 /* go! */ 1648 dev_info(&pdev->dev, "Atmel SPI Controller version 0x%x at 0x%08lx (irq %d)\n", 1649 atmel_get_version(as), (unsigned long)regs->start, 1650 irq); 1651 1652 return 0; 1653 1654out_free_dma: 1655 pm_runtime_disable(&pdev->dev); 1656 pm_runtime_set_suspended(&pdev->dev); 1657 1658 if (as->use_dma) 1659 atmel_spi_release_dma(host); 1660 1661 spi_writel(as, CR, SPI_BIT(SWRST)); 1662 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ 1663 clk_disable_unprepare(clk); 1664out_free_irq: 1665out_unmap_regs: 1666 spi_controller_put(host); 1667 return ret; 1668} 1669 1670static void atmel_spi_remove(struct platform_device *pdev) 1671{ 1672 struct spi_controller *host = platform_get_drvdata(pdev); 1673 struct atmel_spi *as = spi_controller_get_devdata(host); 1674 1675 pm_runtime_get_sync(&pdev->dev); 1676 1677 /* reset the hardware and block queue progress */ 1678 if (as->use_dma) { 1679 atmel_spi_stop_dma(host); 1680 atmel_spi_release_dma(host); 1681 if (IS_ENABLED(CONFIG_SOC_SAM_V4_V5)) { 1682 dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER, 1683 as->addr_tx_bbuf, 1684 as->dma_addr_tx_bbuf); 1685 dma_free_coherent(&pdev->dev, SPI_MAX_DMA_XFER, 1686 as->addr_rx_bbuf, 1687 as->dma_addr_rx_bbuf); 1688 } 1689 } 1690 1691 spin_lock_irq(&as->lock); 1692 spi_writel(as, CR, SPI_BIT(SWRST)); 1693 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */ 1694 spi_readl(as, SR); 1695 spin_unlock_irq(&as->lock); 1696 1697 clk_disable_unprepare(as->clk); 1698 1699 pm_runtime_put_noidle(&pdev->dev); 1700 pm_runtime_disable(&pdev->dev); 1701} 1702 1703static int atmel_spi_runtime_suspend(struct device *dev) 1704{ 1705 struct spi_controller *host = dev_get_drvdata(dev); 1706 struct atmel_spi *as = spi_controller_get_devdata(host); 1707 1708 clk_disable_unprepare(as->clk); 1709 pinctrl_pm_select_sleep_state(dev); 1710 1711 return 0; 1712} 1713 1714static int atmel_spi_runtime_resume(struct device *dev) 1715{ 1716 struct spi_controller *host = dev_get_drvdata(dev); 1717 struct atmel_spi *as = spi_controller_get_devdata(host); 1718 1719 pinctrl_pm_select_default_state(dev); 1720 1721 return clk_prepare_enable(as->clk); 1722} 1723 1724static int atmel_spi_suspend(struct device *dev) 1725{ 1726 struct spi_controller *host = dev_get_drvdata(dev); 1727 int ret; 1728 1729 /* Stop the queue running */ 1730 ret = spi_controller_suspend(host); 1731 if (ret) 1732 return ret; 1733 1734 if (!pm_runtime_suspended(dev)) 1735 atmel_spi_runtime_suspend(dev); 1736 1737 return 0; 1738} 1739 1740static int atmel_spi_resume(struct device *dev) 1741{ 1742 struct spi_controller *host = dev_get_drvdata(dev); 1743 struct atmel_spi *as = spi_controller_get_devdata(host); 1744 int ret; 1745 1746 ret = clk_prepare_enable(as->clk); 1747 if (ret) 1748 return ret; 1749 1750 atmel_spi_init(as); 1751 1752 clk_disable_unprepare(as->clk); 1753 1754 if (!pm_runtime_suspended(dev)) { 1755 ret = atmel_spi_runtime_resume(dev); 1756 if (ret) 1757 return ret; 1758 } 1759 1760 /* Start the queue running */ 1761 return spi_controller_resume(host); 1762} 1763 1764static const struct dev_pm_ops atmel_spi_pm_ops = { 1765 SYSTEM_SLEEP_PM_OPS(atmel_spi_suspend, atmel_spi_resume) 1766 RUNTIME_PM_OPS(atmel_spi_runtime_suspend, 1767 atmel_spi_runtime_resume, NULL) 1768}; 1769 1770static const struct of_device_id atmel_spi_dt_ids[] = { 1771 { .compatible = "atmel,at91rm9200-spi" }, 1772 { /* sentinel */ } 1773}; 1774 1775MODULE_DEVICE_TABLE(of, atmel_spi_dt_ids); 1776 1777static struct platform_driver atmel_spi_driver = { 1778 .driver = { 1779 .name = "atmel_spi", 1780 .pm = pm_ptr(&atmel_spi_pm_ops), 1781 .of_match_table = atmel_spi_dt_ids, 1782 }, 1783 .probe = atmel_spi_probe, 1784 .remove_new = atmel_spi_remove, 1785}; 1786module_platform_driver(atmel_spi_driver); 1787 1788MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver"); 1789MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); 1790MODULE_LICENSE("GPL"); 1791MODULE_ALIAS("platform:atmel_spi"); 1792