1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * Driver for Broadcom MPI3 Storage Controllers 4 * 5 * Copyright (C) 2017-2023 Broadcom Inc. 6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com) 7 * 8 */ 9 10#ifndef MPI3MR_H_INCLUDED 11#define MPI3MR_H_INCLUDED 12 13#include <linux/blkdev.h> 14#include <linux/blk-mq.h> 15#include <linux/blk-mq-pci.h> 16#include <linux/delay.h> 17#include <linux/dmapool.h> 18#include <linux/errno.h> 19#include <linux/init.h> 20#include <linux/io.h> 21#include <linux/interrupt.h> 22#include <linux/kernel.h> 23#include <linux/miscdevice.h> 24#include <linux/module.h> 25#include <linux/pci.h> 26#include <linux/poll.h> 27#include <linux/sched.h> 28#include <linux/slab.h> 29#include <linux/types.h> 30#include <linux/uaccess.h> 31#include <linux/utsname.h> 32#include <linux/workqueue.h> 33#include <asm/unaligned.h> 34#include <scsi/scsi.h> 35#include <scsi/scsi_cmnd.h> 36#include <scsi/scsi_dbg.h> 37#include <scsi/scsi_device.h> 38#include <scsi/scsi_host.h> 39#include <scsi/scsi_tcq.h> 40#include <uapi/scsi/scsi_bsg_mpi3mr.h> 41#include <scsi/scsi_transport_sas.h> 42 43#include "mpi/mpi30_transport.h" 44#include "mpi/mpi30_cnfg.h" 45#include "mpi/mpi30_image.h" 46#include "mpi/mpi30_init.h" 47#include "mpi/mpi30_ioc.h" 48#include "mpi/mpi30_sas.h" 49#include "mpi/mpi30_pci.h" 50#include "mpi3mr_debug.h" 51 52/* Global list and lock for storing multiple adapters managed by the driver */ 53extern spinlock_t mrioc_list_lock; 54extern struct list_head mrioc_list; 55extern int prot_mask; 56extern atomic64_t event_counter; 57 58#define MPI3MR_DRIVER_VERSION "8.8.1.0.50" 59#define MPI3MR_DRIVER_RELDATE "5-March-2024" 60 61#define MPI3MR_DRIVER_NAME "mpi3mr" 62#define MPI3MR_DRIVER_LICENSE "GPL" 63#define MPI3MR_DRIVER_AUTHOR "Broadcom Inc. <mpi3mr-linuxdrv.pdl@broadcom.com>" 64#define MPI3MR_DRIVER_DESC "MPI3 Storage Controller Device Driver" 65 66#define MPI3MR_NAME_LENGTH 64 67#define IOCNAME "%s: " 68 69#define MPI3MR_DEFAULT_MAX_IO_SIZE (1 * 1024 * 1024) 70 71/* Definitions for internal SGL and Chain SGL buffers */ 72#define MPI3MR_PAGE_SIZE_4K 4096 73#define MPI3MR_DEFAULT_SGL_ENTRIES 256 74#define MPI3MR_MAX_SGL_ENTRIES 2048 75 76/* Definitions for MAX values for shost */ 77#define MPI3MR_MAX_CMDS_LUN 128 78#define MPI3MR_MAX_CDB_LENGTH 32 79 80/* Admin queue management definitions */ 81#define MPI3MR_ADMIN_REQ_Q_SIZE (2 * MPI3MR_PAGE_SIZE_4K) 82#define MPI3MR_ADMIN_REPLY_Q_SIZE (4 * MPI3MR_PAGE_SIZE_4K) 83#define MPI3MR_ADMIN_REQ_FRAME_SZ 128 84#define MPI3MR_ADMIN_REPLY_FRAME_SZ 16 85 86/* Operational queue management definitions */ 87#define MPI3MR_OP_REQ_Q_QD 512 88#define MPI3MR_OP_REP_Q_QD 1024 89#define MPI3MR_OP_REP_Q_QD4K 4096 90#define MPI3MR_OP_REQ_Q_SEG_SIZE 4096 91#define MPI3MR_OP_REP_Q_SEG_SIZE 4096 92#define MPI3MR_MAX_SEG_LIST_SIZE 4096 93 94/* Reserved Host Tag definitions */ 95#define MPI3MR_HOSTTAG_INVALID 0xFFFF 96#define MPI3MR_HOSTTAG_INITCMDS 1 97#define MPI3MR_HOSTTAG_BSG_CMDS 2 98#define MPI3MR_HOSTTAG_PEL_ABORT 3 99#define MPI3MR_HOSTTAG_PEL_WAIT 4 100#define MPI3MR_HOSTTAG_BLK_TMS 5 101#define MPI3MR_HOSTTAG_CFG_CMDS 6 102#define MPI3MR_HOSTTAG_TRANSPORT_CMDS 7 103 104#define MPI3MR_NUM_DEVRMCMD 16 105#define MPI3MR_HOSTTAG_DEVRMCMD_MIN (MPI3MR_HOSTTAG_TRANSPORT_CMDS + 1) 106#define MPI3MR_HOSTTAG_DEVRMCMD_MAX (MPI3MR_HOSTTAG_DEVRMCMD_MIN + \ 107 MPI3MR_NUM_DEVRMCMD - 1) 108 109#define MPI3MR_INTERNAL_CMDS_RESVD MPI3MR_HOSTTAG_DEVRMCMD_MAX 110#define MPI3MR_NUM_EVTACKCMD 4 111#define MPI3MR_HOSTTAG_EVTACKCMD_MIN (MPI3MR_HOSTTAG_DEVRMCMD_MAX + 1) 112#define MPI3MR_HOSTTAG_EVTACKCMD_MAX (MPI3MR_HOSTTAG_EVTACKCMD_MIN + \ 113 MPI3MR_NUM_EVTACKCMD - 1) 114 115/* Reduced resource count definition for crash kernel */ 116#define MPI3MR_HOST_IOS_KDUMP 128 117 118/* command/controller interaction timeout definitions in seconds */ 119#define MPI3MR_INTADMCMD_TIMEOUT 60 120#define MPI3MR_PORTENABLE_TIMEOUT 300 121#define MPI3MR_PORTENABLE_POLL_INTERVAL 5 122#define MPI3MR_ABORTTM_TIMEOUT 60 123#define MPI3MR_RESETTM_TIMEOUT 60 124#define MPI3MR_RESET_HOST_IOWAIT_TIMEOUT 5 125#define MPI3MR_TSUPDATE_INTERVAL 900 126#define MPI3MR_DEFAULT_SHUTDOWN_TIME 120 127#define MPI3MR_RAID_ERRREC_RESET_TIMEOUT 180 128#define MPI3MR_PREPARE_FOR_RESET_TIMEOUT 180 129#define MPI3MR_RESET_ACK_TIMEOUT 30 130#define MPI3MR_MUR_TIMEOUT 120 131 132#define MPI3MR_WATCHDOG_INTERVAL 1000 /* in milli seconds */ 133 134#define MPI3MR_DEFAULT_CFG_PAGE_SZ 1024 /* in bytes */ 135 136#define MPI3MR_RESET_TOPOLOGY_SETTLE_TIME 10 137 138#define MPI3MR_SCMD_TIMEOUT (60 * HZ) 139#define MPI3MR_EH_SCMD_TIMEOUT (60 * HZ) 140 141/* Internal admin command state definitions*/ 142#define MPI3MR_CMD_NOTUSED 0x8000 143#define MPI3MR_CMD_COMPLETE 0x0001 144#define MPI3MR_CMD_PENDING 0x0002 145#define MPI3MR_CMD_REPLY_VALID 0x0004 146#define MPI3MR_CMD_RESET 0x0008 147 148/* Definitions for Event replies and sense buffer allocated per controller */ 149#define MPI3MR_NUM_EVT_REPLIES 64 150#define MPI3MR_SENSE_BUF_SZ 256 151#define MPI3MR_SENSEBUF_FACTOR 3 152#define MPI3MR_CHAINBUF_FACTOR 3 153#define MPI3MR_CHAINBUFDIX_FACTOR 2 154 155/* Invalid target device handle */ 156#define MPI3MR_INVALID_DEV_HANDLE 0xFFFF 157 158/* Controller Reset related definitions */ 159#define MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT 5 160#define MPI3MR_MAX_RESET_RETRY_COUNT 3 161 162/* ResponseCode definitions */ 163#define MPI3MR_RI_MASK_RESPCODE (0x000000FF) 164#define MPI3MR_RSP_IO_QUEUED_ON_IOC \ 165 MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC 166 167#define MPI3MR_DEFAULT_MDTS (128 * 1024) 168#define MPI3MR_DEFAULT_PGSZEXP (12) 169 170/* Command retry count definitions */ 171#define MPI3MR_DEV_RMHS_RETRY_COUNT 3 172#define MPI3MR_PEL_RETRY_COUNT 3 173 174/* Default target device queue depth */ 175#define MPI3MR_DEFAULT_SDEV_QD 32 176 177/* Definitions for Threaded IRQ poll*/ 178#define MPI3MR_IRQ_POLL_SLEEP 2 179#define MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT 8 180 181/* Definitions for the controller security status*/ 182#define MPI3MR_CTLR_SECURITY_STATUS_MASK 0x0C 183#define MPI3MR_CTLR_SECURE_DBG_STATUS_MASK 0x02 184 185#define MPI3MR_INVALID_DEVICE 0x00 186#define MPI3MR_CONFIG_SECURE_DEVICE 0x04 187#define MPI3MR_HARD_SECURE_DEVICE 0x08 188#define MPI3MR_TAMPERED_DEVICE 0x0C 189 190/* SGE Flag definition */ 191#define MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST \ 192 (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | MPI3_SGE_FLAGS_DLAS_SYSTEM | \ 193 MPI3_SGE_FLAGS_END_OF_LIST) 194 195/* MSI Index from Reply Queue Index */ 196#define REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, offset) (qidx + offset) 197 198/* 199 * Maximum data transfer size definitions for management 200 * application commands 201 */ 202#define MPI3MR_MAX_APP_XFER_SIZE (1 * 1024 * 1024) 203#define MPI3MR_MAX_APP_XFER_SEGMENTS 512 204/* 205 * 2048 sectors are for data buffers and additional 512 sectors for 206 * other buffers 207 */ 208#define MPI3MR_MAX_APP_XFER_SECTORS (2048 + 512) 209 210#define MPI3MR_WRITE_SAME_MAX_LEN_256_BLKS 256 211#define MPI3MR_WRITE_SAME_MAX_LEN_2048_BLKS 2048 212 213/** 214 * struct mpi3mr_nvme_pt_sge - Structure to store SGEs for NVMe 215 * Encapsulated commands. 216 * 217 * @base_addr: Physical address 218 * @length: SGE length 219 * @rsvd: Reserved 220 * @rsvd1: Reserved 221 * @sub_type: sgl sub type 222 * @type: sgl type 223 */ 224struct mpi3mr_nvme_pt_sge { 225 __le64 base_addr; 226 __le32 length; 227 u16 rsvd; 228 u8 rsvd1; 229 u8 sub_type:4; 230 u8 type:4; 231}; 232 233/** 234 * struct mpi3mr_buf_map - local structure to 235 * track kernel and user buffers associated with an BSG 236 * structure. 237 * 238 * @bsg_buf: BSG buffer virtual address 239 * @bsg_buf_len: BSG buffer length 240 * @kern_buf: Kernel buffer virtual address 241 * @kern_buf_len: Kernel buffer length 242 * @kern_buf_dma: Kernel buffer DMA address 243 * @data_dir: Data direction. 244 */ 245struct mpi3mr_buf_map { 246 void *bsg_buf; 247 u32 bsg_buf_len; 248 void *kern_buf; 249 u32 kern_buf_len; 250 dma_addr_t kern_buf_dma; 251 u8 data_dir; 252 u16 num_dma_desc; 253 struct dma_memory_desc *dma_desc; 254}; 255 256/* IOC State definitions */ 257enum mpi3mr_iocstate { 258 MRIOC_STATE_READY = 1, 259 MRIOC_STATE_RESET, 260 MRIOC_STATE_FAULT, 261 MRIOC_STATE_BECOMING_READY, 262 MRIOC_STATE_RESET_REQUESTED, 263 MRIOC_STATE_UNRECOVERABLE, 264}; 265 266/* Reset reason code definitions*/ 267enum mpi3mr_reset_reason { 268 MPI3MR_RESET_FROM_BRINGUP = 1, 269 MPI3MR_RESET_FROM_FAULT_WATCH = 2, 270 MPI3MR_RESET_FROM_APP = 3, 271 MPI3MR_RESET_FROM_EH_HOS = 4, 272 MPI3MR_RESET_FROM_TM_TIMEOUT = 5, 273 MPI3MR_RESET_FROM_APP_TIMEOUT = 6, 274 MPI3MR_RESET_FROM_MUR_FAILURE = 7, 275 MPI3MR_RESET_FROM_CTLR_CLEANUP = 8, 276 MPI3MR_RESET_FROM_CIACTIV_FAULT = 9, 277 MPI3MR_RESET_FROM_PE_TIMEOUT = 10, 278 MPI3MR_RESET_FROM_TSU_TIMEOUT = 11, 279 MPI3MR_RESET_FROM_DELREQQ_TIMEOUT = 12, 280 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT = 13, 281 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT = 14, 282 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT = 15, 283 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT = 16, 284 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT = 17, 285 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT = 18, 286 MPI3MR_RESET_FROM_EVTACK_TIMEOUT = 19, 287 MPI3MR_RESET_FROM_CIACTVRST_TIMER = 20, 288 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT = 21, 289 MPI3MR_RESET_FROM_PELABORT_TIMEOUT = 22, 290 MPI3MR_RESET_FROM_SYSFS = 23, 291 MPI3MR_RESET_FROM_SYSFS_TIMEOUT = 24, 292 MPI3MR_RESET_FROM_FIRMWARE = 27, 293 MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT = 29, 294 MPI3MR_RESET_FROM_SAS_TRANSPORT_TIMEOUT = 30, 295}; 296 297#define MPI3MR_RESET_REASON_OSTYPE_LINUX 1 298#define MPI3MR_RESET_REASON_OSTYPE_SHIFT 28 299#define MPI3MR_RESET_REASON_IOCNUM_SHIFT 20 300 301/* Queue type definitions */ 302enum queue_type { 303 MPI3MR_DEFAULT_QUEUE = 0, 304 MPI3MR_POLL_QUEUE, 305}; 306 307/** 308 * struct mpi3mr_compimg_ver - replica of component image 309 * version defined in mpi30_image.h in host endianness 310 * 311 */ 312struct mpi3mr_compimg_ver { 313 u16 build_num; 314 u16 cust_id; 315 u8 ph_minor; 316 u8 ph_major; 317 u8 gen_minor; 318 u8 gen_major; 319}; 320 321/** 322 * struct mpi3mr_ioc_facs - replica of component image version 323 * defined in mpi30_ioc.h in host endianness 324 * 325 */ 326struct mpi3mr_ioc_facts { 327 u32 ioc_capabilities; 328 struct mpi3mr_compimg_ver fw_ver; 329 u32 mpi_version; 330 u16 max_reqs; 331 u16 product_id; 332 u16 op_req_sz; 333 u16 reply_sz; 334 u16 exceptions; 335 u16 max_perids; 336 u16 max_pds; 337 u16 max_sasexpanders; 338 u32 max_data_length; 339 u16 max_sasinitiators; 340 u16 max_enclosures; 341 u16 max_pcie_switches; 342 u16 max_nvme; 343 u16 max_vds; 344 u16 max_hpds; 345 u16 max_advhpds; 346 u16 max_raid_pds; 347 u16 min_devhandle; 348 u16 max_devhandle; 349 u16 max_op_req_q; 350 u16 max_op_reply_q; 351 u16 shutdown_timeout; 352 u8 ioc_num; 353 u8 who_init; 354 u16 max_msix_vectors; 355 u8 personality; 356 u8 dma_mask; 357 u8 protocol_flags; 358 u8 sge_mod_mask; 359 u8 sge_mod_value; 360 u8 sge_mod_shift; 361 u8 max_dev_per_tg; 362 u16 max_io_throttle_group; 363 u16 io_throttle_data_length; 364 u16 io_throttle_low; 365 u16 io_throttle_high; 366 367}; 368 369/** 370 * struct segments - memory descriptor structure to store 371 * virtual and dma addresses for operational queue segments. 372 * 373 * @segment: virtual address 374 * @segment_dma: dma address 375 */ 376struct segments { 377 void *segment; 378 dma_addr_t segment_dma; 379}; 380 381/** 382 * struct op_req_qinfo - Operational Request Queue Information 383 * 384 * @ci: consumer index 385 * @pi: producer index 386 * @num_request: Maximum number of entries in the queue 387 * @qid: Queue Id starting from 1 388 * @reply_qid: Associated reply queue Id 389 * @num_segments: Number of discontiguous memory segments 390 * @segment_qd: Depth of each segments 391 * @q_lock: Concurrent queue access lock 392 * @q_segments: Segment descriptor pointer 393 * @q_segment_list: Segment list base virtual address 394 * @q_segment_list_dma: Segment list base DMA address 395 */ 396struct op_req_qinfo { 397 u16 ci; 398 u16 pi; 399 u16 num_requests; 400 u16 qid; 401 u16 reply_qid; 402 u16 num_segments; 403 u16 segment_qd; 404 spinlock_t q_lock; 405 struct segments *q_segments; 406 void *q_segment_list; 407 dma_addr_t q_segment_list_dma; 408}; 409 410/** 411 * struct op_reply_qinfo - Operational Reply Queue Information 412 * 413 * @ci: consumer index 414 * @qid: Queue Id starting from 1 415 * @num_replies: Maximum number of entries in the queue 416 * @num_segments: Number of discontiguous memory segments 417 * @segment_qd: Depth of each segments 418 * @q_segments: Segment descriptor pointer 419 * @q_segment_list: Segment list base virtual address 420 * @q_segment_list_dma: Segment list base DMA address 421 * @ephase: Expected phased identifier for the reply queue 422 * @pend_ios: Number of IOs pending in HW for this queue 423 * @enable_irq_poll: Flag to indicate polling is enabled 424 * @in_use: Queue is handled by poll/ISR 425 * @qtype: Type of queue (types defined in enum queue_type) 426 */ 427struct op_reply_qinfo { 428 u16 ci; 429 u16 qid; 430 u16 num_replies; 431 u16 num_segments; 432 u16 segment_qd; 433 struct segments *q_segments; 434 void *q_segment_list; 435 dma_addr_t q_segment_list_dma; 436 u8 ephase; 437 atomic_t pend_ios; 438 bool enable_irq_poll; 439 atomic_t in_use; 440 enum queue_type qtype; 441}; 442 443/** 444 * struct mpi3mr_intr_info - Interrupt cookie information 445 * 446 * @mrioc: Adapter instance reference 447 * @os_irq: irq number 448 * @msix_index: MSIx index 449 * @op_reply_q: Associated operational reply queue 450 * @name: Dev name for the irq claiming device 451 */ 452struct mpi3mr_intr_info { 453 struct mpi3mr_ioc *mrioc; 454 int os_irq; 455 u16 msix_index; 456 struct op_reply_qinfo *op_reply_q; 457 char name[MPI3MR_NAME_LENGTH]; 458}; 459 460/** 461 * struct mpi3mr_throttle_group_info - Throttle group info 462 * 463 * @io_divert: Flag indicates io divert is on or off for the TG 464 * @need_qd_reduction: Flag to indicate QD reduction is needed 465 * @qd_reduction: Queue Depth reduction in units of 10% 466 * @fw_qd: QueueDepth value reported by the firmware 467 * @modified_qd: Modified QueueDepth value due to throttling 468 * @id: Throttle Group ID. 469 * @high: High limit to turn on throttling in 512 byte blocks 470 * @low: Low limit to turn off throttling in 512 byte blocks 471 * @pend_large_data_sz: Counter to track pending large data 472 */ 473struct mpi3mr_throttle_group_info { 474 u8 io_divert; 475 u8 need_qd_reduction; 476 u8 qd_reduction; 477 u16 fw_qd; 478 u16 modified_qd; 479 u16 id; 480 u32 high; 481 u32 low; 482 atomic_t pend_large_data_sz; 483}; 484 485/* HBA port flags */ 486#define MPI3MR_HBA_PORT_FLAG_DIRTY 0x01 487 488/* IOCTL data transfer sge*/ 489#define MPI3MR_NUM_IOCTL_SGE 256 490#define MPI3MR_IOCTL_SGE_SIZE (8 * 1024) 491 492/** 493 * struct mpi3mr_hba_port - HBA's port information 494 * @port_id: Port number 495 * @flags: HBA port flags 496 */ 497struct mpi3mr_hba_port { 498 struct list_head list; 499 u8 port_id; 500 u8 flags; 501}; 502 503/** 504 * struct mpi3mr_sas_port - Internal SAS port information 505 * @port_list: List of ports belonging to a SAS node 506 * @num_phys: Number of phys associated with port 507 * @marked_responding: used while refresing the sas ports 508 * @lowest_phy: lowest phy ID of current sas port 509 * @phy_mask: phy_mask of current sas port 510 * @hba_port: HBA port entry 511 * @remote_identify: Attached device identification 512 * @rphy: SAS transport layer rphy object 513 * @port: SAS transport layer port object 514 * @phy_list: mpi3mr_sas_phy objects belonging to this port 515 */ 516struct mpi3mr_sas_port { 517 struct list_head port_list; 518 u8 num_phys; 519 u8 marked_responding; 520 int lowest_phy; 521 u64 phy_mask; 522 struct mpi3mr_hba_port *hba_port; 523 struct sas_identify remote_identify; 524 struct sas_rphy *rphy; 525 struct sas_port *port; 526 struct list_head phy_list; 527}; 528 529/** 530 * struct mpi3mr_sas_phy - Internal SAS Phy information 531 * @port_siblings: List of phys belonging to a port 532 * @identify: Phy identification 533 * @remote_identify: Attached device identification 534 * @phy: SAS transport layer Phy object 535 * @phy_id: Unique phy id within a port 536 * @handle: Firmware device handle for this phy 537 * @attached_handle: Firmware device handle for attached device 538 * @phy_belongs_to_port: Flag to indicate phy belongs to port 539 @hba_port: HBA port entry 540 */ 541struct mpi3mr_sas_phy { 542 struct list_head port_siblings; 543 struct sas_identify identify; 544 struct sas_identify remote_identify; 545 struct sas_phy *phy; 546 u8 phy_id; 547 u16 handle; 548 u16 attached_handle; 549 u8 phy_belongs_to_port; 550 struct mpi3mr_hba_port *hba_port; 551}; 552 553/** 554 * struct mpi3mr_sas_node - SAS host/expander information 555 * @list: List of sas nodes in a controller 556 * @parent_dev: Parent device class 557 * @num_phys: Number phys belonging to sas_node 558 * @sas_address: SAS address of sas_node 559 * @handle: Firmware device handle for this sas_host/expander 560 * @sas_address_parent: SAS address of parent expander or host 561 * @enclosure_handle: Firmware handle of enclosure of this node 562 * @device_info: Capabilities of this sas_host/expander 563 * @non_responding: used to refresh the expander devices during reset 564 * @host_node: Flag to indicate this is a host_node 565 * @hba_port: HBA port entry 566 * @phy: A list of phys that make up this sas_host/expander 567 * @sas_port_list: List of internal ports of this node 568 * @rphy: sas_rphy object of this expander node 569 */ 570struct mpi3mr_sas_node { 571 struct list_head list; 572 struct device *parent_dev; 573 u8 num_phys; 574 u64 sas_address; 575 u16 handle; 576 u64 sas_address_parent; 577 u16 enclosure_handle; 578 u64 enclosure_logical_id; 579 u8 non_responding; 580 u8 host_node; 581 struct mpi3mr_hba_port *hba_port; 582 struct mpi3mr_sas_phy *phy; 583 struct list_head sas_port_list; 584 struct sas_rphy *rphy; 585}; 586 587/** 588 * struct mpi3mr_enclosure_node - enclosure information 589 * @list: List of enclosures 590 * @pg0: Enclosure page 0; 591 */ 592struct mpi3mr_enclosure_node { 593 struct list_head list; 594 struct mpi3_enclosure_page0 pg0; 595}; 596 597/** 598 * struct tgt_dev_sas_sata - SAS/SATA device specific 599 * information cached from firmware given data 600 * 601 * @sas_address: World wide unique SAS address 602 * @sas_address_parent: Sas address of parent expander or host 603 * @dev_info: Device information bits 604 * @phy_id: Phy identifier provided in device page 0 605 * @attached_phy_id: Attached phy identifier provided in device page 0 606 * @sas_transport_attached: Is this device exposed to transport 607 * @pend_sas_rphy_add: Flag to check device is in process of add 608 * @hba_port: HBA port entry 609 * @rphy: SAS transport layer rphy object 610 */ 611struct tgt_dev_sas_sata { 612 u64 sas_address; 613 u64 sas_address_parent; 614 u16 dev_info; 615 u8 phy_id; 616 u8 attached_phy_id; 617 u8 sas_transport_attached; 618 u8 pend_sas_rphy_add; 619 struct mpi3mr_hba_port *hba_port; 620 struct sas_rphy *rphy; 621}; 622 623/** 624 * struct tgt_dev_pcie - PCIe device specific information cached 625 * from firmware given data 626 * 627 * @mdts: Maximum data transfer size 628 * @capb: Device capabilities 629 * @pgsz: Device page size 630 * @abort_to: Timeout for abort TM 631 * @reset_to: Timeout for Target/LUN reset TM 632 * @dev_info: Device information bits 633 */ 634struct tgt_dev_pcie { 635 u32 mdts; 636 u16 capb; 637 u8 pgsz; 638 u8 abort_to; 639 u8 reset_to; 640 u16 dev_info; 641}; 642 643/** 644 * struct tgt_dev_vd - virtual device specific information 645 * cached from firmware given data 646 * 647 * @state: State of the VD 648 * @tg_qd_reduction: Queue Depth reduction in units of 10% 649 * @tg_id: VDs throttle group ID 650 * @high: High limit to turn on throttling in 512 byte blocks 651 * @low: Low limit to turn off throttling in 512 byte blocks 652 * @tg: Pointer to throttle group info 653 */ 654struct tgt_dev_vd { 655 u8 state; 656 u8 tg_qd_reduction; 657 u16 tg_id; 658 u32 tg_high; 659 u32 tg_low; 660 struct mpi3mr_throttle_group_info *tg; 661}; 662 663 664/** 665 * union _form_spec_inf - union of device specific information 666 */ 667union _form_spec_inf { 668 struct tgt_dev_sas_sata sas_sata_inf; 669 struct tgt_dev_pcie pcie_inf; 670 struct tgt_dev_vd vd_inf; 671}; 672 673enum mpi3mr_dev_state { 674 MPI3MR_DEV_CREATED = 1, 675 MPI3MR_DEV_REMOVE_HS_STARTED = 2, 676 MPI3MR_DEV_DELETED = 3, 677}; 678 679/** 680 * struct mpi3mr_tgt_dev - target device data structure 681 * 682 * @list: List pointer 683 * @starget: Scsi_target pointer 684 * @dev_handle: FW device handle 685 * @parent_handle: FW parent device handle 686 * @slot: Slot number 687 * @encl_handle: FW enclosure handle 688 * @perst_id: FW assigned Persistent ID 689 * @devpg0_flag: Device Page0 flag 690 * @dev_type: SAS/SATA/PCIE device type 691 * @is_hidden: Should be exposed to upper layers or not 692 * @host_exposed: Already exposed to host or not 693 * @io_unit_port: IO Unit port ID 694 * @non_stl: Is this device not to be attached with SAS TL 695 * @io_throttle_enabled: I/O throttling needed or not 696 * @wslen: Write same max length 697 * @q_depth: Device specific Queue Depth 698 * @wwid: World wide ID 699 * @enclosure_logical_id: Enclosure logical identifier 700 * @dev_spec: Device type specific information 701 * @ref_count: Reference count 702 * @state: device state 703 */ 704struct mpi3mr_tgt_dev { 705 struct list_head list; 706 struct scsi_target *starget; 707 u16 dev_handle; 708 u16 parent_handle; 709 u16 slot; 710 u16 encl_handle; 711 u16 perst_id; 712 u16 devpg0_flag; 713 u8 dev_type; 714 u8 is_hidden; 715 u8 host_exposed; 716 u8 io_unit_port; 717 u8 non_stl; 718 u8 io_throttle_enabled; 719 u16 wslen; 720 u16 q_depth; 721 u64 wwid; 722 u64 enclosure_logical_id; 723 union _form_spec_inf dev_spec; 724 struct kref ref_count; 725 enum mpi3mr_dev_state state; 726}; 727 728/** 729 * mpi3mr_tgtdev_get - k reference incrementor 730 * @s: Target device reference 731 * 732 * Increment target device reference count. 733 */ 734static inline void mpi3mr_tgtdev_get(struct mpi3mr_tgt_dev *s) 735{ 736 kref_get(&s->ref_count); 737} 738 739/** 740 * mpi3mr_free_tgtdev - target device memory dealloctor 741 * @r: k reference pointer of the target device 742 * 743 * Free target device memory when no reference. 744 */ 745static inline void mpi3mr_free_tgtdev(struct kref *r) 746{ 747 kfree(container_of(r, struct mpi3mr_tgt_dev, ref_count)); 748} 749 750/** 751 * mpi3mr_tgtdev_put - k reference decrementor 752 * @s: Target device reference 753 * 754 * Decrement target device reference count. 755 */ 756static inline void mpi3mr_tgtdev_put(struct mpi3mr_tgt_dev *s) 757{ 758 kref_put(&s->ref_count, mpi3mr_free_tgtdev); 759} 760 761 762/** 763 * struct mpi3mr_stgt_priv_data - SCSI target private structure 764 * 765 * @starget: Scsi_target pointer 766 * @dev_handle: FW device handle 767 * @perst_id: FW assigned Persistent ID 768 * @num_luns: Number of Logical Units 769 * @block_io: I/O blocked to the device or not 770 * @dev_removed: Device removed in the Firmware 771 * @dev_removedelay: Device is waiting to be removed in FW 772 * @dev_type: Device type 773 * @dev_nvme_dif: Device is NVMe DIF enabled 774 * @wslen: Write same max length 775 * @io_throttle_enabled: I/O throttling needed or not 776 * @io_divert: Flag indicates io divert is on or off for the dev 777 * @throttle_group: Pointer to throttle group info 778 * @tgt_dev: Internal target device pointer 779 * @pend_count: Counter to track pending I/Os during error 780 * handling 781 */ 782struct mpi3mr_stgt_priv_data { 783 struct scsi_target *starget; 784 u16 dev_handle; 785 u16 perst_id; 786 u32 num_luns; 787 atomic_t block_io; 788 u8 dev_removed; 789 u8 dev_removedelay; 790 u8 dev_type; 791 u8 dev_nvme_dif; 792 u16 wslen; 793 u8 io_throttle_enabled; 794 u8 io_divert; 795 struct mpi3mr_throttle_group_info *throttle_group; 796 struct mpi3mr_tgt_dev *tgt_dev; 797 u32 pend_count; 798}; 799 800/** 801 * struct mpi3mr_stgt_priv_data - SCSI device private structure 802 * 803 * @tgt_priv_data: Scsi_target private data pointer 804 * @lun_id: LUN ID of the device 805 * @ncq_prio_enable: NCQ priority enable for SATA device 806 * @pend_count: Counter to track pending I/Os during error 807 * handling 808 * @wslen: Write same max length 809 */ 810struct mpi3mr_sdev_priv_data { 811 struct mpi3mr_stgt_priv_data *tgt_priv_data; 812 u32 lun_id; 813 u8 ncq_prio_enable; 814 u32 pend_count; 815 u16 wslen; 816}; 817 818/** 819 * struct mpi3mr_drv_cmd - Internal command tracker 820 * 821 * @mutex: Command mutex 822 * @done: Completeor for wakeup 823 * @reply: Firmware reply for internal commands 824 * @sensebuf: Sensebuf for SCSI IO commands 825 * @iou_rc: IO Unit control reason code 826 * @state: Command State 827 * @dev_handle: Firmware handle for device specific commands 828 * @ioc_status: IOC status from the firmware 829 * @ioc_loginfo:IOC log info from the firmware 830 * @is_waiting: Is the command issued in block mode 831 * @is_sense: Is Sense data present 832 * @retry_count: Retry count for retriable commands 833 * @host_tag: Host tag used by the command 834 * @callback: Callback for non blocking commands 835 */ 836struct mpi3mr_drv_cmd { 837 struct mutex mutex; 838 struct completion done; 839 void *reply; 840 u8 *sensebuf; 841 u8 iou_rc; 842 u16 state; 843 u16 dev_handle; 844 u16 ioc_status; 845 u32 ioc_loginfo; 846 u8 is_waiting; 847 u8 is_sense; 848 u8 retry_count; 849 u16 host_tag; 850 851 void (*callback)(struct mpi3mr_ioc *mrioc, 852 struct mpi3mr_drv_cmd *drv_cmd); 853}; 854 855/** 856 * struct dma_memory_desc - memory descriptor structure to store 857 * virtual address, dma address and size for any generic dma 858 * memory allocations in the driver. 859 * 860 * @size: buffer size 861 * @addr: virtual address 862 * @dma_addr: dma address 863 */ 864struct dma_memory_desc { 865 u32 size; 866 void *addr; 867 dma_addr_t dma_addr; 868}; 869 870 871/** 872 * struct chain_element - memory descriptor structure to store 873 * virtual and dma addresses for chain elements. 874 * 875 * @addr: virtual address 876 * @dma_addr: dma address 877 */ 878struct chain_element { 879 void *addr; 880 dma_addr_t dma_addr; 881}; 882 883/** 884 * struct scmd_priv - SCSI command private data 885 * 886 * @host_tag: Host tag specific to operational queue 887 * @in_lld_scope: Command in LLD scope or not 888 * @meta_sg_valid: DIX command with meta data SGL or not 889 * @scmd: SCSI Command pointer 890 * @req_q_idx: Operational request queue index 891 * @chain_idx: Chain frame index 892 * @meta_chain_idx: Chain frame index of meta data SGL 893 * @mpi3mr_scsiio_req: MPI SCSI IO request 894 */ 895struct scmd_priv { 896 u16 host_tag; 897 u8 in_lld_scope; 898 u8 meta_sg_valid; 899 struct scsi_cmnd *scmd; 900 u16 req_q_idx; 901 int chain_idx; 902 int meta_chain_idx; 903 u8 mpi3mr_scsiio_req[MPI3MR_ADMIN_REQ_FRAME_SZ]; 904}; 905 906/** 907 * struct mpi3mr_ioc - Adapter anchor structure stored in shost 908 * private data 909 * 910 * @list: List pointer 911 * @pdev: PCI device pointer 912 * @shost: Scsi_Host pointer 913 * @id: Controller ID 914 * @cpu_count: Number of online CPUs 915 * @irqpoll_sleep: usleep unit used in threaded isr irqpoll 916 * @name: Controller ASCII name 917 * @driver_name: Driver ASCII name 918 * @sysif_regs: System interface registers virtual address 919 * @sysif_regs_phys: System interface registers physical address 920 * @bars: PCI BARS 921 * @dma_mask: DMA mask 922 * @msix_count: Number of MSIX vectors used 923 * @intr_enabled: Is interrupts enabled 924 * @num_admin_req: Number of admin requests 925 * @admin_req_q_sz: Admin request queue size 926 * @admin_req_pi: Admin request queue producer index 927 * @admin_req_ci: Admin request queue consumer index 928 * @admin_req_base: Admin request queue base virtual address 929 * @admin_req_dma: Admin request queue base dma address 930 * @admin_req_lock: Admin queue access lock 931 * @num_admin_replies: Number of admin replies 932 * @admin_reply_q_sz: Admin reply queue size 933 * @admin_reply_ci: Admin reply queue consumer index 934 * @admin_reply_ephase:Admin reply queue expected phase 935 * @admin_reply_base: Admin reply queue base virtual address 936 * @admin_reply_dma: Admin reply queue base dma address 937 * @admin_reply_q_in_use: Queue is handled by poll/ISR 938 * @ready_timeout: Controller ready timeout 939 * @intr_info: Interrupt cookie pointer 940 * @intr_info_count: Number of interrupt cookies 941 * @is_intr_info_set: Flag to indicate intr info is setup 942 * @num_queues: Number of operational queues 943 * @num_op_req_q: Number of operational request queues 944 * @req_qinfo: Operational request queue info pointer 945 * @num_op_reply_q: Number of operational reply queues 946 * @op_reply_qinfo: Operational reply queue info pointer 947 * @init_cmds: Command tracker for initialization commands 948 * @cfg_cmds: Command tracker for configuration requests 949 * @facts: Cached IOC facts data 950 * @op_reply_desc_sz: Operational reply descriptor size 951 * @num_reply_bufs: Number of reply buffers allocated 952 * @reply_buf_pool: Reply buffer pool 953 * @reply_buf: Reply buffer base virtual address 954 * @reply_buf_dma: Reply buffer DMA address 955 * @reply_buf_dma_max_address: Reply DMA address max limit 956 * @reply_free_qsz: Reply free queue size 957 * @reply_free_q_pool: Reply free queue pool 958 * @reply_free_q: Reply free queue base virtual address 959 * @reply_free_q_dma: Reply free queue base DMA address 960 * @reply_free_queue_lock: Reply free queue lock 961 * @reply_free_queue_host_index: Reply free queue host index 962 * @num_sense_bufs: Number of sense buffers 963 * @sense_buf_pool: Sense buffer pool 964 * @sense_buf: Sense buffer base virtual address 965 * @sense_buf_dma: Sense buffer base DMA address 966 * @sense_buf_q_sz: Sense buffer queue size 967 * @sense_buf_q_pool: Sense buffer queue pool 968 * @sense_buf_q: Sense buffer queue virtual address 969 * @sense_buf_q_dma: Sense buffer queue DMA address 970 * @sbq_lock: Sense buffer queue lock 971 * @sbq_host_index: Sense buffer queuehost index 972 * @event_masks: Event mask bitmap 973 * @fwevt_worker_name: Firmware event worker thread name 974 * @fwevt_worker_thread: Firmware event worker thread 975 * @fwevt_lock: Firmware event lock 976 * @fwevt_list: Firmware event list 977 * @watchdog_work_q_name: Fault watchdog worker thread name 978 * @watchdog_work_q: Fault watchdog worker thread 979 * @watchdog_work: Fault watchdog work 980 * @watchdog_lock: Fault watchdog lock 981 * @is_driver_loading: Is driver still loading 982 * @scan_started: Async scan started 983 * @scan_failed: Asycn scan failed 984 * @stop_drv_processing: Stop all command processing 985 * @device_refresh_on: Don't process the events until devices are refreshed 986 * @max_host_ios: Maximum host I/O count 987 * @max_sgl_entries: Max SGL entries per I/O 988 * @chain_buf_count: Chain buffer count 989 * @chain_buf_pool: Chain buffer pool 990 * @chain_sgl_list: Chain SGL list 991 * @chain_bitmap: Chain buffer allocator bitmap 992 * @chain_buf_lock: Chain buffer list lock 993 * @bsg_cmds: Command tracker for BSG command 994 * @host_tm_cmds: Command tracker for task management commands 995 * @dev_rmhs_cmds: Command tracker for device removal commands 996 * @evtack_cmds: Command tracker for event ack commands 997 * @devrem_bitmap: Device removal bitmap 998 * @dev_handle_bitmap_bits: Number of bits in device handle bitmap 999 * @removepend_bitmap: Remove pending bitmap 1000 * @delayed_rmhs_list: Delayed device removal list 1001 * @evtack_cmds_bitmap: Event Ack bitmap 1002 * @delayed_evtack_cmds_list: Delayed event acknowledgment list 1003 * @ts_update_counter: Timestamp update counter 1004 * @reset_in_progress: Reset in progress flag 1005 * @unrecoverable: Controller unrecoverable flag 1006 * @prev_reset_result: Result of previous reset 1007 * @reset_mutex: Controller reset mutex 1008 * @reset_waitq: Controller reset wait queue 1009 * @prepare_for_reset: Prepare for reset event received 1010 * @prepare_for_reset_timeout_counter: Prepare for reset timeout 1011 * @prp_list_virt: NVMe encapsulated PRP list virtual base 1012 * @prp_list_dma: NVMe encapsulated PRP list DMA 1013 * @prp_sz: NVME encapsulated PRP list size 1014 * @diagsave_timeout: Diagnostic information save timeout 1015 * @logging_level: Controller debug logging level 1016 * @flush_io_count: I/O count to flush after reset 1017 * @current_event: Firmware event currently in process 1018 * @driver_info: Driver, Kernel, OS information to firmware 1019 * @change_count: Topology change count 1020 * @pel_enabled: Persistent Event Log(PEL) enabled or not 1021 * @pel_abort_requested: PEL abort is requested or not 1022 * @pel_class: PEL Class identifier 1023 * @pel_locale: PEL Locale identifier 1024 * @pel_cmds: Command tracker for PEL wait command 1025 * @pel_abort_cmd: Command tracker for PEL abort command 1026 * @pel_newest_seqnum: Newest PEL sequenece number 1027 * @pel_seqnum_virt: PEL sequence number virtual address 1028 * @pel_seqnum_dma: PEL sequence number DMA address 1029 * @pel_seqnum_sz: PEL sequenece number size 1030 * @op_reply_q_offset: Operational reply queue offset with MSIx 1031 * @default_qcount: Total Default queues 1032 * @active_poll_qcount: Currently active poll queue count 1033 * @requested_poll_qcount: User requested poll queue count 1034 * @bsg_dev: BSG device structure 1035 * @bsg_queue: Request queue for BSG device 1036 * @stop_bsgs: Stop BSG request flag 1037 * @logdata_buf: Circular buffer to store log data entries 1038 * @logdata_buf_idx: Index of entry in buffer to store 1039 * @logdata_entry_sz: log data entry size 1040 * @pend_large_data_sz: Counter to track pending large data 1041 * @io_throttle_data_length: I/O size to track in 512b blocks 1042 * @io_throttle_high: I/O size to start throttle in 512b blocks 1043 * @io_throttle_low: I/O size to stop throttle in 512b blocks 1044 * @num_io_throttle_group: Maximum number of throttle groups 1045 * @throttle_groups: Pointer to throttle group info structures 1046 * @cfg_page: Default memory for configuration pages 1047 * @cfg_page_dma: Configuration page DMA address 1048 * @cfg_page_sz: Default configuration page memory size 1049 * @sas_transport_enabled: SAS transport enabled or not 1050 * @scsi_device_channel: Channel ID for SCSI devices 1051 * @transport_cmds: Command tracker for SAS transport commands 1052 * @sas_hba: SAS node for the controller 1053 * @sas_expander_list: SAS node list of expanders 1054 * @sas_node_lock: Lock to protect SAS node list 1055 * @hba_port_table_list: List of HBA Ports 1056 * @enclosure_list: List of Enclosure objects 1057 * @ioctl_dma_pool: DMA pool for IOCTL data buffers 1058 * @ioctl_sge: DMA buffer descriptors for IOCTL data 1059 * @ioctl_chain_sge: DMA buffer descriptor for IOCTL chain 1060 * @ioctl_resp_sge: DMA buffer descriptor for Mgmt cmd response 1061 * @ioctl_sges_allocated: Flag for IOCTL SGEs allocated or not 1062 */ 1063struct mpi3mr_ioc { 1064 struct list_head list; 1065 struct pci_dev *pdev; 1066 struct Scsi_Host *shost; 1067 u8 id; 1068 int cpu_count; 1069 bool enable_segqueue; 1070 u32 irqpoll_sleep; 1071 1072 char name[MPI3MR_NAME_LENGTH]; 1073 char driver_name[MPI3MR_NAME_LENGTH]; 1074 1075 volatile struct mpi3_sysif_registers __iomem *sysif_regs; 1076 resource_size_t sysif_regs_phys; 1077 int bars; 1078 u64 dma_mask; 1079 1080 u16 msix_count; 1081 u8 intr_enabled; 1082 1083 u16 num_admin_req; 1084 u32 admin_req_q_sz; 1085 u16 admin_req_pi; 1086 u16 admin_req_ci; 1087 void *admin_req_base; 1088 dma_addr_t admin_req_dma; 1089 spinlock_t admin_req_lock; 1090 1091 u16 num_admin_replies; 1092 u32 admin_reply_q_sz; 1093 u16 admin_reply_ci; 1094 u8 admin_reply_ephase; 1095 void *admin_reply_base; 1096 dma_addr_t admin_reply_dma; 1097 atomic_t admin_reply_q_in_use; 1098 1099 u32 ready_timeout; 1100 1101 struct mpi3mr_intr_info *intr_info; 1102 u16 intr_info_count; 1103 bool is_intr_info_set; 1104 1105 u16 num_queues; 1106 u16 num_op_req_q; 1107 struct op_req_qinfo *req_qinfo; 1108 1109 u16 num_op_reply_q; 1110 struct op_reply_qinfo *op_reply_qinfo; 1111 1112 struct mpi3mr_drv_cmd init_cmds; 1113 struct mpi3mr_drv_cmd cfg_cmds; 1114 struct mpi3mr_ioc_facts facts; 1115 u16 op_reply_desc_sz; 1116 1117 u32 num_reply_bufs; 1118 struct dma_pool *reply_buf_pool; 1119 u8 *reply_buf; 1120 dma_addr_t reply_buf_dma; 1121 dma_addr_t reply_buf_dma_max_address; 1122 1123 u16 reply_free_qsz; 1124 u16 reply_sz; 1125 struct dma_pool *reply_free_q_pool; 1126 __le64 *reply_free_q; 1127 dma_addr_t reply_free_q_dma; 1128 spinlock_t reply_free_queue_lock; 1129 u32 reply_free_queue_host_index; 1130 1131 u32 num_sense_bufs; 1132 struct dma_pool *sense_buf_pool; 1133 u8 *sense_buf; 1134 dma_addr_t sense_buf_dma; 1135 1136 u16 sense_buf_q_sz; 1137 struct dma_pool *sense_buf_q_pool; 1138 __le64 *sense_buf_q; 1139 dma_addr_t sense_buf_q_dma; 1140 spinlock_t sbq_lock; 1141 u32 sbq_host_index; 1142 u32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS]; 1143 1144 char fwevt_worker_name[MPI3MR_NAME_LENGTH]; 1145 struct workqueue_struct *fwevt_worker_thread; 1146 spinlock_t fwevt_lock; 1147 struct list_head fwevt_list; 1148 1149 char watchdog_work_q_name[50]; 1150 struct workqueue_struct *watchdog_work_q; 1151 struct delayed_work watchdog_work; 1152 spinlock_t watchdog_lock; 1153 1154 u8 is_driver_loading; 1155 u8 scan_started; 1156 u16 scan_failed; 1157 u8 stop_drv_processing; 1158 u8 device_refresh_on; 1159 1160 u16 max_host_ios; 1161 spinlock_t tgtdev_lock; 1162 struct list_head tgtdev_list; 1163 u16 max_sgl_entries; 1164 1165 u32 chain_buf_count; 1166 struct dma_pool *chain_buf_pool; 1167 struct chain_element *chain_sgl_list; 1168 unsigned long *chain_bitmap; 1169 spinlock_t chain_buf_lock; 1170 1171 struct mpi3mr_drv_cmd bsg_cmds; 1172 struct mpi3mr_drv_cmd host_tm_cmds; 1173 struct mpi3mr_drv_cmd dev_rmhs_cmds[MPI3MR_NUM_DEVRMCMD]; 1174 struct mpi3mr_drv_cmd evtack_cmds[MPI3MR_NUM_EVTACKCMD]; 1175 unsigned long *devrem_bitmap; 1176 u16 dev_handle_bitmap_bits; 1177 unsigned long *removepend_bitmap; 1178 struct list_head delayed_rmhs_list; 1179 unsigned long *evtack_cmds_bitmap; 1180 struct list_head delayed_evtack_cmds_list; 1181 1182 u32 ts_update_counter; 1183 u8 reset_in_progress; 1184 u8 unrecoverable; 1185 int prev_reset_result; 1186 struct mutex reset_mutex; 1187 wait_queue_head_t reset_waitq; 1188 1189 u8 prepare_for_reset; 1190 u16 prepare_for_reset_timeout_counter; 1191 1192 void *prp_list_virt; 1193 dma_addr_t prp_list_dma; 1194 u32 prp_sz; 1195 1196 u16 diagsave_timeout; 1197 int logging_level; 1198 u16 flush_io_count; 1199 1200 struct mpi3mr_fwevt *current_event; 1201 struct mpi3_driver_info_layout driver_info; 1202 u16 change_count; 1203 1204 u8 pel_enabled; 1205 u8 pel_abort_requested; 1206 u8 pel_class; 1207 u16 pel_locale; 1208 struct mpi3mr_drv_cmd pel_cmds; 1209 struct mpi3mr_drv_cmd pel_abort_cmd; 1210 1211 u32 pel_newest_seqnum; 1212 void *pel_seqnum_virt; 1213 dma_addr_t pel_seqnum_dma; 1214 u32 pel_seqnum_sz; 1215 1216 u16 op_reply_q_offset; 1217 u16 default_qcount; 1218 u16 active_poll_qcount; 1219 u16 requested_poll_qcount; 1220 1221 struct device bsg_dev; 1222 struct request_queue *bsg_queue; 1223 u8 stop_bsgs; 1224 u8 *logdata_buf; 1225 u16 logdata_buf_idx; 1226 u16 logdata_entry_sz; 1227 1228 atomic_t pend_large_data_sz; 1229 u32 io_throttle_data_length; 1230 u32 io_throttle_high; 1231 u32 io_throttle_low; 1232 u16 num_io_throttle_group; 1233 struct mpi3mr_throttle_group_info *throttle_groups; 1234 1235 void *cfg_page; 1236 dma_addr_t cfg_page_dma; 1237 u16 cfg_page_sz; 1238 1239 u8 sas_transport_enabled; 1240 u8 scsi_device_channel; 1241 struct mpi3mr_drv_cmd transport_cmds; 1242 struct mpi3mr_sas_node sas_hba; 1243 struct list_head sas_expander_list; 1244 spinlock_t sas_node_lock; 1245 struct list_head hba_port_table_list; 1246 struct list_head enclosure_list; 1247 1248 struct dma_pool *ioctl_dma_pool; 1249 struct dma_memory_desc ioctl_sge[MPI3MR_NUM_IOCTL_SGE]; 1250 struct dma_memory_desc ioctl_chain_sge; 1251 struct dma_memory_desc ioctl_resp_sge; 1252 bool ioctl_sges_allocated; 1253}; 1254 1255/** 1256 * struct mpi3mr_fwevt - Firmware event structure. 1257 * 1258 * @list: list head 1259 * @work: Work structure 1260 * @mrioc: Adapter instance reference 1261 * @event_id: MPI3 firmware event ID 1262 * @send_ack: Event acknowledgment required or not 1263 * @process_evt: Bottomhalf processing required or not 1264 * @evt_ctx: Event context to send in Ack 1265 * @event_data_size: size of the event data in bytes 1266 * @pending_at_sml: waiting for device add/remove API to complete 1267 * @discard: discard this event 1268 * @ref_count: kref count 1269 * @event_data: Actual MPI3 event data 1270 */ 1271struct mpi3mr_fwevt { 1272 struct list_head list; 1273 struct work_struct work; 1274 struct mpi3mr_ioc *mrioc; 1275 u16 event_id; 1276 bool send_ack; 1277 bool process_evt; 1278 u32 evt_ctx; 1279 u16 event_data_size; 1280 bool pending_at_sml; 1281 bool discard; 1282 struct kref ref_count; 1283 char event_data[] __aligned(4); 1284}; 1285 1286 1287/** 1288 * struct delayed_dev_rmhs_node - Delayed device removal node 1289 * 1290 * @list: list head 1291 * @handle: Device handle 1292 * @iou_rc: IO Unit Control Reason Code 1293 */ 1294struct delayed_dev_rmhs_node { 1295 struct list_head list; 1296 u16 handle; 1297 u8 iou_rc; 1298}; 1299 1300/** 1301 * struct delayed_evt_ack_node - Delayed event ack node 1302 * @list: list head 1303 * @event: MPI3 event ID 1304 * @event_ctx: event context 1305 */ 1306struct delayed_evt_ack_node { 1307 struct list_head list; 1308 u8 event; 1309 u32 event_ctx; 1310}; 1311 1312int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc); 1313void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc); 1314int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc); 1315int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume); 1316void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc); 1317int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async); 1318int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req, 1319u16 admin_req_sz, u8 ignore_reset); 1320int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc, 1321 struct op_req_qinfo *opreqq, u8 *req); 1322void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length, 1323 dma_addr_t dma_addr); 1324void mpi3mr_build_zero_len_sge(void *paddr); 1325void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc, 1326 dma_addr_t phys_addr); 1327void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc, 1328 dma_addr_t phys_addr); 1329void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc, 1330 u64 sense_buf_dma); 1331 1332void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc); 1333void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc); 1334void mpi3mr_os_handle_events(struct mpi3mr_ioc *mrioc, 1335 struct mpi3_event_notification_reply *event_reply); 1336void mpi3mr_process_op_reply_desc(struct mpi3mr_ioc *mrioc, 1337 struct mpi3_default_reply_descriptor *reply_desc, 1338 u64 *reply_dma, u16 qidx); 1339void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc); 1340void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc); 1341 1342int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc, 1343 u16 reset_reason, u8 snapdump); 1344void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc); 1345void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc); 1346 1347enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc); 1348int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event, 1349 u32 event_ctx); 1350 1351void mpi3mr_wait_for_host_io(struct mpi3mr_ioc *mrioc, u32 timeout); 1352void mpi3mr_cleanup_fwevt_list(struct mpi3mr_ioc *mrioc); 1353void mpi3mr_flush_host_io(struct mpi3mr_ioc *mrioc); 1354void mpi3mr_invalidate_devhandles(struct mpi3mr_ioc *mrioc); 1355void mpi3mr_flush_delayed_cmd_lists(struct mpi3mr_ioc *mrioc); 1356void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code); 1357void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc); 1358void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code); 1359int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc, 1360 struct op_reply_qinfo *op_reply_q); 1361int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num); 1362void mpi3mr_bsg_init(struct mpi3mr_ioc *mrioc); 1363void mpi3mr_bsg_exit(struct mpi3mr_ioc *mrioc); 1364int mpi3mr_issue_tm(struct mpi3mr_ioc *mrioc, u8 tm_type, 1365 u16 handle, uint lun, u16 htag, ulong timeout, 1366 struct mpi3mr_drv_cmd *drv_cmd, 1367 u8 *resp_code, struct scsi_cmnd *scmd); 1368struct mpi3mr_tgt_dev *mpi3mr_get_tgtdev_by_handle( 1369 struct mpi3mr_ioc *mrioc, u16 handle); 1370void mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc *mrioc, 1371 struct mpi3mr_drv_cmd *drv_cmd); 1372int mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc *mrioc, 1373 struct mpi3mr_drv_cmd *drv_cmd); 1374void mpi3mr_app_save_logdata(struct mpi3mr_ioc *mrioc, char *event_data, 1375 u16 event_data_size); 1376struct mpi3mr_enclosure_node *mpi3mr_enclosure_find_by_handle( 1377 struct mpi3mr_ioc *mrioc, u16 handle); 1378extern const struct attribute_group *mpi3mr_host_groups[]; 1379extern const struct attribute_group *mpi3mr_dev_groups[]; 1380 1381extern struct sas_function_template mpi3mr_transport_functions; 1382extern struct scsi_transport_template *mpi3mr_transport_template; 1383 1384int mpi3mr_cfg_get_dev_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1385 struct mpi3_device_page0 *dev_pg0, u16 pg_sz, u32 form, u32 form_spec); 1386int mpi3mr_cfg_get_sas_phy_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1387 struct mpi3_sas_phy_page0 *phy_pg0, u16 pg_sz, u32 form, 1388 u32 form_spec); 1389int mpi3mr_cfg_get_sas_phy_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1390 struct mpi3_sas_phy_page1 *phy_pg1, u16 pg_sz, u32 form, 1391 u32 form_spec); 1392int mpi3mr_cfg_get_sas_exp_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1393 struct mpi3_sas_expander_page0 *exp_pg0, u16 pg_sz, u32 form, 1394 u32 form_spec); 1395int mpi3mr_cfg_get_sas_exp_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1396 struct mpi3_sas_expander_page1 *exp_pg1, u16 pg_sz, u32 form, 1397 u32 form_spec); 1398int mpi3mr_cfg_get_enclosure_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status, 1399 struct mpi3_enclosure_page0 *encl_pg0, u16 pg_sz, u32 form, 1400 u32 form_spec); 1401int mpi3mr_cfg_get_sas_io_unit_pg0(struct mpi3mr_ioc *mrioc, 1402 struct mpi3_sas_io_unit_page0 *sas_io_unit_pg0, u16 pg_sz); 1403int mpi3mr_cfg_get_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc, 1404 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz); 1405int mpi3mr_cfg_set_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc, 1406 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz); 1407int mpi3mr_cfg_get_driver_pg1(struct mpi3mr_ioc *mrioc, 1408 struct mpi3_driver_page1 *driver_pg1, u16 pg_sz); 1409 1410u8 mpi3mr_is_expander_device(u16 device_info); 1411int mpi3mr_expander_add(struct mpi3mr_ioc *mrioc, u16 handle); 1412void mpi3mr_expander_remove(struct mpi3mr_ioc *mrioc, u64 sas_address, 1413 struct mpi3mr_hba_port *hba_port); 1414struct mpi3mr_sas_node *__mpi3mr_expander_find_by_handle(struct mpi3mr_ioc 1415 *mrioc, u16 handle); 1416struct mpi3mr_hba_port *mpi3mr_get_hba_port_by_id(struct mpi3mr_ioc *mrioc, 1417 u8 port_id); 1418void mpi3mr_sas_host_refresh(struct mpi3mr_ioc *mrioc); 1419void mpi3mr_sas_host_add(struct mpi3mr_ioc *mrioc); 1420void mpi3mr_update_links(struct mpi3mr_ioc *mrioc, 1421 u64 sas_address_parent, u16 handle, u8 phy_number, u8 link_rate, 1422 struct mpi3mr_hba_port *hba_port); 1423void mpi3mr_remove_tgtdev_from_host(struct mpi3mr_ioc *mrioc, 1424 struct mpi3mr_tgt_dev *tgtdev); 1425int mpi3mr_report_tgtdev_to_sas_transport(struct mpi3mr_ioc *mrioc, 1426 struct mpi3mr_tgt_dev *tgtdev); 1427void mpi3mr_remove_tgtdev_from_sas_transport(struct mpi3mr_ioc *mrioc, 1428 struct mpi3mr_tgt_dev *tgtdev); 1429struct mpi3mr_tgt_dev *__mpi3mr_get_tgtdev_by_addr_and_rphy( 1430 struct mpi3mr_ioc *mrioc, u64 sas_address, struct sas_rphy *rphy); 1431void mpi3mr_print_device_event_notice(struct mpi3mr_ioc *mrioc, 1432 bool device_add); 1433void mpi3mr_refresh_sas_ports(struct mpi3mr_ioc *mrioc); 1434void mpi3mr_refresh_expanders(struct mpi3mr_ioc *mrioc); 1435void mpi3mr_add_event_wait_for_device_refresh(struct mpi3mr_ioc *mrioc); 1436void mpi3mr_flush_drv_cmds(struct mpi3mr_ioc *mrioc); 1437void mpi3mr_flush_cmds_for_unrecovered_controller(struct mpi3mr_ioc *mrioc); 1438void mpi3mr_free_enclosure_list(struct mpi3mr_ioc *mrioc); 1439int mpi3mr_process_admin_reply_q(struct mpi3mr_ioc *mrioc); 1440void mpi3mr_expander_node_remove(struct mpi3mr_ioc *mrioc, 1441 struct mpi3mr_sas_node *sas_expander); 1442#endif /*MPI3MR_H_INCLUDED*/ 1443