1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2/* Copyright(c) 2019-2022 Realtek Corporation 3 */ 4 5#include "chan.h" 6#include "coex.h" 7#include "debug.h" 8#include "fw.h" 9#include "mac.h" 10#include "phy.h" 11#include "reg.h" 12#include "rtw8852c.h" 13#include "rtw8852c_rfk.h" 14#include "rtw8852c_table.h" 15#include "util.h" 16 17#define RTW8852C_FW_FORMAT_MAX 0 18#define RTW8852C_FW_BASENAME "rtw89/rtw8852c_fw" 19#define RTW8852C_MODULE_FIRMWARE \ 20 RTW8852C_FW_BASENAME ".bin" 21 22static const struct rtw89_hfc_ch_cfg rtw8852c_hfc_chcfg_pcie[] = { 23 {13, 1614, grp_0}, /* ACH 0 */ 24 {13, 1614, grp_0}, /* ACH 1 */ 25 {13, 1614, grp_0}, /* ACH 2 */ 26 {13, 1614, grp_0}, /* ACH 3 */ 27 {13, 1614, grp_1}, /* ACH 4 */ 28 {13, 1614, grp_1}, /* ACH 5 */ 29 {13, 1614, grp_1}, /* ACH 6 */ 30 {13, 1614, grp_1}, /* ACH 7 */ 31 {13, 1614, grp_0}, /* B0MGQ */ 32 {13, 1614, grp_0}, /* B0HIQ */ 33 {13, 1614, grp_1}, /* B1MGQ */ 34 {13, 1614, grp_1}, /* B1HIQ */ 35 {40, 0, 0} /* FWCMDQ */ 36}; 37 38static const struct rtw89_hfc_pub_cfg rtw8852c_hfc_pubcfg_pcie = { 39 1614, /* Group 0 */ 40 1614, /* Group 1 */ 41 3228, /* Public Max */ 42 0 /* WP threshold */ 43}; 44 45static const struct rtw89_hfc_param_ini rtw8852c_hfc_param_ini_pcie[] = { 46 [RTW89_QTA_SCC] = {rtw8852c_hfc_chcfg_pcie, &rtw8852c_hfc_pubcfg_pcie, 47 &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH}, 48 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie, 49 RTW89_HCIFC_POH}, 50 [RTW89_QTA_INVALID] = {NULL}, 51}; 52 53static const struct rtw89_dle_mem rtw8852c_dle_mem_pcie[] = { 54 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size19, 55 &rtw89_mac_size.ple_size19, &rtw89_mac_size.wde_qt18, 56 &rtw89_mac_size.wde_qt18, &rtw89_mac_size.ple_qt46, 57 &rtw89_mac_size.ple_qt47}, 58 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size18, 59 &rtw89_mac_size.ple_size18, &rtw89_mac_size.wde_qt17, 60 &rtw89_mac_size.wde_qt17, &rtw89_mac_size.ple_qt44, 61 &rtw89_mac_size.ple_qt45}, 62 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, 63 NULL}, 64}; 65 66static const u32 rtw8852c_h2c_regs[RTW89_H2CREG_MAX] = { 67 R_AX_H2CREG_DATA0_V1, R_AX_H2CREG_DATA1_V1, R_AX_H2CREG_DATA2_V1, 68 R_AX_H2CREG_DATA3_V1 69}; 70 71static const u32 rtw8852c_c2h_regs[RTW89_H2CREG_MAX] = { 72 R_AX_C2HREG_DATA0_V1, R_AX_C2HREG_DATA1_V1, R_AX_C2HREG_DATA2_V1, 73 R_AX_C2HREG_DATA3_V1 74}; 75 76static const struct rtw89_page_regs rtw8852c_page_regs = { 77 .hci_fc_ctrl = R_AX_HCI_FC_CTRL_V1, 78 .ch_page_ctrl = R_AX_CH_PAGE_CTRL_V1, 79 .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL_V1, 80 .ach_page_info = R_AX_ACH0_PAGE_INFO_V1, 81 .pub_page_info3 = R_AX_PUB_PAGE_INFO3_V1, 82 .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1_V1, 83 .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2_V1, 84 .pub_page_info1 = R_AX_PUB_PAGE_INFO1_V1, 85 .pub_page_info2 = R_AX_PUB_PAGE_INFO2_V1, 86 .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1_V1, 87 .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2_V1, 88 .wp_page_info1 = R_AX_WP_PAGE_INFO1_V1, 89}; 90 91static const struct rtw89_reg_def rtw8852c_dcfo_comp = { 92 R_DCFO_COMP_S0_V1, B_DCFO_COMP_S0_V1_MSK 93}; 94 95static const struct rtw89_imr_info rtw8852c_imr_info = { 96 .wdrls_imr_set = B_AX_WDRLS_IMR_SET_V1, 97 .wsec_imr_reg = R_AX_SEC_ERROR_FLAG_IMR, 98 .wsec_imr_set = B_AX_TX_HANG_IMR | B_AX_RX_HANG_IMR, 99 .mpdu_tx_imr_set = B_AX_MPDU_TX_IMR_SET_V1, 100 .mpdu_rx_imr_set = B_AX_MPDU_RX_IMR_SET_V1, 101 .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET, 102 .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_B0_ERRFLAG_IMR, 103 .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR_V1, 104 .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET_V1, 105 .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_B1_ERRFLAG_IMR, 106 .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR_V1, 107 .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET_V1, 108 .wde_imr_clr = B_AX_WDE_IMR_CLR_V1, 109 .wde_imr_set = B_AX_WDE_IMR_SET_V1, 110 .ple_imr_clr = B_AX_PLE_IMR_CLR_V1, 111 .ple_imr_set = B_AX_PLE_IMR_SET_V1, 112 .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR_V1, 113 .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET_V1, 114 .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR_V1, 115 .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET_V1, 116 .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR_V1, 117 .other_disp_imr_set = B_AX_OTHER_DISP_IMR_SET_V1, 118 .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR, 119 .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR, 120 .bbrpt_err_imr_set = R_AX_BBRPT_CHINFO_IMR_SET_V1, 121 .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR, 122 .ptcl_imr_clr = B_AX_PTCL_IMR_CLR_V1, 123 .ptcl_imr_set = B_AX_PTCL_IMR_SET_V1, 124 .cdma_imr_0_reg = R_AX_RX_ERR_FLAG_IMR, 125 .cdma_imr_0_clr = B_AX_RX_ERR_IMR_CLR_V1, 126 .cdma_imr_0_set = B_AX_RX_ERR_IMR_SET_V1, 127 .cdma_imr_1_reg = R_AX_TX_ERR_FLAG_IMR, 128 .cdma_imr_1_clr = B_AX_TX_ERR_IMR_CLR_V1, 129 .cdma_imr_1_set = B_AX_TX_ERR_IMR_SET_V1, 130 .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR_V1, 131 .phy_intf_imr_clr = B_AX_PHYINFO_IMR_CLR_V1, 132 .phy_intf_imr_set = B_AX_PHYINFO_IMR_SET_V1, 133 .rmac_imr_reg = R_AX_RX_ERR_IMR, 134 .rmac_imr_clr = B_AX_RMAC_IMR_CLR_V1, 135 .rmac_imr_set = B_AX_RMAC_IMR_SET_V1, 136 .tmac_imr_reg = R_AX_TRXPTCL_ERROR_INDICA_MASK, 137 .tmac_imr_clr = B_AX_TMAC_IMR_CLR_V1, 138 .tmac_imr_set = B_AX_TMAC_IMR_SET_V1, 139}; 140 141static const struct rtw89_rrsr_cfgs rtw8852c_rrsr_cfgs = { 142 .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0}, 143 .rsc = {R_AX_PTCL_RRSR1, B_AX_RSC_MASK, 2}, 144}; 145 146static const struct rtw89_dig_regs rtw8852c_dig_regs = { 147 .seg0_pd_reg = R_SEG0R_PD, 148 .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK, 149 .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK, 150 .bmode_pd_reg = R_BMODE_PDTH_EN_V1, 151 .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1, 152 .bmode_pd_lower_bound_reg = R_BMODE_PDTH_V1, 153 .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1, 154 .p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK}, 155 .p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK}, 156 .p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1}, 157 .p1_tia_init = {R_PATH1_TIA_INIT_V1, B_PATH1_TIA_INIT_IDX_MSK_V1}, 158 .p0_rxb_init = {R_PATH0_RXB_INIT_V1, B_PATH0_RXB_INIT_IDX_MSK_V1}, 159 .p1_rxb_init = {R_PATH1_RXB_INIT_V1, B_PATH1_RXB_INIT_IDX_MSK_V1}, 160 .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC_V1, 161 B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 162 .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC_V1, 163 B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 164 .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC_V1, 165 B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 166 .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC_V1, 167 B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 168}; 169 170static const struct rtw89_edcca_regs rtw8852c_edcca_regs = { 171 .edcca_level = R_SEG0R_EDCCA_LVL, 172 .edcca_mask = B_EDCCA_LVL_MSK0, 173 .edcca_p_mask = B_EDCCA_LVL_MSK1, 174 .ppdu_level = R_SEG0R_EDCCA_LVL, 175 .ppdu_mask = B_EDCCA_LVL_MSK3, 176 .rpt_a = R_EDCCA_RPT_A, 177 .rpt_b = R_EDCCA_RPT_B, 178 .rpt_sel = R_EDCCA_RPT_SEL, 179 .rpt_sel_mask = B_EDCCA_RPT_SEL_MSK, 180 .tx_collision_t2r_st = R_TX_COLLISION_T2R_ST, 181 .tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_M, 182}; 183 184static void rtw8852c_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 185 enum rtw89_phy_idx phy_idx); 186 187static void rtw8852c_ctrl_tx_path_tmac(struct rtw89_dev *rtwdev, u8 tx_path, 188 enum rtw89_mac_idx mac_idx); 189 190static int rtw8852c_pwr_on_func(struct rtw89_dev *rtwdev) 191{ 192 u32 val32; 193 u32 ret; 194 195 val32 = rtw89_read32_mask(rtwdev, R_AX_SYS_STATUS1, B_AX_PAD_HCI_SEL_V2_MASK); 196 if (val32 == MAC_AX_HCI_SEL_PCIE_USB) 197 rtw89_write32_set(rtwdev, R_AX_LDO_AON_CTRL0, B_AX_PD_REGU_L); 198 199 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN | 200 B_AX_AFSM_PCIE_SUS_EN); 201 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC); 202 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC); 203 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN); 204 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS); 205 206 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, 207 B_AX_OCP_L1_MASK, 0x7); 208 209 ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_RDY_SYSPWR, 210 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 211 if (ret) 212 return ret; 213 214 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON); 215 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC); 216 217 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFN_ONMAC), 218 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 219 if (ret) 220 return ret; 221 222 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 223 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 224 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 225 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 226 227 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 228 rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1); 229 230 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, B_AX_CMAC1_FEN); 231 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, B_AX_R_SYM_ISO_CMAC12PP); 232 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, B_AX_R_SYM_WLCMAC1_P4_PC_EN | 233 B_AX_R_SYM_WLCMAC1_P3_PC_EN | 234 B_AX_R_SYM_WLCMAC1_P2_PC_EN | 235 B_AX_R_SYM_WLCMAC1_P1_PC_EN | 236 B_AX_R_SYM_WLCMAC1_PC_EN); 237 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3); 238 239 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 240 XTAL_SI_GND_SHDN_WL, XTAL_SI_GND_SHDN_WL); 241 if (ret) 242 return ret; 243 244 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3); 245 246 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 247 XTAL_SI_SHDN_WL, XTAL_SI_SHDN_WL); 248 if (ret) 249 return ret; 250 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI, 251 XTAL_SI_OFF_WEI); 252 if (ret) 253 return ret; 254 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI, 255 XTAL_SI_OFF_EI); 256 if (ret) 257 return ret; 258 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF); 259 if (ret) 260 return ret; 261 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI, 262 XTAL_SI_PON_WEI); 263 if (ret) 264 return ret; 265 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI, 266 XTAL_SI_PON_EI); 267 if (ret) 268 return ret; 269 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC); 270 if (ret) 271 return ret; 272 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0x10, XTAL_SI_LDO_LPS); 273 if (ret) 274 return ret; 275 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP); 276 if (ret) 277 return ret; 278 279 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 280 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE); 281 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15); 282 283 fsleep(1000); 284 285 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14); 286 rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 287 rtw89_write32_set(rtwdev, R_AX_GPIO0_15_EECS_EESK_LED1_PULL_LOW_EN, 288 B_AX_EECS_PULL_LOW_EN | B_AX_EESK_PULL_LOW_EN | 289 B_AX_LED1_PULL_LOW_EN); 290 291 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 292 B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MPDU_PROC_EN | 293 B_AX_WD_RLS_EN | B_AX_DLE_WDE_EN | B_AX_TXPKT_CTRL_EN | 294 B_AX_STA_SCH_EN | B_AX_DLE_PLE_EN | B_AX_PKT_BUF_EN | 295 B_AX_DMAC_TBL_EN | B_AX_PKT_IN_EN | B_AX_DLE_CPUIO_EN | 296 B_AX_DISPATCHER_EN | B_AX_BBRPT_EN | B_AX_MAC_SEC_EN | 297 B_AX_MAC_UN_EN | B_AX_H_AXIDMA_EN); 298 299 rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN, 300 B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 301 B_AX_FORCE_CMACREG_GCKEN | B_AX_PHYINTF_EN | 302 B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | B_AX_SCHEDULER_EN | 303 B_AX_TMAC_EN | B_AX_RMAC_EN); 304 305 rtw89_write32_mask(rtwdev, R_AX_LED1_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_V1_MASK, 306 PINMUX_EESK_FUNC_SEL_BT_LOG); 307 308 return 0; 309} 310 311static int rtw8852c_pwr_off_func(struct rtw89_dev *rtwdev) 312{ 313 u32 val32; 314 u32 ret; 315 316 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF, 317 XTAL_SI_RFC2RF); 318 if (ret) 319 return ret; 320 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI); 321 if (ret) 322 return ret; 323 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI); 324 if (ret) 325 return ret; 326 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00); 327 if (ret) 328 return ret; 329 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0, XTAL_SI_RF10); 330 if (ret) 331 return ret; 332 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC, 333 XTAL_SI_SRAM2RFC); 334 if (ret) 335 return ret; 336 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI); 337 if (ret) 338 return ret; 339 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI); 340 if (ret) 341 return ret; 342 343 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON); 344 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 345 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB); 346 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 347 B_AX_R_SYM_FEN_WLBBGLB_1 | B_AX_R_SYM_FEN_WLBBFUN_1); 348 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3); 349 350 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SHDN_WL); 351 if (ret) 352 return ret; 353 354 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3); 355 356 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_GND_SHDN_WL); 357 if (ret) 358 return ret; 359 360 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC); 361 362 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFM_OFFMAC), 363 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 364 if (ret) 365 return ret; 366 367 rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, SW_LPS_OPTION); 368 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_XTAL_OFF_A_DIE); 369 rtw89_write32_set(rtwdev, R_AX_SYS_SWR_CTRL1, B_AX_SYM_CTRL_SPS_PWMFREQ); 370 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, 371 B_AX_REG_ZCDC_H_MASK, 0x3); 372 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS); 373 374 return 0; 375} 376 377static void rtw8852c_e_efuse_parsing(struct rtw89_efuse *efuse, 378 struct rtw8852c_efuse *map) 379{ 380 ether_addr_copy(efuse->addr, map->e.mac_addr); 381 efuse->rfe_type = map->rfe_type; 382 efuse->xtal_cap = map->xtal_k; 383} 384 385static void rtw8852c_efuse_parsing_tssi(struct rtw89_dev *rtwdev, 386 struct rtw8852c_efuse *map) 387{ 388 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 389 struct rtw8852c_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi}; 390 u8 *bw40_1s_tssi_6g_ofst[] = {map->bw40_1s_tssi_6g_a, map->bw40_1s_tssi_6g_b}; 391 u8 i, j; 392 393 tssi->thermal[RF_PATH_A] = map->path_a_therm; 394 tssi->thermal[RF_PATH_B] = map->path_b_therm; 395 396 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 397 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi, 398 sizeof(ofst[i]->cck_tssi)); 399 400 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++) 401 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 402 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n", 403 i, j, tssi->tssi_cck[i][j]); 404 405 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi, 406 sizeof(ofst[i]->bw40_tssi)); 407 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM, 408 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g)); 409 memcpy(tssi->tssi_6g_mcs[i], bw40_1s_tssi_6g_ofst[i], 410 sizeof(tssi->tssi_6g_mcs[i])); 411 412 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++) 413 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 414 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n", 415 i, j, tssi->tssi_mcs[i][j]); 416 } 417} 418 419static bool _decode_efuse_gain(u8 data, s8 *high, s8 *low) 420{ 421 if (high) 422 *high = sign_extend32(FIELD_GET(GENMASK(7, 4), data), 3); 423 if (low) 424 *low = sign_extend32(FIELD_GET(GENMASK(3, 0), data), 3); 425 426 return data != 0xff; 427} 428 429static void rtw8852c_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev, 430 struct rtw8852c_efuse *map) 431{ 432 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; 433 bool valid = false; 434 435 valid |= _decode_efuse_gain(map->rx_gain_2g_cck, 436 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_CCK], 437 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_CCK]); 438 valid |= _decode_efuse_gain(map->rx_gain_2g_ofdm, 439 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_OFDM], 440 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_OFDM]); 441 valid |= _decode_efuse_gain(map->rx_gain_5g_low, 442 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_LOW], 443 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_LOW]); 444 valid |= _decode_efuse_gain(map->rx_gain_5g_mid, 445 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_MID], 446 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_MID]); 447 valid |= _decode_efuse_gain(map->rx_gain_5g_high, 448 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_HIGH], 449 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_HIGH]); 450 valid |= _decode_efuse_gain(map->rx_gain_6g_l0, 451 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_L0], 452 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_L0]); 453 valid |= _decode_efuse_gain(map->rx_gain_6g_l1, 454 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_L1], 455 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_L1]); 456 valid |= _decode_efuse_gain(map->rx_gain_6g_m0, 457 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_M0], 458 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_M0]); 459 valid |= _decode_efuse_gain(map->rx_gain_6g_m1, 460 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_M1], 461 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_M1]); 462 valid |= _decode_efuse_gain(map->rx_gain_6g_h0, 463 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_H0], 464 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_H0]); 465 valid |= _decode_efuse_gain(map->rx_gain_6g_h1, 466 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_H1], 467 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_H1]); 468 valid |= _decode_efuse_gain(map->rx_gain_6g_uh0, 469 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_UH0], 470 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_UH0]); 471 valid |= _decode_efuse_gain(map->rx_gain_6g_uh1, 472 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_UH1], 473 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_UH1]); 474 475 gain->offset_valid = valid; 476} 477 478static int rtw8852c_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map, 479 enum rtw89_efuse_block block) 480{ 481 struct rtw89_efuse *efuse = &rtwdev->efuse; 482 struct rtw8852c_efuse *map; 483 484 map = (struct rtw8852c_efuse *)log_map; 485 486 efuse->country_code[0] = map->country_code[0]; 487 efuse->country_code[1] = map->country_code[1]; 488 rtw8852c_efuse_parsing_tssi(rtwdev, map); 489 rtw8852c_efuse_parsing_gain_offset(rtwdev, map); 490 491 switch (rtwdev->hci.type) { 492 case RTW89_HCI_TYPE_PCIE: 493 rtw8852c_e_efuse_parsing(efuse, map); 494 break; 495 default: 496 return -ENOTSUPP; 497 } 498 499 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type); 500 501 return 0; 502} 503 504static void rtw8852c_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map) 505{ 506 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 507 static const u32 tssi_trim_addr[RF_PATH_NUM_8852C] = {0x5D6, 0x5AB}; 508 static const u32 tssi_trim_addr_6g[RF_PATH_NUM_8852C] = {0x5CE, 0x5A3}; 509 u32 addr = rtwdev->chip->phycap_addr; 510 bool pg = false; 511 u32 ofst; 512 u8 i, j; 513 514 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 515 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) { 516 /* addrs are in decreasing order */ 517 ofst = tssi_trim_addr[i] - addr - j; 518 tssi->tssi_trim[i][j] = phycap_map[ofst]; 519 520 if (phycap_map[ofst] != 0xff) 521 pg = true; 522 } 523 524 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM_6G; j++) { 525 /* addrs are in decreasing order */ 526 ofst = tssi_trim_addr_6g[i] - addr - j; 527 tssi->tssi_trim_6g[i][j] = phycap_map[ofst]; 528 529 if (phycap_map[ofst] != 0xff) 530 pg = true; 531 } 532 } 533 534 if (!pg) { 535 memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim)); 536 memset(tssi->tssi_trim_6g, 0, sizeof(tssi->tssi_trim_6g)); 537 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 538 "[TSSI][TRIM] no PG, set all trim info to 0\n"); 539 } 540 541 for (i = 0; i < RF_PATH_NUM_8852C; i++) 542 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) 543 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 544 "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n", 545 i, j, tssi->tssi_trim[i][j], 546 tssi_trim_addr[i] - j); 547} 548 549static void rtw8852c_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev, 550 u8 *phycap_map) 551{ 552 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 553 static const u32 thm_trim_addr[RF_PATH_NUM_8852C] = {0x5DF, 0x5DC}; 554 u32 addr = rtwdev->chip->phycap_addr; 555 u8 i; 556 557 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 558 info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr]; 559 560 rtw89_debug(rtwdev, RTW89_DBG_RFK, 561 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n", 562 i, info->thermal_trim[i]); 563 564 if (info->thermal_trim[i] != 0xff) 565 info->pg_thermal_trim = true; 566 } 567} 568 569static void rtw8852c_thermal_trim(struct rtw89_dev *rtwdev) 570{ 571#define __thm_setting(raw) \ 572({ \ 573 u8 __v = (raw); \ 574 ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \ 575}) 576 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 577 u8 i, val; 578 579 if (!info->pg_thermal_trim) { 580 rtw89_debug(rtwdev, RTW89_DBG_RFK, 581 "[THERMAL][TRIM] no PG, do nothing\n"); 582 583 return; 584 } 585 586 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 587 val = __thm_setting(info->thermal_trim[i]); 588 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val); 589 590 rtw89_debug(rtwdev, RTW89_DBG_RFK, 591 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n", 592 i, val); 593 } 594#undef __thm_setting 595} 596 597static void rtw8852c_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev, 598 u8 *phycap_map) 599{ 600 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 601 static const u32 pabias_trim_addr[RF_PATH_NUM_8852C] = {0x5DE, 0x5DB}; 602 u32 addr = rtwdev->chip->phycap_addr; 603 u8 i; 604 605 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 606 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr]; 607 608 rtw89_debug(rtwdev, RTW89_DBG_RFK, 609 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n", 610 i, info->pa_bias_trim[i]); 611 612 if (info->pa_bias_trim[i] != 0xff) 613 info->pg_pa_bias_trim = true; 614 } 615} 616 617static void rtw8852c_pa_bias_trim(struct rtw89_dev *rtwdev) 618{ 619 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 620 u8 pabias_2g, pabias_5g; 621 u8 i; 622 623 if (!info->pg_pa_bias_trim) { 624 rtw89_debug(rtwdev, RTW89_DBG_RFK, 625 "[PA_BIAS][TRIM] no PG, do nothing\n"); 626 627 return; 628 } 629 630 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 631 pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]); 632 pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]); 633 634 rtw89_debug(rtwdev, RTW89_DBG_RFK, 635 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n", 636 i, pabias_2g, pabias_5g); 637 638 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g); 639 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g); 640 } 641} 642 643static int rtw8852c_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map) 644{ 645 rtw8852c_phycap_parsing_tssi(rtwdev, phycap_map); 646 rtw8852c_phycap_parsing_thermal_trim(rtwdev, phycap_map); 647 rtw8852c_phycap_parsing_pa_bias_trim(rtwdev, phycap_map); 648 649 return 0; 650} 651 652static void rtw8852c_power_trim(struct rtw89_dev *rtwdev) 653{ 654 rtw8852c_thermal_trim(rtwdev); 655 rtw8852c_pa_bias_trim(rtwdev); 656} 657 658static void rtw8852c_set_channel_mac(struct rtw89_dev *rtwdev, 659 const struct rtw89_chan *chan, 660 u8 mac_idx) 661{ 662 u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_AX_WMAC_RFMOD, mac_idx); 663 u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 664 u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXRATE_CHK, mac_idx); 665 u8 txsc20 = 0, txsc40 = 0, txsc80 = 0; 666 u8 rf_mod_val = 0, chk_rate_mask = 0; 667 u32 txsc; 668 669 switch (chan->band_width) { 670 case RTW89_CHANNEL_WIDTH_160: 671 txsc80 = rtw89_phy_get_txsc(rtwdev, chan, 672 RTW89_CHANNEL_WIDTH_80); 673 fallthrough; 674 case RTW89_CHANNEL_WIDTH_80: 675 txsc40 = rtw89_phy_get_txsc(rtwdev, chan, 676 RTW89_CHANNEL_WIDTH_40); 677 fallthrough; 678 case RTW89_CHANNEL_WIDTH_40: 679 txsc20 = rtw89_phy_get_txsc(rtwdev, chan, 680 RTW89_CHANNEL_WIDTH_20); 681 break; 682 default: 683 break; 684 } 685 686 switch (chan->band_width) { 687 case RTW89_CHANNEL_WIDTH_160: 688 rf_mod_val = AX_WMAC_RFMOD_160M; 689 txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20) | 690 FIELD_PREP(B_AX_TXSC_40M_MASK, txsc40) | 691 FIELD_PREP(B_AX_TXSC_80M_MASK, txsc80); 692 break; 693 case RTW89_CHANNEL_WIDTH_80: 694 rf_mod_val = AX_WMAC_RFMOD_80M; 695 txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20) | 696 FIELD_PREP(B_AX_TXSC_40M_MASK, txsc40); 697 break; 698 case RTW89_CHANNEL_WIDTH_40: 699 rf_mod_val = AX_WMAC_RFMOD_40M; 700 txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20); 701 break; 702 case RTW89_CHANNEL_WIDTH_20: 703 default: 704 rf_mod_val = AX_WMAC_RFMOD_20M; 705 txsc = 0; 706 break; 707 } 708 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, rf_mod_val); 709 rtw89_write32(rtwdev, sub_carr, txsc); 710 711 switch (chan->band_type) { 712 case RTW89_BAND_2G: 713 chk_rate_mask = B_AX_BAND_MODE; 714 break; 715 case RTW89_BAND_5G: 716 case RTW89_BAND_6G: 717 chk_rate_mask = B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6; 718 break; 719 default: 720 rtw89_warn(rtwdev, "Invalid band_type:%d\n", chan->band_type); 721 return; 722 } 723 rtw89_write8_clr(rtwdev, chk_rate, B_AX_BAND_MODE | B_AX_CHECK_CCK_EN | 724 B_AX_RTS_LIMIT_IN_OFDM6); 725 rtw89_write8_set(rtwdev, chk_rate, chk_rate_mask); 726} 727 728static const u32 rtw8852c_sco_barker_threshold[14] = { 729 0x1fe4f, 0x1ff5e, 0x2006c, 0x2017b, 0x2028a, 0x20399, 0x204a8, 0x205b6, 730 0x206c5, 0x207d4, 0x208e3, 0x209f2, 0x20b00, 0x20d8a 731}; 732 733static const u32 rtw8852c_sco_cck_threshold[14] = { 734 0x2bdac, 0x2bf21, 0x2c095, 0x2c209, 0x2c37e, 0x2c4f2, 0x2c666, 0x2c7db, 735 0x2c94f, 0x2cac3, 0x2cc38, 0x2cdac, 0x2cf21, 0x2d29e 736}; 737 738static int rtw8852c_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 central_ch, 739 u8 primary_ch, enum rtw89_bandwidth bw) 740{ 741 u8 ch_element; 742 743 if (bw == RTW89_CHANNEL_WIDTH_20) { 744 ch_element = central_ch - 1; 745 } else if (bw == RTW89_CHANNEL_WIDTH_40) { 746 if (primary_ch == 1) 747 ch_element = central_ch - 1 + 2; 748 else 749 ch_element = central_ch - 1 - 2; 750 } else { 751 rtw89_warn(rtwdev, "Invalid BW:%d for CCK\n", bw); 752 return -EINVAL; 753 } 754 rtw89_phy_write32_mask(rtwdev, R_BK_FC0_INV_V1, B_BK_FC0_INV_MSK_V1, 755 rtw8852c_sco_barker_threshold[ch_element]); 756 rtw89_phy_write32_mask(rtwdev, R_CCK_FC0_INV_V1, B_CCK_FC0_INV_MSK_V1, 757 rtw8852c_sco_cck_threshold[ch_element]); 758 759 return 0; 760} 761 762struct rtw8852c_bb_gain { 763 u32 gain_g[BB_PATH_NUM_8852C]; 764 u32 gain_a[BB_PATH_NUM_8852C]; 765 u32 gain_mask; 766}; 767 768static const struct rtw8852c_bb_gain bb_gain_lna[LNA_GAIN_NUM] = { 769 { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740}, 770 .gain_mask = 0x00ff0000 }, 771 { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740}, 772 .gain_mask = 0xff000000 }, 773 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 774 .gain_mask = 0x000000ff }, 775 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 776 .gain_mask = 0x0000ff00 }, 777 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 778 .gain_mask = 0x00ff0000 }, 779 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 780 .gain_mask = 0xff000000 }, 781 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 782 .gain_mask = 0x000000ff }, 783}; 784 785static const struct rtw8852c_bb_gain bb_gain_tia[TIA_GAIN_NUM] = { 786 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 787 .gain_mask = 0x00ff0000 }, 788 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 789 .gain_mask = 0xff000000 }, 790}; 791 792struct rtw8852c_bb_gain_bypass { 793 u32 gain_g[BB_PATH_NUM_8852C]; 794 u32 gain_a[BB_PATH_NUM_8852C]; 795 u32 gain_mask_g; 796 u32 gain_mask_a; 797}; 798 799static 800const struct rtw8852c_bb_gain_bypass bb_gain_bypass_lna[LNA_GAIN_NUM] = { 801 { .gain_g = {0x4BB8, 0x4C7C}, .gain_a = {0x4BB4, 0x4C78}, 802 .gain_mask_g = 0xff000000, .gain_mask_a = 0xff}, 803 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78}, 804 .gain_mask_g = 0xff, .gain_mask_a = 0xff00}, 805 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78}, 806 .gain_mask_g = 0xff00, .gain_mask_a = 0xff0000}, 807 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78}, 808 .gain_mask_g = 0xff0000, .gain_mask_a = 0xff000000}, 809 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB8, 0x4C7C}, 810 .gain_mask_g = 0xff000000, .gain_mask_a = 0xff}, 811 { .gain_g = {0x4BC0, 0x4C84}, .gain_a = {0x4BB8, 0x4C7C}, 812 .gain_mask_g = 0xff, .gain_mask_a = 0xff00}, 813 { .gain_g = {0x4BC0, 0x4C84}, .gain_a = {0x4BB8, 0x4C7C}, 814 .gain_mask_g = 0xff00, .gain_mask_a = 0xff0000}, 815}; 816 817struct rtw8852c_bb_gain_op1db { 818 struct { 819 u32 lna[BB_PATH_NUM_8852C]; 820 u32 tia_lna[BB_PATH_NUM_8852C]; 821 u32 mask; 822 } reg[LNA_GAIN_NUM]; 823 u32 reg_tia0_lna6[BB_PATH_NUM_8852C]; 824 u32 mask_tia0_lna6; 825}; 826 827static const struct rtw8852c_bb_gain_op1db bb_gain_op1db_a = { 828 .reg = { 829 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 830 .mask = 0xff}, 831 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 832 .mask = 0xff00}, 833 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 834 .mask = 0xff0000}, 835 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 836 .mask = 0xff000000}, 837 { .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758}, 838 .mask = 0xff}, 839 { .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758}, 840 .mask = 0xff00}, 841 { .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758}, 842 .mask = 0xff0000}, 843 }, 844 .reg_tia0_lna6 = {0x4674, 0x4758}, 845 .mask_tia0_lna6 = 0xff000000, 846}; 847 848static void rtw8852c_set_gain_error(struct rtw89_dev *rtwdev, 849 enum rtw89_subband subband, 850 enum rtw89_rf_path path) 851{ 852 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax; 853 u8 gain_band = rtw89_subband_to_bb_gain_band(subband); 854 s32 val; 855 u32 reg; 856 u32 mask; 857 int i; 858 859 for (i = 0; i < LNA_GAIN_NUM; i++) { 860 if (subband == RTW89_CH_2G) 861 reg = bb_gain_lna[i].gain_g[path]; 862 else 863 reg = bb_gain_lna[i].gain_a[path]; 864 865 mask = bb_gain_lna[i].gain_mask; 866 val = gain->lna_gain[gain_band][path][i]; 867 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 868 869 if (subband == RTW89_CH_2G) { 870 reg = bb_gain_bypass_lna[i].gain_g[path]; 871 mask = bb_gain_bypass_lna[i].gain_mask_g; 872 } else { 873 reg = bb_gain_bypass_lna[i].gain_a[path]; 874 mask = bb_gain_bypass_lna[i].gain_mask_a; 875 } 876 877 val = gain->lna_gain_bypass[gain_band][path][i]; 878 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 879 880 if (subband != RTW89_CH_2G) { 881 reg = bb_gain_op1db_a.reg[i].lna[path]; 882 mask = bb_gain_op1db_a.reg[i].mask; 883 val = gain->lna_op1db[gain_band][path][i]; 884 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 885 886 reg = bb_gain_op1db_a.reg[i].tia_lna[path]; 887 mask = bb_gain_op1db_a.reg[i].mask; 888 val = gain->tia_lna_op1db[gain_band][path][i]; 889 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 890 } 891 } 892 893 if (subband != RTW89_CH_2G) { 894 reg = bb_gain_op1db_a.reg_tia0_lna6[path]; 895 mask = bb_gain_op1db_a.mask_tia0_lna6; 896 val = gain->tia_lna_op1db[gain_band][path][7]; 897 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 898 } 899 900 for (i = 0; i < TIA_GAIN_NUM; i++) { 901 if (subband == RTW89_CH_2G) 902 reg = bb_gain_tia[i].gain_g[path]; 903 else 904 reg = bb_gain_tia[i].gain_a[path]; 905 906 mask = bb_gain_tia[i].gain_mask; 907 val = gain->tia_gain[gain_band][path][i]; 908 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 909 } 910} 911 912static void rtw8852c_set_gain_offset(struct rtw89_dev *rtwdev, 913 const struct rtw89_chan *chan, 914 enum rtw89_phy_idx phy_idx, 915 enum rtw89_rf_path path) 916{ 917 static const u32 rssi_ofst_addr[2] = {R_PATH0_G_TIA0_LNA6_OP1DB_V1, 918 R_PATH1_G_TIA0_LNA6_OP1DB_V1}; 919 static const u32 rpl_mask[2] = {B_RPL_PATHA_MASK, B_RPL_PATHB_MASK}; 920 static const u32 rpl_tb_mask[2] = {B_RSSI_M_PATHA_MASK, B_RSSI_M_PATHB_MASK}; 921 struct rtw89_phy_efuse_gain *efuse_gain = &rtwdev->efuse_gain; 922 enum rtw89_gain_offset gain_band; 923 s32 offset_q0, offset_base_q4; 924 s32 tmp = 0; 925 926 if (!efuse_gain->offset_valid) 927 return; 928 929 if (rtwdev->dbcc_en && path == RF_PATH_B) 930 phy_idx = RTW89_PHY_1; 931 932 if (chan->band_type == RTW89_BAND_2G) { 933 offset_q0 = efuse_gain->offset[path][RTW89_GAIN_OFFSET_2G_CCK]; 934 offset_base_q4 = efuse_gain->offset_base[phy_idx]; 935 936 tmp = clamp_t(s32, (-offset_q0 << 3) + (offset_base_q4 >> 1), 937 S8_MIN >> 1, S8_MAX >> 1); 938 rtw89_phy_write32_mask(rtwdev, R_RPL_OFST, B_RPL_OFST_MASK, tmp & 0x7f); 939 } 940 941 gain_band = rtw89_subband_to_gain_offset_band_of_ofdm(chan->subband_type); 942 943 offset_q0 = -efuse_gain->offset[path][gain_band]; 944 offset_base_q4 = efuse_gain->offset_base[phy_idx]; 945 946 tmp = (offset_q0 << 2) + (offset_base_q4 >> 2); 947 tmp = clamp_t(s32, -tmp, S8_MIN, S8_MAX); 948 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[path], B_PATH0_R_G_OFST_MASK, tmp & 0xff); 949 950 tmp = clamp_t(s32, offset_q0 << 4, S8_MIN, S8_MAX); 951 rtw89_phy_write32_idx(rtwdev, R_RPL_PATHAB, rpl_mask[path], tmp & 0xff, phy_idx); 952 rtw89_phy_write32_idx(rtwdev, R_RSSI_M_PATHAB, rpl_tb_mask[path], tmp & 0xff, phy_idx); 953} 954 955static void rtw8852c_ctrl_ch(struct rtw89_dev *rtwdev, 956 const struct rtw89_chan *chan, 957 enum rtw89_phy_idx phy_idx) 958{ 959 u8 sco; 960 u16 central_freq = chan->freq; 961 u8 central_ch = chan->channel; 962 u8 band = chan->band_type; 963 u8 subband = chan->subband_type; 964 bool is_2g = band == RTW89_BAND_2G; 965 u8 chan_idx; 966 967 if (!central_freq) { 968 rtw89_warn(rtwdev, "Invalid central_freq\n"); 969 return; 970 } 971 972 if (phy_idx == RTW89_PHY_0) { 973 /* Path A */ 974 rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_A); 975 rtw8852c_set_gain_offset(rtwdev, chan, phy_idx, RF_PATH_A); 976 977 if (is_2g) 978 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, 979 B_PATH0_BAND_SEL_MSK_V1, 1, 980 phy_idx); 981 else 982 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, 983 B_PATH0_BAND_SEL_MSK_V1, 0, 984 phy_idx); 985 /* Path B */ 986 if (!rtwdev->dbcc_en) { 987 rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_B); 988 rtw8852c_set_gain_offset(rtwdev, chan, phy_idx, RF_PATH_B); 989 990 if (is_2g) 991 rtw89_phy_write32_idx(rtwdev, 992 R_PATH1_BAND_SEL_V1, 993 B_PATH1_BAND_SEL_MSK_V1, 994 1, phy_idx); 995 else 996 rtw89_phy_write32_idx(rtwdev, 997 R_PATH1_BAND_SEL_V1, 998 B_PATH1_BAND_SEL_MSK_V1, 999 0, phy_idx); 1000 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL); 1001 } else { 1002 if (is_2g) 1003 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL); 1004 else 1005 rtw89_phy_write32_set(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL); 1006 } 1007 /* SCO compensate FC setting */ 1008 rtw89_phy_write32_idx(rtwdev, R_FC0_V1, B_FC0_MSK_V1, 1009 central_freq, phy_idx); 1010 /* round_up((1/fc0)*pow(2,18)) */ 1011 sco = DIV_ROUND_CLOSEST(1 << 18, central_freq); 1012 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, sco, 1013 phy_idx); 1014 } else { 1015 /* Path B */ 1016 rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_B); 1017 rtw8852c_set_gain_offset(rtwdev, chan, phy_idx, RF_PATH_B); 1018 1019 if (is_2g) 1020 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1, 1021 B_PATH1_BAND_SEL_MSK_V1, 1022 1, phy_idx); 1023 else 1024 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1, 1025 B_PATH1_BAND_SEL_MSK_V1, 1026 0, phy_idx); 1027 /* SCO compensate FC setting */ 1028 rtw89_phy_write32_idx(rtwdev, R_FC0_V1, B_FC0_MSK_V1, 1029 central_freq, phy_idx); 1030 /* round_up((1/fc0)*pow(2,18)) */ 1031 sco = DIV_ROUND_CLOSEST(1 << 18, central_freq); 1032 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, sco, 1033 phy_idx); 1034 } 1035 /* CCK parameters */ 1036 if (band == RTW89_BAND_2G) { 1037 if (central_ch == 14) { 1038 rtw89_phy_write32_mask(rtwdev, R_PCOEFF0_V1, 1039 B_PCOEFF01_MSK_V1, 0x3b13ff); 1040 rtw89_phy_write32_mask(rtwdev, R_PCOEFF2_V1, 1041 B_PCOEFF23_MSK_V1, 0x1c42de); 1042 rtw89_phy_write32_mask(rtwdev, R_PCOEFF4_V1, 1043 B_PCOEFF45_MSK_V1, 0xfdb0ad); 1044 rtw89_phy_write32_mask(rtwdev, R_PCOEFF6_V1, 1045 B_PCOEFF67_MSK_V1, 0xf60f6e); 1046 rtw89_phy_write32_mask(rtwdev, R_PCOEFF8_V1, 1047 B_PCOEFF89_MSK_V1, 0xfd8f92); 1048 rtw89_phy_write32_mask(rtwdev, R_PCOEFFA_V1, 1049 B_PCOEFFAB_MSK_V1, 0x2d011); 1050 rtw89_phy_write32_mask(rtwdev, R_PCOEFFC_V1, 1051 B_PCOEFFCD_MSK_V1, 0x1c02c); 1052 rtw89_phy_write32_mask(rtwdev, R_PCOEFFE_V1, 1053 B_PCOEFFEF_MSK_V1, 0xfff00a); 1054 } else { 1055 rtw89_phy_write32_mask(rtwdev, R_PCOEFF0_V1, 1056 B_PCOEFF01_MSK_V1, 0x3d23ff); 1057 rtw89_phy_write32_mask(rtwdev, R_PCOEFF2_V1, 1058 B_PCOEFF23_MSK_V1, 0x29b354); 1059 rtw89_phy_write32_mask(rtwdev, R_PCOEFF4_V1, 1060 B_PCOEFF45_MSK_V1, 0xfc1c8); 1061 rtw89_phy_write32_mask(rtwdev, R_PCOEFF6_V1, 1062 B_PCOEFF67_MSK_V1, 0xfdb053); 1063 rtw89_phy_write32_mask(rtwdev, R_PCOEFF8_V1, 1064 B_PCOEFF89_MSK_V1, 0xf86f9a); 1065 rtw89_phy_write32_mask(rtwdev, R_PCOEFFA_V1, 1066 B_PCOEFFAB_MSK_V1, 0xfaef92); 1067 rtw89_phy_write32_mask(rtwdev, R_PCOEFFC_V1, 1068 B_PCOEFFCD_MSK_V1, 0xfe5fcc); 1069 rtw89_phy_write32_mask(rtwdev, R_PCOEFFE_V1, 1070 B_PCOEFFEF_MSK_V1, 0xffdff5); 1071 } 1072 } 1073 1074 chan_idx = rtw89_encode_chan_idx(rtwdev, chan->primary_channel, band); 1075 rtw89_phy_write32_idx(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, chan_idx, phy_idx); 1076} 1077 1078static void rtw8852c_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path) 1079{ 1080 static const u32 adc_sel[2] = {0xC0EC, 0xC1EC}; 1081 static const u32 wbadc_sel[2] = {0xC0E4, 0xC1E4}; 1082 1083 switch (bw) { 1084 case RTW89_CHANNEL_WIDTH_5: 1085 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1); 1086 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0); 1087 break; 1088 case RTW89_CHANNEL_WIDTH_10: 1089 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2); 1090 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1); 1091 break; 1092 case RTW89_CHANNEL_WIDTH_20: 1093 case RTW89_CHANNEL_WIDTH_40: 1094 case RTW89_CHANNEL_WIDTH_80: 1095 case RTW89_CHANNEL_WIDTH_160: 1096 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 1097 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 1098 break; 1099 default: 1100 rtw89_warn(rtwdev, "Fail to set ADC\n"); 1101 } 1102} 1103 1104static void rtw8852c_edcca_per20_bitmap_sifs(struct rtw89_dev *rtwdev, u8 bw, 1105 enum rtw89_phy_idx phy_idx) 1106{ 1107 if (bw == RTW89_CHANNEL_WIDTH_20) { 1108 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A1, B_SNDCCA_A1_EN, 0xff, phy_idx); 1109 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A2, B_SNDCCA_A2_VAL, 0, phy_idx); 1110 } else { 1111 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A1, B_SNDCCA_A1_EN, 0, phy_idx); 1112 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A2, B_SNDCCA_A2_VAL, 0, phy_idx); 1113 } 1114} 1115 1116static void 1117rtw8852c_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw, 1118 enum rtw89_phy_idx phy_idx) 1119{ 1120 u8 mod_sbw = 0; 1121 1122 switch (bw) { 1123 case RTW89_CHANNEL_WIDTH_5: 1124 case RTW89_CHANNEL_WIDTH_10: 1125 case RTW89_CHANNEL_WIDTH_20: 1126 if (bw == RTW89_CHANNEL_WIDTH_5) 1127 mod_sbw = 0x1; 1128 else if (bw == RTW89_CHANNEL_WIDTH_10) 1129 mod_sbw = 0x2; 1130 else if (bw == RTW89_CHANNEL_WIDTH_20) 1131 mod_sbw = 0x0; 1132 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 1133 phy_idx); 1134 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 1135 mod_sbw, phy_idx); 1136 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 0x0, 1137 phy_idx); 1138 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1139 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x3); 1140 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1141 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x3); 1142 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1143 B_PATH0_BW_SEL_MSK_V1, 0xf); 1144 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1145 B_PATH1_BW_SEL_MSK_V1, 0xf); 1146 break; 1147 case RTW89_CHANNEL_WIDTH_40: 1148 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x1, 1149 phy_idx); 1150 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1151 phy_idx); 1152 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1153 pri_ch, 1154 phy_idx); 1155 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1156 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x3); 1157 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1158 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x3); 1159 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1160 B_PATH0_BW_SEL_MSK_V1, 0xf); 1161 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1162 B_PATH1_BW_SEL_MSK_V1, 0xf); 1163 break; 1164 case RTW89_CHANNEL_WIDTH_80: 1165 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x2, 1166 phy_idx); 1167 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1168 phy_idx); 1169 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1170 pri_ch, 1171 phy_idx); 1172 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1173 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x2); 1174 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1175 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x2); 1176 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1177 B_PATH0_BW_SEL_MSK_V1, 0xd); 1178 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1179 B_PATH1_BW_SEL_MSK_V1, 0xd); 1180 break; 1181 case RTW89_CHANNEL_WIDTH_160: 1182 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x3, 1183 phy_idx); 1184 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1185 phy_idx); 1186 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1187 pri_ch, 1188 phy_idx); 1189 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1190 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x1); 1191 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1192 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x1); 1193 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1194 B_PATH0_BW_SEL_MSK_V1, 0xb); 1195 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1196 B_PATH1_BW_SEL_MSK_V1, 0xb); 1197 break; 1198 default: 1199 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw, 1200 pri_ch); 1201 } 1202 1203 if (bw == RTW89_CHANNEL_WIDTH_40) { 1204 rtw89_phy_write32_idx(rtwdev, R_RX_BW40_2XFFT_EN_V1, 1205 B_RX_BW40_2XFFT_EN_MSK_V1, 0x1, phy_idx); 1206 rtw89_phy_write32_idx(rtwdev, R_T2F_GI_COMB, B_T2F_GI_COMB_EN, 1, phy_idx); 1207 } else { 1208 rtw89_phy_write32_idx(rtwdev, R_RX_BW40_2XFFT_EN_V1, 1209 B_RX_BW40_2XFFT_EN_MSK_V1, 0x0, phy_idx); 1210 rtw89_phy_write32_idx(rtwdev, R_T2F_GI_COMB, B_T2F_GI_COMB_EN, 0, phy_idx); 1211 } 1212 1213 if (phy_idx == RTW89_PHY_0) { 1214 rtw8852c_bw_setting(rtwdev, bw, RF_PATH_A); 1215 if (!rtwdev->dbcc_en) 1216 rtw8852c_bw_setting(rtwdev, bw, RF_PATH_B); 1217 } else { 1218 rtw8852c_bw_setting(rtwdev, bw, RF_PATH_B); 1219 } 1220 1221 rtw8852c_edcca_per20_bitmap_sifs(rtwdev, bw, phy_idx); 1222} 1223 1224static u32 rtw8852c_spur_freq(struct rtw89_dev *rtwdev, 1225 const struct rtw89_chan *chan) 1226{ 1227 u8 center_chan = chan->channel; 1228 u8 bw = chan->band_width; 1229 1230 switch (chan->band_type) { 1231 case RTW89_BAND_2G: 1232 if (bw == RTW89_CHANNEL_WIDTH_20) { 1233 if (center_chan >= 5 && center_chan <= 8) 1234 return 2440; 1235 if (center_chan == 13) 1236 return 2480; 1237 } else if (bw == RTW89_CHANNEL_WIDTH_40) { 1238 if (center_chan >= 3 && center_chan <= 10) 1239 return 2440; 1240 } 1241 break; 1242 case RTW89_BAND_5G: 1243 if (center_chan == 151 || center_chan == 153 || 1244 center_chan == 155 || center_chan == 163) 1245 return 5760; 1246 break; 1247 case RTW89_BAND_6G: 1248 if (center_chan == 195 || center_chan == 197 || 1249 center_chan == 199 || center_chan == 207) 1250 return 6920; 1251 break; 1252 default: 1253 break; 1254 } 1255 1256 return 0; 1257} 1258 1259#define CARRIER_SPACING_312_5 312500 /* 312.5 kHz */ 1260#define CARRIER_SPACING_78_125 78125 /* 78.125 kHz */ 1261#define MAX_TONE_NUM 2048 1262 1263static void rtw8852c_set_csi_tone_idx(struct rtw89_dev *rtwdev, 1264 const struct rtw89_chan *chan, 1265 enum rtw89_phy_idx phy_idx) 1266{ 1267 u32 spur_freq; 1268 s32 freq_diff, csi_idx, csi_tone_idx; 1269 1270 spur_freq = rtw8852c_spur_freq(rtwdev, chan); 1271 if (spur_freq == 0) { 1272 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 0, phy_idx); 1273 return; 1274 } 1275 1276 freq_diff = (spur_freq - chan->freq) * 1000000; 1277 csi_idx = s32_div_u32_round_closest(freq_diff, CARRIER_SPACING_78_125); 1278 s32_div_u32_round_down(csi_idx, MAX_TONE_NUM, &csi_tone_idx); 1279 1280 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, csi_tone_idx, phy_idx); 1281 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1, phy_idx); 1282} 1283 1284static const struct rtw89_nbi_reg_def rtw8852c_nbi_reg_def[] = { 1285 [RF_PATH_A] = { 1286 .notch1_idx = {0x4C14, 0xFF}, 1287 .notch1_frac_idx = {0x4C14, 0xC00}, 1288 .notch1_en = {0x4C14, 0x1000}, 1289 .notch2_idx = {0x4C20, 0xFF}, 1290 .notch2_frac_idx = {0x4C20, 0xC00}, 1291 .notch2_en = {0x4C20, 0x1000}, 1292 }, 1293 [RF_PATH_B] = { 1294 .notch1_idx = {0x4CD8, 0xFF}, 1295 .notch1_frac_idx = {0x4CD8, 0xC00}, 1296 .notch1_en = {0x4CD8, 0x1000}, 1297 .notch2_idx = {0x4CE4, 0xFF}, 1298 .notch2_frac_idx = {0x4CE4, 0xC00}, 1299 .notch2_en = {0x4CE4, 0x1000}, 1300 }, 1301}; 1302 1303static void rtw8852c_set_nbi_tone_idx(struct rtw89_dev *rtwdev, 1304 const struct rtw89_chan *chan, 1305 enum rtw89_rf_path path) 1306{ 1307 const struct rtw89_nbi_reg_def *nbi = &rtw8852c_nbi_reg_def[path]; 1308 u32 spur_freq, fc; 1309 s32 freq_diff; 1310 s32 nbi_idx, nbi_tone_idx; 1311 s32 nbi_frac_idx, nbi_frac_tone_idx; 1312 bool notch2_chk = false; 1313 1314 spur_freq = rtw8852c_spur_freq(rtwdev, chan); 1315 if (spur_freq == 0) { 1316 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1317 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1318 return; 1319 } 1320 1321 fc = chan->freq; 1322 if (chan->band_width == RTW89_CHANNEL_WIDTH_160) { 1323 fc = (spur_freq > fc) ? fc + 40 : fc - 40; 1324 if ((fc > spur_freq && 1325 chan->channel < chan->primary_channel) || 1326 (fc < spur_freq && 1327 chan->channel > chan->primary_channel)) 1328 notch2_chk = true; 1329 } 1330 1331 freq_diff = (spur_freq - fc) * 1000000; 1332 nbi_idx = s32_div_u32_round_down(freq_diff, CARRIER_SPACING_312_5, &nbi_frac_idx); 1333 1334 if (chan->band_width == RTW89_CHANNEL_WIDTH_20) { 1335 s32_div_u32_round_down(nbi_idx + 32, 64, &nbi_tone_idx); 1336 } else { 1337 u16 tone_para = (chan->band_width == RTW89_CHANNEL_WIDTH_40) ? 1338 128 : 256; 1339 1340 s32_div_u32_round_down(nbi_idx, tone_para, &nbi_tone_idx); 1341 } 1342 nbi_frac_tone_idx = s32_div_u32_round_closest(nbi_frac_idx, CARRIER_SPACING_78_125); 1343 1344 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && notch2_chk) { 1345 rtw89_phy_write32_mask(rtwdev, nbi->notch2_idx.addr, 1346 nbi->notch2_idx.mask, nbi_tone_idx); 1347 rtw89_phy_write32_mask(rtwdev, nbi->notch2_frac_idx.addr, 1348 nbi->notch2_frac_idx.mask, nbi_frac_tone_idx); 1349 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 0); 1350 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 1); 1351 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1352 } else { 1353 rtw89_phy_write32_mask(rtwdev, nbi->notch1_idx.addr, 1354 nbi->notch1_idx.mask, nbi_tone_idx); 1355 rtw89_phy_write32_mask(rtwdev, nbi->notch1_frac_idx.addr, 1356 nbi->notch1_frac_idx.mask, nbi_frac_tone_idx); 1357 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1358 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 1); 1359 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 0); 1360 } 1361} 1362 1363static void rtw8852c_spur_notch(struct rtw89_dev *rtwdev, u32 val, 1364 enum rtw89_phy_idx phy_idx) 1365{ 1366 u32 notch; 1367 u32 notch2; 1368 1369 if (phy_idx == RTW89_PHY_0) { 1370 notch = R_PATH0_NOTCH; 1371 notch2 = R_PATH0_NOTCH2; 1372 } else { 1373 notch = R_PATH1_NOTCH; 1374 notch2 = R_PATH1_NOTCH2; 1375 } 1376 1377 rtw89_phy_write32_mask(rtwdev, notch, 1378 B_PATH0_NOTCH_VAL | B_PATH0_NOTCH_EN, val); 1379 rtw89_phy_write32_set(rtwdev, notch, B_PATH0_NOTCH_EN); 1380 rtw89_phy_write32_mask(rtwdev, notch2, 1381 B_PATH0_NOTCH2_VAL | B_PATH0_NOTCH2_EN, val); 1382 rtw89_phy_write32_set(rtwdev, notch2, B_PATH0_NOTCH2_EN); 1383} 1384 1385static void rtw8852c_spur_elimination(struct rtw89_dev *rtwdev, 1386 const struct rtw89_chan *chan, 1387 u8 pri_ch_idx, 1388 enum rtw89_phy_idx phy_idx) 1389{ 1390 rtw8852c_set_csi_tone_idx(rtwdev, chan, phy_idx); 1391 1392 if (phy_idx == RTW89_PHY_0) { 1393 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1394 (pri_ch_idx == RTW89_SC_20_LOWER || 1395 pri_ch_idx == RTW89_SC_20_UP3X)) { 1396 rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_0); 1397 if (!rtwdev->dbcc_en) 1398 rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_1); 1399 } else if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1400 (pri_ch_idx == RTW89_SC_20_UPPER || 1401 pri_ch_idx == RTW89_SC_20_LOW3X)) { 1402 rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_0); 1403 if (!rtwdev->dbcc_en) 1404 rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_1); 1405 } else { 1406 rtw8852c_set_nbi_tone_idx(rtwdev, chan, RF_PATH_A); 1407 if (!rtwdev->dbcc_en) 1408 rtw8852c_set_nbi_tone_idx(rtwdev, chan, 1409 RF_PATH_B); 1410 } 1411 } else { 1412 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1413 (pri_ch_idx == RTW89_SC_20_LOWER || 1414 pri_ch_idx == RTW89_SC_20_UP3X)) { 1415 rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_1); 1416 } else if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1417 (pri_ch_idx == RTW89_SC_20_UPPER || 1418 pri_ch_idx == RTW89_SC_20_LOW3X)) { 1419 rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_1); 1420 } else { 1421 rtw8852c_set_nbi_tone_idx(rtwdev, chan, RF_PATH_B); 1422 } 1423 } 1424 1425 if (pri_ch_idx == RTW89_SC_20_UP3X || pri_ch_idx == RTW89_SC_20_LOW3X) 1426 rtw89_phy_write32_idx(rtwdev, R_PD_BOOST_EN, B_PD_BOOST_EN, 0, phy_idx); 1427 else 1428 rtw89_phy_write32_idx(rtwdev, R_PD_BOOST_EN, B_PD_BOOST_EN, 1, phy_idx); 1429} 1430 1431static void rtw8852c_5m_mask(struct rtw89_dev *rtwdev, 1432 const struct rtw89_chan *chan, 1433 enum rtw89_phy_idx phy_idx) 1434{ 1435 u8 pri_ch = chan->pri_ch_idx; 1436 bool mask_5m_low; 1437 bool mask_5m_en; 1438 1439 switch (chan->band_width) { 1440 case RTW89_CHANNEL_WIDTH_40: 1441 mask_5m_en = true; 1442 mask_5m_low = pri_ch == RTW89_SC_20_LOWER; 1443 break; 1444 case RTW89_CHANNEL_WIDTH_80: 1445 mask_5m_en = pri_ch == RTW89_SC_20_UPMOST || 1446 pri_ch == RTW89_SC_20_LOWEST; 1447 mask_5m_low = pri_ch == RTW89_SC_20_LOWEST; 1448 break; 1449 default: 1450 mask_5m_en = false; 1451 mask_5m_low = false; 1452 break; 1453 } 1454 1455 if (!mask_5m_en) { 1456 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x0); 1457 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x0); 1458 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT, 1459 B_ASSIGN_SBD_OPT_EN, 0x0, phy_idx); 1460 } else { 1461 if (mask_5m_low) { 1462 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_TH, 0x4); 1463 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x1); 1464 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB2, 0x0); 1465 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB0, 0x1); 1466 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_TH, 0x4); 1467 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x1); 1468 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB2, 0x0); 1469 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB0, 0x1); 1470 } else { 1471 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_TH, 0x4); 1472 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x1); 1473 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB2, 0x1); 1474 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB0, 0x0); 1475 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_TH, 0x4); 1476 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x1); 1477 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB2, 0x1); 1478 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB0, 0x0); 1479 } 1480 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT, B_ASSIGN_SBD_OPT_EN, 0x1, phy_idx); 1481 } 1482} 1483 1484static void rtw8852c_bb_reset_all(struct rtw89_dev *rtwdev, 1485 enum rtw89_phy_idx phy_idx) 1486{ 1487 /*HW SI reset*/ 1488 rtw89_phy_write32_mask(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 1489 0x7); 1490 rtw89_phy_write32_mask(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, 1491 0x7); 1492 1493 udelay(1); 1494 1495 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1496 phy_idx); 1497 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, 1498 phy_idx); 1499 /*HW SI reset*/ 1500 rtw89_phy_write32_mask(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 1501 0x0); 1502 rtw89_phy_write32_mask(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, 1503 0x0); 1504 1505 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1506 phy_idx); 1507} 1508 1509static void rtw8852c_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band, 1510 enum rtw89_phy_idx phy_idx, bool en) 1511{ 1512 if (en) { 1513 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, 1514 B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 1515 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, 1516 B_S1_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 1517 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1518 phy_idx); 1519 if (band == RTW89_BAND_2G) 1520 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0x0); 1521 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0); 1522 } else { 1523 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0x1); 1524 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1); 1525 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, 1526 B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 1527 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, 1528 B_S1_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 1529 fsleep(1); 1530 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, 1531 phy_idx); 1532 } 1533} 1534 1535static void rtw8852c_bb_reset(struct rtw89_dev *rtwdev, 1536 enum rtw89_phy_idx phy_idx) 1537{ 1538 rtw8852c_bb_reset_all(rtwdev, phy_idx); 1539} 1540 1541static 1542void rtw8852c_bb_gpio_trsw(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, 1543 u8 tx_path_en, u8 trsw_tx, 1544 u8 trsw_rx, u8 trsw, u8 trsw_b) 1545{ 1546 static const u32 path_cr_bases[] = {0x5868, 0x7868}; 1547 u32 mask_ofst = 16; 1548 u32 cr; 1549 u32 val; 1550 1551 if (path >= ARRAY_SIZE(path_cr_bases)) 1552 return; 1553 1554 cr = path_cr_bases[path]; 1555 1556 mask_ofst += (tx_path_en * 4 + trsw_tx * 2 + trsw_rx) * 2; 1557 val = FIELD_PREP(B_P0_TRSW_A, trsw) | FIELD_PREP(B_P0_TRSW_B, trsw_b); 1558 1559 rtw89_phy_write32_mask(rtwdev, cr, (B_P0_TRSW_A | B_P0_TRSW_B) << mask_ofst, val); 1560} 1561 1562enum rtw8852c_rfe_src { 1563 PAPE_RFM, 1564 TRSW_RFM, 1565 LNAON_RFM, 1566}; 1567 1568static 1569void rtw8852c_bb_gpio_rfm(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, 1570 enum rtw8852c_rfe_src src, u8 dis_tx_gnt_wl, 1571 u8 active_tx_opt, u8 act_bt_en, u8 rfm_output_val) 1572{ 1573 static const u32 path_cr_bases[] = {0x5894, 0x7894}; 1574 static const u32 masks[] = {0, 8, 16}; 1575 u32 mask, mask_ofst; 1576 u32 cr; 1577 u32 val; 1578 1579 if (src >= ARRAY_SIZE(masks) || path >= ARRAY_SIZE(path_cr_bases)) 1580 return; 1581 1582 mask_ofst = masks[src]; 1583 cr = path_cr_bases[path]; 1584 1585 val = FIELD_PREP(B_P0_RFM_DIS_WL, dis_tx_gnt_wl) | 1586 FIELD_PREP(B_P0_RFM_TX_OPT, active_tx_opt) | 1587 FIELD_PREP(B_P0_RFM_BT_EN, act_bt_en) | 1588 FIELD_PREP(B_P0_RFM_OUT, rfm_output_val); 1589 mask = 0xff << mask_ofst; 1590 1591 rtw89_phy_write32_mask(rtwdev, cr, mask, val); 1592} 1593 1594static void rtw8852c_bb_gpio_init(struct rtw89_dev *rtwdev) 1595{ 1596 static const u32 cr_bases[] = {0x5800, 0x7800}; 1597 u32 addr; 1598 u8 i; 1599 1600 for (i = 0; i < ARRAY_SIZE(cr_bases); i++) { 1601 addr = cr_bases[i]; 1602 rtw89_phy_write32_set(rtwdev, (addr | 0x68), B_P0_TRSW_A); 1603 rtw89_phy_write32_clr(rtwdev, (addr | 0x68), B_P0_TRSW_X); 1604 rtw89_phy_write32_clr(rtwdev, (addr | 0x68), B_P0_TRSW_SO_A2); 1605 rtw89_phy_write32(rtwdev, (addr | 0x80), 0x77777777); 1606 rtw89_phy_write32(rtwdev, (addr | 0x84), 0x77777777); 1607 } 1608 1609 rtw89_phy_write32(rtwdev, R_RFE_E_A2, 0xffffffff); 1610 rtw89_phy_write32(rtwdev, R_RFE_O_SEL_A2, 0); 1611 rtw89_phy_write32(rtwdev, R_RFE_SEL0_A2, 0); 1612 rtw89_phy_write32(rtwdev, R_RFE_SEL32_A2, 0); 1613 1614 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 0, 0, 1); 1615 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 1, 1, 0); 1616 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 0, 1, 0); 1617 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 1, 1, 0); 1618 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 0, 0, 1); 1619 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 1, 1, 0); 1620 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 0, 1, 0); 1621 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 1, 1, 0); 1622 1623 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 0, 0, 0, 1); 1624 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 0, 1, 1, 0); 1625 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 1, 0, 1, 0); 1626 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 1, 1, 1, 0); 1627 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 0, 0, 0, 1); 1628 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 0, 1, 1, 0); 1629 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 1, 0, 1, 0); 1630 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 1, 1, 1, 0); 1631 1632 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, PAPE_RFM, 0, 0, 0, 0x0); 1633 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, TRSW_RFM, 0, 0, 0, 0x4); 1634 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, LNAON_RFM, 0, 0, 0, 0x8); 1635 1636 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, PAPE_RFM, 0, 0, 0, 0x0); 1637 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, TRSW_RFM, 0, 0, 0, 0x4); 1638 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, LNAON_RFM, 0, 0, 0, 0x8); 1639} 1640 1641static void rtw8852c_bb_macid_ctrl_init(struct rtw89_dev *rtwdev, 1642 enum rtw89_phy_idx phy_idx) 1643{ 1644 u32 addr; 1645 1646 for (addr = R_AX_PWR_MACID_LMT_TABLE0; 1647 addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4) 1648 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0); 1649} 1650 1651static void rtw8852c_bb_sethw(struct rtw89_dev *rtwdev) 1652{ 1653 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; 1654 1655 rtw89_phy_write32_set(rtwdev, R_DBCC_80P80_SEL_EVM_RPT, 1656 B_DBCC_80P80_SEL_EVM_RPT_EN); 1657 rtw89_phy_write32_set(rtwdev, R_DBCC_80P80_SEL_EVM_RPT2, 1658 B_DBCC_80P80_SEL_EVM_RPT2_EN); 1659 1660 rtw8852c_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0); 1661 rtw8852c_bb_gpio_init(rtwdev); 1662 1663 /* read these registers after loading BB parameters */ 1664 gain->offset_base[RTW89_PHY_0] = 1665 rtw89_phy_read32_mask(rtwdev, R_RPL_BIAS_COMP, B_RPL_BIAS_COMP_MASK); 1666 gain->offset_base[RTW89_PHY_1] = 1667 rtw89_phy_read32_mask(rtwdev, R_RPL_BIAS_COMP1, B_RPL_BIAS_COMP1_MASK); 1668} 1669 1670static void rtw8852c_set_channel_bb(struct rtw89_dev *rtwdev, 1671 const struct rtw89_chan *chan, 1672 enum rtw89_phy_idx phy_idx) 1673{ 1674 static const u32 ru_alloc_msk[2] = {B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY0, 1675 B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY1}; 1676 struct rtw89_hal *hal = &rtwdev->hal; 1677 bool cck_en = chan->band_type == RTW89_BAND_2G; 1678 u8 pri_ch_idx = chan->pri_ch_idx; 1679 u32 mask, reg; 1680 u8 ntx_path; 1681 1682 if (chan->band_type == RTW89_BAND_2G) 1683 rtw8852c_ctrl_sco_cck(rtwdev, chan->channel, 1684 chan->primary_channel, 1685 chan->band_width); 1686 1687 rtw8852c_ctrl_ch(rtwdev, chan, phy_idx); 1688 rtw8852c_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx); 1689 if (cck_en) { 1690 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 1); 1691 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0); 1692 rtw89_phy_write32_idx(rtwdev, R_PD_ARBITER_OFF, 1693 B_PD_ARBITER_OFF, 0x0, phy_idx); 1694 } else { 1695 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0); 1696 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 1); 1697 rtw89_phy_write32_idx(rtwdev, R_PD_ARBITER_OFF, 1698 B_PD_ARBITER_OFF, 0x1, phy_idx); 1699 } 1700 1701 rtw8852c_spur_elimination(rtwdev, chan, pri_ch_idx, phy_idx); 1702 rtw8852c_ctrl_btg_bt_rx(rtwdev, chan->band_type == RTW89_BAND_2G, 1703 RTW89_PHY_0); 1704 rtw8852c_5m_mask(rtwdev, chan, phy_idx); 1705 1706 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1707 rtwdev->hal.cv != CHIP_CAV) { 1708 rtw89_phy_write32_idx(rtwdev, R_P80_AT_HIGH_FREQ, 1709 B_P80_AT_HIGH_FREQ, 0x0, phy_idx); 1710 reg = rtw89_mac_reg_by_idx(rtwdev, R_P80_AT_HIGH_FREQ_BB_WRP, phy_idx); 1711 if (chan->primary_channel > chan->channel) { 1712 rtw89_phy_write32_mask(rtwdev, 1713 R_P80_AT_HIGH_FREQ_RU_ALLOC, 1714 ru_alloc_msk[phy_idx], 1); 1715 rtw89_write32_mask(rtwdev, reg, 1716 B_P80_AT_HIGH_FREQ_BB_WRP, 1); 1717 } else { 1718 rtw89_phy_write32_mask(rtwdev, 1719 R_P80_AT_HIGH_FREQ_RU_ALLOC, 1720 ru_alloc_msk[phy_idx], 0); 1721 rtw89_write32_mask(rtwdev, reg, 1722 B_P80_AT_HIGH_FREQ_BB_WRP, 0); 1723 } 1724 } 1725 1726 if (chan->band_type == RTW89_BAND_6G && 1727 chan->band_width == RTW89_CHANNEL_WIDTH_160) 1728 rtw89_phy_write32_idx(rtwdev, R_CDD_EVM_CHK_EN, 1729 B_CDD_EVM_CHK_EN, 0, phy_idx); 1730 else 1731 rtw89_phy_write32_idx(rtwdev, R_CDD_EVM_CHK_EN, 1732 B_CDD_EVM_CHK_EN, 1, phy_idx); 1733 1734 if (!rtwdev->dbcc_en) { 1735 mask = B_P0_TXPW_RSTB_TSSI | B_P0_TXPW_RSTB_MANON; 1736 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x1); 1737 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x3); 1738 mask = B_P1_TXPW_RSTB_TSSI | B_P1_TXPW_RSTB_MANON; 1739 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x1); 1740 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x3); 1741 } else { 1742 if (phy_idx == RTW89_PHY_0) { 1743 mask = B_P0_TXPW_RSTB_TSSI | B_P0_TXPW_RSTB_MANON; 1744 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x1); 1745 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x3); 1746 } else { 1747 mask = B_P1_TXPW_RSTB_TSSI | B_P1_TXPW_RSTB_MANON; 1748 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x1); 1749 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x3); 1750 } 1751 } 1752 1753 if (chan->band_type == RTW89_BAND_6G) 1754 rtw89_phy_write32_set(rtwdev, R_MUIC, B_MUIC_EN); 1755 else 1756 rtw89_phy_write32_clr(rtwdev, R_MUIC, B_MUIC_EN); 1757 1758 if (hal->antenna_tx) 1759 ntx_path = hal->antenna_tx; 1760 else 1761 ntx_path = chan->band_type == RTW89_BAND_6G ? RF_B : RF_AB; 1762 1763 rtw8852c_ctrl_tx_path_tmac(rtwdev, ntx_path, (enum rtw89_mac_idx)phy_idx); 1764 1765 rtw8852c_bb_reset_all(rtwdev, phy_idx); 1766} 1767 1768static void rtw8852c_set_channel(struct rtw89_dev *rtwdev, 1769 const struct rtw89_chan *chan, 1770 enum rtw89_mac_idx mac_idx, 1771 enum rtw89_phy_idx phy_idx) 1772{ 1773 rtw8852c_set_channel_mac(rtwdev, chan, mac_idx); 1774 rtw8852c_set_channel_bb(rtwdev, chan, phy_idx); 1775 rtw8852c_set_channel_rf(rtwdev, chan, phy_idx); 1776} 1777 1778static void rtw8852c_dfs_en(struct rtw89_dev *rtwdev, bool en) 1779{ 1780 if (en) 1781 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 1); 1782 else 1783 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 0); 1784} 1785 1786static void rtw8852c_adc_en(struct rtw89_dev *rtwdev, bool en) 1787{ 1788 if (en) 1789 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1790 0x0); 1791 else 1792 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1793 0xf); 1794} 1795 1796static void rtw8852c_set_channel_help(struct rtw89_dev *rtwdev, bool enter, 1797 struct rtw89_channel_help_params *p, 1798 const struct rtw89_chan *chan, 1799 enum rtw89_mac_idx mac_idx, 1800 enum rtw89_phy_idx phy_idx) 1801{ 1802 if (enter) { 1803 rtw89_chip_stop_sch_tx(rtwdev, mac_idx, &p->tx_en, 1804 RTW89_SCH_TX_SEL_ALL); 1805 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, false); 1806 rtw8852c_dfs_en(rtwdev, false); 1807 rtw8852c_tssi_cont_en_phyidx(rtwdev, false, phy_idx); 1808 rtw8852c_adc_en(rtwdev, false); 1809 fsleep(40); 1810 rtw8852c_bb_reset_en(rtwdev, chan->band_type, phy_idx, false); 1811 } else { 1812 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, true); 1813 rtw8852c_adc_en(rtwdev, true); 1814 rtw8852c_dfs_en(rtwdev, true); 1815 rtw8852c_tssi_cont_en_phyidx(rtwdev, true, phy_idx); 1816 rtw8852c_bb_reset_en(rtwdev, chan->band_type, phy_idx, true); 1817 rtw89_chip_resume_sch_tx(rtwdev, mac_idx, p->tx_en); 1818 } 1819} 1820 1821static void rtw8852c_rfk_init(struct rtw89_dev *rtwdev) 1822{ 1823 struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc; 1824 1825 rtwdev->is_tssi_mode[RF_PATH_A] = false; 1826 rtwdev->is_tssi_mode[RF_PATH_B] = false; 1827 memset(rfk_mcc, 0, sizeof(*rfk_mcc)); 1828 rtw8852c_lck_init(rtwdev); 1829 rtw8852c_dpk_init(rtwdev); 1830 1831 rtw8852c_rck(rtwdev); 1832 rtw8852c_dack(rtwdev); 1833 rtw8852c_rx_dck(rtwdev, RTW89_PHY_0, false); 1834} 1835 1836static void rtw8852c_rfk_channel(struct rtw89_dev *rtwdev) 1837{ 1838 enum rtw89_phy_idx phy_idx = RTW89_PHY_0; 1839 1840 rtw8852c_mcc_get_ch_info(rtwdev, phy_idx); 1841 rtw8852c_rx_dck(rtwdev, phy_idx, false); 1842 rtw8852c_iqk(rtwdev, phy_idx); 1843 rtw8852c_tssi(rtwdev, phy_idx); 1844 rtw8852c_dpk(rtwdev, phy_idx); 1845 rtw89_fw_h2c_rf_ntfy_mcc(rtwdev); 1846} 1847 1848static void rtw8852c_rfk_band_changed(struct rtw89_dev *rtwdev, 1849 enum rtw89_phy_idx phy_idx) 1850{ 1851 rtw8852c_tssi_scan(rtwdev, phy_idx); 1852} 1853 1854static void rtw8852c_rfk_scan(struct rtw89_dev *rtwdev, bool start) 1855{ 1856 rtw8852c_wifi_scan_notify(rtwdev, start, RTW89_PHY_0); 1857} 1858 1859static void rtw8852c_rfk_track(struct rtw89_dev *rtwdev) 1860{ 1861 rtw8852c_dpk_track(rtwdev); 1862 rtw8852c_lck_track(rtwdev); 1863 rtw8852c_rx_dck_track(rtwdev); 1864} 1865 1866static u32 rtw8852c_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev, 1867 enum rtw89_phy_idx phy_idx, s16 ref) 1868{ 1869 s8 ofst_int = 0; 1870 u8 base_cw_0db = 0x27; 1871 u16 tssi_16dbm_cw = 0x12c; 1872 s16 pwr_s10_3 = 0; 1873 s16 rf_pwr_cw = 0; 1874 u16 bb_pwr_cw = 0; 1875 u32 pwr_cw = 0; 1876 u32 tssi_ofst_cw = 0; 1877 1878 pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3); 1879 bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3); 1880 rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3); 1881 rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63); 1882 pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw; 1883 1884 tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3)); 1885 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1886 "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n", 1887 tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw); 1888 1889 return (tssi_ofst_cw << 18) | (pwr_cw << 9) | (ref & GENMASK(8, 0)); 1890} 1891 1892static 1893void rtw8852c_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 1894 s8 pw_ofst, enum rtw89_mac_idx mac_idx) 1895{ 1896 s8 pw_ofst_2tx; 1897 s8 val_1t; 1898 s8 val_2t; 1899 u32 reg; 1900 u8 i; 1901 1902 if (pw_ofst < -32 || pw_ofst > 31) { 1903 rtw89_warn(rtwdev, "[ULTB] Err pwr_offset=%d\n", pw_ofst); 1904 return; 1905 } 1906 val_1t = pw_ofst << 2; 1907 pw_ofst_2tx = max(pw_ofst - 3, -32); 1908 val_2t = pw_ofst_2tx << 2; 1909 1910 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] val_1tx=0x%x\n", val_1t); 1911 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] val_2tx=0x%x\n", val_2t); 1912 1913 for (i = 0; i < 4; i++) { 1914 /* 1TX */ 1915 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, mac_idx); 1916 rtw89_write32_mask(rtwdev, reg, 1917 B_AX_PWR_UL_TB_1T_V1_MASK << (8 * i), 1918 val_1t); 1919 /* 2TX */ 1920 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, mac_idx); 1921 rtw89_write32_mask(rtwdev, reg, 1922 B_AX_PWR_UL_TB_2T_V1_MASK << (8 * i), 1923 val_2t); 1924 } 1925} 1926 1927static void rtw8852c_set_txpwr_ref(struct rtw89_dev *rtwdev, 1928 enum rtw89_phy_idx phy_idx) 1929{ 1930 static const u32 addr[RF_PATH_NUM_8852C] = {0x5800, 0x7800}; 1931 const u32 mask = 0x7FFFFFF; 1932 const u8 ofst_ofdm = 0x4; 1933 const u8 ofst_cck = 0x8; 1934 s16 ref_ofdm = 0; 1935 s16 ref_cck = 0; 1936 u32 val; 1937 u8 i; 1938 1939 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n"); 1940 1941 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL, 1942 GENMASK(27, 10), 0x0); 1943 1944 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n"); 1945 val = rtw8852c_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm); 1946 1947 for (i = 0; i < RF_PATH_NUM_8852C; i++) 1948 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val, 1949 phy_idx); 1950 1951 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n"); 1952 val = rtw8852c_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck); 1953 1954 for (i = 0; i < RF_PATH_NUM_8852C; i++) 1955 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val, 1956 phy_idx); 1957} 1958 1959static void rtw8852c_bb_set_tx_shape_dfir(struct rtw89_dev *rtwdev, 1960 const struct rtw89_chan *chan, 1961 u8 tx_shape_idx, 1962 enum rtw89_phy_idx phy_idx) 1963{ 1964#define __DFIR_CFG_MASK 0xffffff 1965#define __DFIR_CFG_NR 8 1966#define __DECL_DFIR_VAR(_prefix, _name, _val...) \ 1967 static const u32 _prefix ## _ ## _name[] = {_val}; \ 1968 static_assert(ARRAY_SIZE(_prefix ## _ ## _name) == __DFIR_CFG_NR) 1969#define __DECL_DFIR_PARAM(_name, _val...) __DECL_DFIR_VAR(param, _name, _val) 1970#define __DECL_DFIR_ADDR(_name, _val...) __DECL_DFIR_VAR(addr, _name, _val) 1971 1972 __DECL_DFIR_PARAM(flat, 1973 0x003D23FF, 0x0029B354, 0x000FC1C8, 0x00FDB053, 1974 0x00F86F9A, 0x00FAEF92, 0x00FE5FCC, 0x00FFDFF5); 1975 __DECL_DFIR_PARAM(sharp, 1976 0x003D83FF, 0x002C636A, 0x0013F204, 0x00008090, 1977 0x00F87FB0, 0x00F99F83, 0x00FDBFBA, 0x00003FF5); 1978 __DECL_DFIR_PARAM(sharp_14, 1979 0x003B13FF, 0x001C42DE, 0x00FDB0AD, 0x00F60F6E, 1980 0x00FD8F92, 0x0002D011, 0x0001C02C, 0x00FFF00A); 1981 __DECL_DFIR_ADDR(filter, 1982 0x45BC, 0x45CC, 0x45D0, 0x45D4, 0x45D8, 0x45C0, 1983 0x45C4, 0x45C8); 1984 u8 ch = chan->channel; 1985 const u32 *param; 1986 int i; 1987 1988 if (ch > 14) { 1989 rtw89_warn(rtwdev, 1990 "set tx shape dfir by unknown ch: %d on 2G\n", ch); 1991 return; 1992 } 1993 1994 if (ch == 14) 1995 param = param_sharp_14; 1996 else 1997 param = tx_shape_idx == 0 ? param_flat : param_sharp; 1998 1999 for (i = 0; i < __DFIR_CFG_NR; i++) { 2000 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2001 "set tx shape dfir: 0x%x: 0x%x\n", addr_filter[i], 2002 param[i]); 2003 rtw89_phy_write32_idx(rtwdev, addr_filter[i], __DFIR_CFG_MASK, 2004 param[i], phy_idx); 2005 } 2006 2007#undef __DECL_DFIR_ADDR 2008#undef __DECL_DFIR_PARAM 2009#undef __DECL_DFIR_VAR 2010#undef __DFIR_CFG_NR 2011#undef __DFIR_CFG_MASK 2012} 2013 2014static void rtw8852c_set_tx_shape(struct rtw89_dev *rtwdev, 2015 const struct rtw89_chan *chan, 2016 enum rtw89_phy_idx phy_idx) 2017{ 2018 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms; 2019 u8 band = chan->band_type; 2020 u8 regd = rtw89_regd_get(rtwdev, band); 2021 u8 tx_shape_cck = (*rfe_parms->tx_shape.lmt)[band][RTW89_RS_CCK][regd]; 2022 u8 tx_shape_ofdm = (*rfe_parms->tx_shape.lmt)[band][RTW89_RS_OFDM][regd]; 2023 2024 if (band == RTW89_BAND_2G) 2025 rtw8852c_bb_set_tx_shape_dfir(rtwdev, chan, tx_shape_cck, phy_idx); 2026 2027 rtw89_phy_tssi_ctrl_set_bandedge_cfg(rtwdev, 2028 (enum rtw89_mac_idx)phy_idx, 2029 tx_shape_ofdm); 2030 2031 rtw89_phy_write32_set(rtwdev, R_P0_DAC_COMP_POST_DPD_EN, 2032 B_P0_DAC_COMP_POST_DPD_EN); 2033 rtw89_phy_write32_set(rtwdev, R_P1_DAC_COMP_POST_DPD_EN, 2034 B_P1_DAC_COMP_POST_DPD_EN); 2035} 2036 2037static void rtw8852c_set_txpwr(struct rtw89_dev *rtwdev, 2038 const struct rtw89_chan *chan, 2039 enum rtw89_phy_idx phy_idx) 2040{ 2041 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx); 2042 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx); 2043 rtw8852c_set_tx_shape(rtwdev, chan, phy_idx); 2044 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx); 2045 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx); 2046} 2047 2048static void rtw8852c_set_txpwr_ctrl(struct rtw89_dev *rtwdev, 2049 enum rtw89_phy_idx phy_idx) 2050{ 2051 rtw8852c_set_txpwr_ref(rtwdev, phy_idx); 2052} 2053 2054static void 2055rtw8852c_init_tssi_ctrl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 2056{ 2057 static const struct rtw89_reg2_def ctrl_ini[] = { 2058 {0xD938, 0x00010100}, 2059 {0xD93C, 0x0500D500}, 2060 {0xD940, 0x00000500}, 2061 {0xD944, 0x00000005}, 2062 {0xD94C, 0x00220000}, 2063 {0xD950, 0x00030000}, 2064 }; 2065 u32 addr; 2066 int i; 2067 2068 for (addr = R_AX_TSSI_CTRL_HEAD; addr <= R_AX_TSSI_CTRL_TAIL; addr += 4) 2069 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0); 2070 2071 for (i = 0; i < ARRAY_SIZE(ctrl_ini); i++) 2072 rtw89_mac_txpwr_write32(rtwdev, phy_idx, ctrl_ini[i].addr, 2073 ctrl_ini[i].data); 2074 2075 rtw89_phy_tssi_ctrl_set_bandedge_cfg(rtwdev, 2076 (enum rtw89_mac_idx)phy_idx, 2077 RTW89_TSSI_BANDEDGE_FLAT); 2078} 2079 2080static int 2081rtw8852c_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 2082{ 2083 int ret; 2084 2085 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333); 2086 if (ret) 2087 return ret; 2088 2089 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf000); 2090 if (ret) 2091 return ret; 2092 2093 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff); 2094 if (ret) 2095 return ret; 2096 2097 rtw8852c_set_txpwr_ul_tb_offset(rtwdev, 0, phy_idx == RTW89_PHY_1 ? 2098 RTW89_MAC_1 : 2099 RTW89_MAC_0); 2100 rtw8852c_init_tssi_ctrl(rtwdev, phy_idx); 2101 2102 return 0; 2103} 2104 2105static void rtw8852c_bb_cfg_rx_path(struct rtw89_dev *rtwdev, u8 rx_path) 2106{ 2107 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 2108 u8 band = chan->band_type; 2109 u32 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI; 2110 u32 rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI; 2111 2112 if (rtwdev->dbcc_en) { 2113 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_ANT_RX_SEG0, 1); 2114 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_ANT_RX_SEG0, 2, 2115 RTW89_PHY_1); 2116 2117 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG0, 2118 1); 2119 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG1, 2120 1); 2121 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG0, 2, 2122 RTW89_PHY_1); 2123 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG1, 2, 2124 RTW89_PHY_1); 2125 2126 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 2127 B_RXHT_MCS_LIMIT, 0); 2128 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 2129 B_RXVHT_MCS_LIMIT, 0); 2130 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 8); 2131 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0); 2132 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0); 2133 2134 rtw89_phy_write32_idx(rtwdev, R_RXHT_MCS_LIMIT, 2135 B_RXHT_MCS_LIMIT, 0, RTW89_PHY_1); 2136 rtw89_phy_write32_idx(rtwdev, R_RXVHT_MCS_LIMIT, 2137 B_RXVHT_MCS_LIMIT, 0, RTW89_PHY_1); 2138 rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHE_USER_MAX, 1, 2139 RTW89_PHY_1); 2140 rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0, 2141 RTW89_PHY_1); 2142 rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0, 2143 RTW89_PHY_1); 2144 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1); 2145 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3); 2146 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1); 2147 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3); 2148 } else { 2149 if (rx_path == RF_PATH_A) { 2150 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, 2151 B_ANT_RX_SEG0, 1); 2152 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2153 B_ANT_RX_1RCCA_SEG0, 1); 2154 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2155 B_ANT_RX_1RCCA_SEG1, 1); 2156 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 2157 B_RXHT_MCS_LIMIT, 0); 2158 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 2159 B_RXVHT_MCS_LIMIT, 0); 2160 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 2161 0); 2162 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 2163 0); 2164 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 2165 rst_mask0, 1); 2166 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 2167 rst_mask0, 3); 2168 } else if (rx_path == RF_PATH_B) { 2169 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, 2170 B_ANT_RX_SEG0, 2); 2171 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2172 B_ANT_RX_1RCCA_SEG0, 2); 2173 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2174 B_ANT_RX_1RCCA_SEG1, 2); 2175 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 2176 B_RXHT_MCS_LIMIT, 0); 2177 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 2178 B_RXVHT_MCS_LIMIT, 0); 2179 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 2180 0); 2181 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 2182 0); 2183 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 2184 rst_mask1, 1); 2185 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 2186 rst_mask1, 3); 2187 } else { 2188 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, 2189 B_ANT_RX_SEG0, 3); 2190 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2191 B_ANT_RX_1RCCA_SEG0, 3); 2192 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2193 B_ANT_RX_1RCCA_SEG1, 3); 2194 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 2195 B_RXHT_MCS_LIMIT, 1); 2196 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 2197 B_RXVHT_MCS_LIMIT, 1); 2198 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 2199 1); 2200 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 2201 1); 2202 rtw8852c_ctrl_btg_bt_rx(rtwdev, band == RTW89_BAND_2G, 2203 RTW89_PHY_0); 2204 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 2205 rst_mask0, 1); 2206 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 2207 rst_mask0, 3); 2208 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 2209 rst_mask1, 1); 2210 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 2211 rst_mask1, 3); 2212 } 2213 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 8); 2214 } 2215} 2216 2217static void rtw8852c_ctrl_tx_path_tmac(struct rtw89_dev *rtwdev, u8 tx_path, 2218 enum rtw89_mac_idx mac_idx) 2219{ 2220 struct rtw89_reg2_def path_com[] = { 2221 {R_AX_PATH_COM0, AX_PATH_COM0_DFVAL}, 2222 {R_AX_PATH_COM1, AX_PATH_COM1_DFVAL}, 2223 {R_AX_PATH_COM2, AX_PATH_COM2_DFVAL}, 2224 {R_AX_PATH_COM3, AX_PATH_COM3_DFVAL}, 2225 {R_AX_PATH_COM4, AX_PATH_COM4_DFVAL}, 2226 {R_AX_PATH_COM5, AX_PATH_COM5_DFVAL}, 2227 {R_AX_PATH_COM6, AX_PATH_COM6_DFVAL}, 2228 {R_AX_PATH_COM7, AX_PATH_COM7_DFVAL}, 2229 {R_AX_PATH_COM8, AX_PATH_COM8_DFVAL}, 2230 {R_AX_PATH_COM9, AX_PATH_COM9_DFVAL}, 2231 {R_AX_PATH_COM10, AX_PATH_COM10_DFVAL}, 2232 {R_AX_PATH_COM11, AX_PATH_COM11_DFVAL}, 2233 }; 2234 u32 addr; 2235 u32 reg; 2236 u8 cr_size = ARRAY_SIZE(path_com); 2237 u8 i = 0; 2238 2239 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, RTW89_PHY_0); 2240 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, RTW89_PHY_1); 2241 2242 for (addr = R_AX_MACID_ANT_TABLE; 2243 addr <= R_AX_MACID_ANT_TABLE_LAST; addr += 4) { 2244 reg = rtw89_mac_reg_by_idx(rtwdev, addr, mac_idx); 2245 rtw89_write32(rtwdev, reg, 0); 2246 } 2247 2248 if (tx_path == RF_A) { 2249 path_com[0].data = AX_PATH_COM0_PATHA; 2250 path_com[1].data = AX_PATH_COM1_PATHA; 2251 path_com[2].data = AX_PATH_COM2_PATHA; 2252 path_com[7].data = AX_PATH_COM7_PATHA; 2253 path_com[8].data = AX_PATH_COM8_PATHA; 2254 } else if (tx_path == RF_B) { 2255 path_com[0].data = AX_PATH_COM0_PATHB; 2256 path_com[1].data = AX_PATH_COM1_PATHB; 2257 path_com[2].data = AX_PATH_COM2_PATHB; 2258 path_com[7].data = AX_PATH_COM7_PATHB; 2259 path_com[8].data = AX_PATH_COM8_PATHB; 2260 } else if (tx_path == RF_AB) { 2261 path_com[0].data = AX_PATH_COM0_PATHAB; 2262 path_com[1].data = AX_PATH_COM1_PATHAB; 2263 path_com[2].data = AX_PATH_COM2_PATHAB; 2264 path_com[7].data = AX_PATH_COM7_PATHAB; 2265 path_com[8].data = AX_PATH_COM8_PATHAB; 2266 } else { 2267 rtw89_warn(rtwdev, "[Invalid Tx Path]Tx Path: %d\n", tx_path); 2268 return; 2269 } 2270 2271 for (i = 0; i < cr_size; i++) { 2272 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "0x%x = 0x%x\n", 2273 path_com[i].addr, path_com[i].data); 2274 reg = rtw89_mac_reg_by_idx(rtwdev, path_com[i].addr, mac_idx); 2275 rtw89_write32(rtwdev, reg, path_com[i].data); 2276 } 2277} 2278 2279static void rtw8852c_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 2280 enum rtw89_phy_idx phy_idx) 2281{ 2282 if (en) { 2283 rtw89_phy_write32_mask(rtwdev, R_PATH0_FRC_FIR_TYPE_V1, 2284 B_PATH0_FRC_FIR_TYPE_MSK_V1, 0x3); 2285 rtw89_phy_write32_mask(rtwdev, R_PATH1_FRC_FIR_TYPE_V1, 2286 B_PATH1_FRC_FIR_TYPE_MSK_V1, 0x3); 2287 rtw89_phy_write32_mask(rtwdev, R_PATH0_RXBB_V1, 2288 B_PATH0_RXBB_MSK_V1, 0xf); 2289 rtw89_phy_write32_mask(rtwdev, R_PATH1_RXBB_V1, 2290 B_PATH1_RXBB_MSK_V1, 0xf); 2291 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1, 2292 B_PATH0_G_LNA6_OP1DB_V1, 0x80); 2293 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 2294 B_PATH1_G_LNA6_OP1DB_V1, 0x80); 2295 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1, 2296 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x80); 2297 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA1_LNA6_OP1DB_V1, 2298 B_PATH0_G_TIA1_LNA6_OP1DB_V1, 0x80); 2299 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 2300 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x80); 2301 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA1_LNA6_OP1DB_V1, 2302 B_PATH1_G_TIA1_LNA6_OP1DB_V1, 0x80); 2303 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_BACKOFF_V1, 2304 B_PATH0_BT_BACKOFF_V1, 0x780D1E); 2305 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_BACKOFF_V1, 2306 B_PATH1_BT_BACKOFF_V1, 0x780D1E); 2307 rtw89_phy_write32_mask(rtwdev, R_P0_BACKOFF_IBADC_V1, 2308 B_P0_BACKOFF_IBADC_V1, 0x34); 2309 rtw89_phy_write32_mask(rtwdev, R_P1_BACKOFF_IBADC_V1, 2310 B_P1_BACKOFF_IBADC_V1, 0x34); 2311 } else { 2312 rtw89_phy_write32_mask(rtwdev, R_PATH0_FRC_FIR_TYPE_V1, 2313 B_PATH0_FRC_FIR_TYPE_MSK_V1, 0x0); 2314 rtw89_phy_write32_mask(rtwdev, R_PATH1_FRC_FIR_TYPE_V1, 2315 B_PATH1_FRC_FIR_TYPE_MSK_V1, 0x0); 2316 rtw89_phy_write32_mask(rtwdev, R_PATH0_RXBB_V1, 2317 B_PATH0_RXBB_MSK_V1, 0x60); 2318 rtw89_phy_write32_mask(rtwdev, R_PATH1_RXBB_V1, 2319 B_PATH1_RXBB_MSK_V1, 0x60); 2320 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1, 2321 B_PATH0_G_LNA6_OP1DB_V1, 0x1a); 2322 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 2323 B_PATH1_G_LNA6_OP1DB_V1, 0x1a); 2324 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1, 2325 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x2a); 2326 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA1_LNA6_OP1DB_V1, 2327 B_PATH0_G_TIA1_LNA6_OP1DB_V1, 0x2a); 2328 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 2329 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x2a); 2330 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA1_LNA6_OP1DB_V1, 2331 B_PATH1_G_TIA1_LNA6_OP1DB_V1, 0x2a); 2332 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_BACKOFF_V1, 2333 B_PATH0_BT_BACKOFF_V1, 0x79E99E); 2334 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_BACKOFF_V1, 2335 B_PATH1_BT_BACKOFF_V1, 0x79E99E); 2336 rtw89_phy_write32_mask(rtwdev, R_P0_BACKOFF_IBADC_V1, 2337 B_P0_BACKOFF_IBADC_V1, 0x26); 2338 rtw89_phy_write32_mask(rtwdev, R_P1_BACKOFF_IBADC_V1, 2339 B_P1_BACKOFF_IBADC_V1, 0x26); 2340 } 2341} 2342 2343static void rtw8852c_bb_cfg_txrx_path(struct rtw89_dev *rtwdev) 2344{ 2345 struct rtw89_hal *hal = &rtwdev->hal; 2346 2347 rtw8852c_bb_cfg_rx_path(rtwdev, RF_PATH_AB); 2348 2349 if (hal->rx_nss == 1) { 2350 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0); 2351 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0); 2352 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0); 2353 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0); 2354 } else { 2355 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 1); 2356 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 1); 2357 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 1); 2358 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 1); 2359 } 2360} 2361 2362static u8 rtw8852c_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path) 2363{ 2364 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 2365 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0); 2366 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 2367 2368 fsleep(200); 2369 2370 return rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL); 2371} 2372 2373static void rtw8852c_btc_set_rfe(struct rtw89_dev *rtwdev) 2374{ 2375 const struct rtw89_btc_ver *ver = rtwdev->btc.ver; 2376 union rtw89_btc_module_info *md = &rtwdev->btc.mdinfo; 2377 2378 if (ver->fcxinit == 7) { 2379 md->md_v7.rfe_type = rtwdev->efuse.rfe_type; 2380 md->md_v7.kt_ver = rtwdev->hal.cv; 2381 md->md_v7.bt_solo = 0; 2382 md->md_v7.switch_type = BTC_SWITCH_INTERNAL; 2383 2384 if (md->md_v7.rfe_type > 0) 2385 md->md_v7.ant.num = (md->md_v7.rfe_type % 2 ? 2 : 3); 2386 else 2387 md->md_v7.ant.num = 2; 2388 2389 md->md_v7.ant.diversity = 0; 2390 md->md_v7.ant.isolation = 10; 2391 2392 if (md->md_v7.ant.num == 3) { 2393 md->md_v7.ant.type = BTC_ANT_DEDICATED; 2394 md->md_v7.bt_pos = BTC_BT_ALONE; 2395 } else { 2396 md->md_v7.ant.type = BTC_ANT_SHARED; 2397 md->md_v7.bt_pos = BTC_BT_BTG; 2398 } 2399 rtwdev->btc.btg_pos = md->md_v7.ant.btg_pos; 2400 rtwdev->btc.ant_type = md->md_v7.ant.type; 2401 } else { 2402 md->md.rfe_type = rtwdev->efuse.rfe_type; 2403 md->md.cv = rtwdev->hal.cv; 2404 md->md.bt_solo = 0; 2405 md->md.switch_type = BTC_SWITCH_INTERNAL; 2406 2407 if (md->md.rfe_type > 0) 2408 md->md.ant.num = (md->md.rfe_type % 2 ? 2 : 3); 2409 else 2410 md->md.ant.num = 2; 2411 2412 md->md.ant.diversity = 0; 2413 md->md.ant.isolation = 10; 2414 2415 if (md->md.ant.num == 3) { 2416 md->md.ant.type = BTC_ANT_DEDICATED; 2417 md->md.bt_pos = BTC_BT_ALONE; 2418 } else { 2419 md->md.ant.type = BTC_ANT_SHARED; 2420 md->md.bt_pos = BTC_BT_BTG; 2421 } 2422 rtwdev->btc.btg_pos = md->md.ant.btg_pos; 2423 rtwdev->btc.ant_type = md->md.ant.type; 2424 } 2425} 2426 2427static void rtw8852c_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 2428 enum rtw89_phy_idx phy_idx) 2429{ 2430 if (en) { 2431 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, 2432 B_PATH0_BT_SHARE_V1, 0x1); 2433 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, 2434 B_PATH0_BTG_PATH_V1, 0x0); 2435 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 2436 B_PATH1_G_LNA6_OP1DB_V1, 0x20); 2437 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 2438 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x30); 2439 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1, 2440 B_PATH1_BT_SHARE_V1, 0x1); 2441 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1, 2442 B_PATH1_BTG_PATH_V1, 0x1); 2443 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0); 2444 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_BT_SHARE, 0x1); 2445 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_BT_SEG0, 0x2); 2446 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN, 2447 B_BT_DYN_DC_EST_EN_MSK, 0x1); 2448 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 2449 0x1); 2450 } else { 2451 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, 2452 B_PATH0_BT_SHARE_V1, 0x0); 2453 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, 2454 B_PATH0_BTG_PATH_V1, 0x0); 2455 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 2456 B_PATH1_G_LNA6_OP1DB_V1, 0x1a); 2457 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 2458 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x2a); 2459 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1, 2460 B_PATH1_BT_SHARE_V1, 0x0); 2461 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1, 2462 B_PATH1_BTG_PATH_V1, 0x0); 2463 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xf); 2464 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P2, 0x4); 2465 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_BT_SHARE, 0x0); 2466 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_BT_SEG0, 0x0); 2467 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN, 2468 B_BT_DYN_DC_EST_EN_MSK, 0x0); 2469 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 2470 0x0); 2471 } 2472} 2473 2474static 2475void rtw8852c_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val) 2476{ 2477 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x20000); 2478 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group); 2479 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val); 2480 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0); 2481} 2482 2483static void rtw8852c_btc_init_cfg(struct rtw89_dev *rtwdev) 2484{ 2485 struct rtw89_btc *btc = &rtwdev->btc; 2486 const struct rtw89_chip_info *chip = rtwdev->chip; 2487 const struct rtw89_mac_ax_coex coex_params = { 2488 .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE, 2489 .direction = RTW89_MAC_AX_COEX_INNER, 2490 }; 2491 2492 /* PTA init */ 2493 rtw89_mac_coex_init_v1(rtwdev, &coex_params); 2494 2495 /* set WL Tx response = Hi-Pri */ 2496 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true); 2497 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true); 2498 2499 /* set rf gnt debug off */ 2500 rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, RFREG_MASK, 0x0); 2501 rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, RFREG_MASK, 0x0); 2502 2503 /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */ 2504 if (btc->ant_type == BTC_ANT_SHARED) { 2505 rtw8852c_set_trx_mask(rtwdev, 2506 RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff); 2507 rtw8852c_set_trx_mask(rtwdev, 2508 RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff); 2509 /* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */ 2510 rtw8852c_set_trx_mask(rtwdev, 2511 RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff); 2512 } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */ 2513 rtw8852c_set_trx_mask(rtwdev, 2514 RF_PATH_A, BTC_BT_SS_GROUP, 0x5df); 2515 rtw8852c_set_trx_mask(rtwdev, 2516 RF_PATH_B, BTC_BT_SS_GROUP, 0x5df); 2517 } 2518 2519 /* set PTA break table */ 2520 rtw89_write32(rtwdev, R_AX_BT_BREAK_TABLE, BTC_BREAK_PARAM); 2521 2522 /* enable BT counter 0xda10[1:0] = 2b'11 */ 2523 rtw89_write32_set(rtwdev, 2524 R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN | 2525 B_AX_BT_CNT_RST_V1); 2526 btc->cx.wl.status.map.init_ok = true; 2527} 2528 2529static 2530void rtw8852c_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state) 2531{ 2532 u32 bitmap = 0; 2533 u32 reg = 0; 2534 2535 switch (map) { 2536 case BTC_PRI_MASK_TX_RESP: 2537 reg = R_BTC_COEX_WL_REQ; 2538 bitmap = B_BTC_RSP_ACK_HI; 2539 break; 2540 case BTC_PRI_MASK_BEACON: 2541 reg = R_BTC_COEX_WL_REQ; 2542 bitmap = B_BTC_TX_BCN_HI; 2543 break; 2544 default: 2545 return; 2546 } 2547 2548 if (state) 2549 rtw89_write32_set(rtwdev, reg, bitmap); 2550 else 2551 rtw89_write32_clr(rtwdev, reg, bitmap); 2552} 2553 2554union rtw8852c_btc_wl_txpwr_ctrl { 2555 u32 txpwr_val; 2556 struct { 2557 union { 2558 u16 ctrl_all_time; 2559 struct { 2560 s16 data:9; 2561 u16 rsvd:6; 2562 u16 flag:1; 2563 } all_time; 2564 }; 2565 union { 2566 u16 ctrl_gnt_bt; 2567 struct { 2568 s16 data:9; 2569 u16 rsvd:7; 2570 } gnt_bt; 2571 }; 2572 }; 2573} __packed; 2574 2575static void 2576rtw8852c_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val) 2577{ 2578 union rtw8852c_btc_wl_txpwr_ctrl arg = { .txpwr_val = txpwr_val }; 2579 s32 val; 2580 2581#define __write_ctrl(_reg, _msk, _val, _en, _cond) \ 2582do { \ 2583 u32 _wrt = FIELD_PREP(_msk, _val); \ 2584 BUILD_BUG_ON((_msk & _en) != 0); \ 2585 if (_cond) \ 2586 _wrt |= _en; \ 2587 else \ 2588 _wrt &= ~_en; \ 2589 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg, \ 2590 _msk | _en, _wrt); \ 2591} while (0) 2592 2593 switch (arg.ctrl_all_time) { 2594 case 0xffff: 2595 val = 0; 2596 break; 2597 default: 2598 val = arg.all_time.data; 2599 break; 2600 } 2601 2602 __write_ctrl(R_AX_PWR_RATE_CTRL, B_AX_FORCE_PWR_BY_RATE_VALUE_MASK, 2603 val, B_AX_FORCE_PWR_BY_RATE_EN, 2604 arg.ctrl_all_time != 0xffff); 2605 2606 switch (arg.ctrl_gnt_bt) { 2607 case 0xffff: 2608 val = 0; 2609 break; 2610 default: 2611 val = arg.gnt_bt.data; 2612 break; 2613 } 2614 2615 __write_ctrl(R_AX_PWR_COEXT_CTRL, B_AX_TXAGC_BT_MASK, val, 2616 B_AX_TXAGC_BT_EN, arg.ctrl_gnt_bt != 0xffff); 2617 2618#undef __write_ctrl 2619} 2620 2621static 2622s8 rtw8852c_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val) 2623{ 2624 /* +6 for compensate offset */ 2625 return clamp_t(s8, val + 6, -100, 0) + 100; 2626} 2627 2628static const struct rtw89_btc_rf_trx_para rtw89_btc_8852c_rf_ul[] = { 2629 {255, 0, 0, 7}, /* 0 -> original */ 2630 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */ 2631 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 2632 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 2633 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 2634 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */ 2635 {6, 1, 0, 7}, 2636 {13, 1, 0, 7}, 2637 {13, 1, 0, 7} 2638}; 2639 2640static const struct rtw89_btc_rf_trx_para rtw89_btc_8852c_rf_dl[] = { 2641 {255, 0, 0, 7}, /* 0 -> original */ 2642 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */ 2643 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 2644 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 2645 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 2646 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */ 2647 {255, 1, 0, 7}, 2648 {255, 1, 0, 7}, 2649 {255, 1, 0, 7} 2650}; 2651 2652static const u8 rtw89_btc_8852c_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30}; 2653static const u8 rtw89_btc_8852c_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {40, 36, 31, 28}; 2654 2655static const struct rtw89_btc_fbtc_mreg rtw89_btc_8852c_mon_reg[] = { 2656 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda00), 2657 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda04), 2658 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24), 2659 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30), 2660 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34), 2661 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda38), 2662 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda44), 2663 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda48), 2664 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c), 2665 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd200), 2666 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd220), 2667 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980), 2668 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4aa4), 2669 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4778), 2670 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x476c), 2671}; 2672 2673static 2674void rtw8852c_btc_update_bt_cnt(struct rtw89_dev *rtwdev) 2675{ 2676 /* Feature move to firmware */ 2677} 2678 2679static 2680void rtw8852c_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state) 2681{ 2682 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000); 2683 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 2684 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x620); 2685 2686 /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */ 2687 if (state) 2688 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 2689 RFREG_MASK, 0x179c); 2690 else 2691 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 2692 RFREG_MASK, 0x208); 2693 2694 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2695} 2696 2697static void rtw8852c_set_wl_lna2(struct rtw89_dev *rtwdev, u8 level) 2698{ 2699 /* level=0 Default: TIA 1/0= (LNA2,TIAN6) = (7,1)/(5,1) = 21dB/12dB 2700 * level=1 Fix LNA2=5: TIA 1/0= (LNA2,TIAN6) = (5,0)/(5,1) = 18dB/12dB 2701 * To improve BT ACI in co-rx 2702 */ 2703 2704 switch (level) { 2705 case 0: /* default */ 2706 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 2707 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x0); 2708 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2709 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 2710 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17); 2711 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 2712 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2713 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 2714 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17); 2715 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2716 break; 2717 case 1: /* Fix LNA2=5 */ 2718 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 2719 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x0); 2720 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2721 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 2722 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5); 2723 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 2724 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2725 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 2726 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5); 2727 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2728 break; 2729 } 2730} 2731 2732static void rtw8852c_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level) 2733{ 2734 struct rtw89_btc *btc = &rtwdev->btc; 2735 2736 switch (level) { 2737 case 0: /* original */ 2738 default: 2739 rtw8852c_ctrl_nbtg_bt_tx(rtwdev, false, RTW89_PHY_0); 2740 btc->dm.wl_lna2 = 0; 2741 break; 2742 case 1: /* for FDD free-run */ 2743 rtw8852c_ctrl_nbtg_bt_tx(rtwdev, true, RTW89_PHY_0); 2744 btc->dm.wl_lna2 = 0; 2745 break; 2746 case 2: /* for BTG Co-Rx*/ 2747 rtw8852c_ctrl_nbtg_bt_tx(rtwdev, false, RTW89_PHY_0); 2748 btc->dm.wl_lna2 = 1; 2749 break; 2750 } 2751 2752 rtw8852c_set_wl_lna2(rtwdev, btc->dm.wl_lna2); 2753} 2754 2755static void rtw8852c_fill_freq_with_ppdu(struct rtw89_dev *rtwdev, 2756 struct rtw89_rx_phy_ppdu *phy_ppdu, 2757 struct ieee80211_rx_status *status) 2758{ 2759 u8 chan_idx = phy_ppdu->chan_idx; 2760 enum nl80211_band band; 2761 u8 ch; 2762 2763 if (chan_idx == 0) 2764 return; 2765 2766 rtw89_decode_chan_idx(rtwdev, chan_idx, &ch, &band); 2767 status->freq = ieee80211_channel_to_frequency(ch, band); 2768 status->band = band; 2769} 2770 2771static void rtw8852c_query_ppdu(struct rtw89_dev *rtwdev, 2772 struct rtw89_rx_phy_ppdu *phy_ppdu, 2773 struct ieee80211_rx_status *status) 2774{ 2775 u8 path; 2776 u8 *rx_power = phy_ppdu->rssi; 2777 2778 status->signal = RTW89_RSSI_RAW_TO_DBM(max(rx_power[RF_PATH_A], rx_power[RF_PATH_B])); 2779 for (path = 0; path < rtwdev->chip->rf_path_num; path++) { 2780 status->chains |= BIT(path); 2781 status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]); 2782 } 2783 if (phy_ppdu->valid) 2784 rtw8852c_fill_freq_with_ppdu(rtwdev, phy_ppdu, status); 2785} 2786 2787static int rtw8852c_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 2788{ 2789 int ret; 2790 2791 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 2792 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 2793 2794 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2795 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2796 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2797 2798 rtw89_write32_mask(rtwdev, R_AX_AFE_OFF_CTRL1, B_AX_S0_LDO_VSEL_F_MASK, 0x1); 2799 rtw89_write32_mask(rtwdev, R_AX_AFE_OFF_CTRL1, B_AX_S1_LDO_VSEL_F_MASK, 0x1); 2800 2801 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL0, 0x7, FULL_BIT_MASK); 2802 if (ret) 2803 return ret; 2804 2805 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x6c, FULL_BIT_MASK); 2806 if (ret) 2807 return ret; 2808 2809 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xc7, FULL_BIT_MASK); 2810 if (ret) 2811 return ret; 2812 2813 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xc7, FULL_BIT_MASK); 2814 if (ret) 2815 return ret; 2816 2817 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL3, 0xd, FULL_BIT_MASK); 2818 if (ret) 2819 return ret; 2820 2821 return 0; 2822} 2823 2824static int rtw8852c_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 2825{ 2826 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2827 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 2828 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 2829 2830 return 0; 2831} 2832 2833static const struct rtw89_chanctx_listener rtw8852c_chanctx_listener = { 2834 .callbacks[RTW89_CHANCTX_CALLBACK_RFK] = rtw8852c_rfk_chanctx_cb, 2835}; 2836 2837#ifdef CONFIG_PM 2838static const struct wiphy_wowlan_support rtw_wowlan_stub_8852c = { 2839 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT, 2840 .n_patterns = RTW89_MAX_PATTERN_NUM, 2841 .pattern_max_len = RTW89_MAX_PATTERN_SIZE, 2842 .pattern_min_len = 1, 2843}; 2844#endif 2845 2846static const struct rtw89_chip_ops rtw8852c_chip_ops = { 2847 .enable_bb_rf = rtw8852c_mac_enable_bb_rf, 2848 .disable_bb_rf = rtw8852c_mac_disable_bb_rf, 2849 .bb_preinit = NULL, 2850 .bb_postinit = NULL, 2851 .bb_reset = rtw8852c_bb_reset, 2852 .bb_sethw = rtw8852c_bb_sethw, 2853 .read_rf = rtw89_phy_read_rf_v1, 2854 .write_rf = rtw89_phy_write_rf_v1, 2855 .set_channel = rtw8852c_set_channel, 2856 .set_channel_help = rtw8852c_set_channel_help, 2857 .read_efuse = rtw8852c_read_efuse, 2858 .read_phycap = rtw8852c_read_phycap, 2859 .fem_setup = NULL, 2860 .rfe_gpio = NULL, 2861 .rfk_hw_init = NULL, 2862 .rfk_init = rtw8852c_rfk_init, 2863 .rfk_init_late = NULL, 2864 .rfk_channel = rtw8852c_rfk_channel, 2865 .rfk_band_changed = rtw8852c_rfk_band_changed, 2866 .rfk_scan = rtw8852c_rfk_scan, 2867 .rfk_track = rtw8852c_rfk_track, 2868 .power_trim = rtw8852c_power_trim, 2869 .set_txpwr = rtw8852c_set_txpwr, 2870 .set_txpwr_ctrl = rtw8852c_set_txpwr_ctrl, 2871 .init_txpwr_unit = rtw8852c_init_txpwr_unit, 2872 .get_thermal = rtw8852c_get_thermal, 2873 .ctrl_btg_bt_rx = rtw8852c_ctrl_btg_bt_rx, 2874 .query_ppdu = rtw8852c_query_ppdu, 2875 .ctrl_nbtg_bt_tx = rtw8852c_ctrl_nbtg_bt_tx, 2876 .cfg_txrx_path = rtw8852c_bb_cfg_txrx_path, 2877 .set_txpwr_ul_tb_offset = rtw8852c_set_txpwr_ul_tb_offset, 2878 .pwr_on_func = rtw8852c_pwr_on_func, 2879 .pwr_off_func = rtw8852c_pwr_off_func, 2880 .query_rxdesc = rtw89_core_query_rxdesc, 2881 .fill_txdesc = rtw89_core_fill_txdesc_v1, 2882 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc_fwcmd_v1, 2883 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path_v1, 2884 .mac_cfg_gnt = rtw89_mac_cfg_gnt_v1, 2885 .stop_sch_tx = rtw89_mac_stop_sch_tx_v1, 2886 .resume_sch_tx = rtw89_mac_resume_sch_tx_v1, 2887 .h2c_dctl_sec_cam = rtw89_fw_h2c_dctl_sec_cam_v1, 2888 .h2c_default_cmac_tbl = rtw89_fw_h2c_default_cmac_tbl, 2889 .h2c_assoc_cmac_tbl = rtw89_fw_h2c_assoc_cmac_tbl, 2890 .h2c_ampdu_cmac_tbl = NULL, 2891 .h2c_default_dmac_tbl = NULL, 2892 .h2c_update_beacon = rtw89_fw_h2c_update_beacon, 2893 .h2c_ba_cam = rtw89_fw_h2c_ba_cam, 2894 2895 .btc_set_rfe = rtw8852c_btc_set_rfe, 2896 .btc_init_cfg = rtw8852c_btc_init_cfg, 2897 .btc_set_wl_pri = rtw8852c_btc_set_wl_pri, 2898 .btc_set_wl_txpwr_ctrl = rtw8852c_btc_set_wl_txpwr_ctrl, 2899 .btc_get_bt_rssi = rtw8852c_btc_get_bt_rssi, 2900 .btc_update_bt_cnt = rtw8852c_btc_update_bt_cnt, 2901 .btc_wl_s1_standby = rtw8852c_btc_wl_s1_standby, 2902 .btc_set_wl_rx_gain = rtw8852c_btc_set_wl_rx_gain, 2903 .btc_set_policy = rtw89_btc_set_policy_v1, 2904}; 2905 2906const struct rtw89_chip_info rtw8852c_chip_info = { 2907 .chip_id = RTL8852C, 2908 .chip_gen = RTW89_CHIP_AX, 2909 .ops = &rtw8852c_chip_ops, 2910 .mac_def = &rtw89_mac_gen_ax, 2911 .phy_def = &rtw89_phy_gen_ax, 2912 .fw_basename = RTW8852C_FW_BASENAME, 2913 .fw_format_max = RTW8852C_FW_FORMAT_MAX, 2914 .try_ce_fw = false, 2915 .bbmcu_nr = 0, 2916 .needed_fw_elms = 0, 2917 .fifo_size = 458752, 2918 .small_fifo_size = false, 2919 .dle_scc_rsvd_size = 0, 2920 .max_amsdu_limit = 8000, 2921 .dis_2g_40m_ul_ofdma = false, 2922 .rsvd_ple_ofst = 0x6f800, 2923 .hfc_param_ini = rtw8852c_hfc_param_ini_pcie, 2924 .dle_mem = rtw8852c_dle_mem_pcie, 2925 .wde_qempty_acq_grpnum = 16, 2926 .wde_qempty_mgq_grpsel = 16, 2927 .rf_base_addr = {0xe000, 0xf000}, 2928 .pwr_on_seq = NULL, 2929 .pwr_off_seq = NULL, 2930 .bb_table = &rtw89_8852c_phy_bb_table, 2931 .bb_gain_table = &rtw89_8852c_phy_bb_gain_table, 2932 .rf_table = {&rtw89_8852c_phy_radiob_table, 2933 &rtw89_8852c_phy_radioa_table,}, 2934 .nctl_table = &rtw89_8852c_phy_nctl_table, 2935 .nctl_post_table = NULL, 2936 .dflt_parms = &rtw89_8852c_dflt_parms, 2937 .rfe_parms_conf = NULL, 2938 .chanctx_listener = &rtw8852c_chanctx_listener, 2939 .txpwr_factor_rf = 2, 2940 .txpwr_factor_mac = 1, 2941 .dig_table = NULL, 2942 .dig_regs = &rtw8852c_dig_regs, 2943 .tssi_dbw_table = &rtw89_8852c_tssi_dbw_table, 2944 .support_chanctx_num = 2, 2945 .support_rnr = false, 2946 .support_bands = BIT(NL80211_BAND_2GHZ) | 2947 BIT(NL80211_BAND_5GHZ) | 2948 BIT(NL80211_BAND_6GHZ), 2949 .support_bandwidths = BIT(NL80211_CHAN_WIDTH_20) | 2950 BIT(NL80211_CHAN_WIDTH_40) | 2951 BIT(NL80211_CHAN_WIDTH_80) | 2952 BIT(NL80211_CHAN_WIDTH_160), 2953 .support_unii4 = true, 2954 .ul_tb_waveform_ctrl = false, 2955 .ul_tb_pwr_diff = true, 2956 .hw_sec_hdr = true, 2957 .rf_path_num = 2, 2958 .tx_nss = 2, 2959 .rx_nss = 2, 2960 .acam_num = 128, 2961 .bcam_num = 20, 2962 .scam_num = 128, 2963 .bacam_num = 8, 2964 .bacam_dynamic_num = 8, 2965 .bacam_ver = RTW89_BACAM_V0_EXT, 2966 .ppdu_max_usr = 8, 2967 .sec_ctrl_efuse_size = 4, 2968 .physical_efuse_size = 1216, 2969 .logical_efuse_size = 2048, 2970 .limit_efuse_size = 1280, 2971 .dav_phy_efuse_size = 96, 2972 .dav_log_efuse_size = 16, 2973 .efuse_blocks = NULL, 2974 .phycap_addr = 0x590, 2975 .phycap_size = 0x60, 2976 .para_ver = 0x1, 2977 .wlcx_desired = 0x06000000, 2978 .btcx_desired = 0x7, 2979 .scbd = 0x1, 2980 .mailbox = 0x1, 2981 2982 .afh_guard_ch = 6, 2983 .wl_rssi_thres = rtw89_btc_8852c_wl_rssi_thres, 2984 .bt_rssi_thres = rtw89_btc_8852c_bt_rssi_thres, 2985 .rssi_tol = 2, 2986 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852c_mon_reg), 2987 .mon_reg = rtw89_btc_8852c_mon_reg, 2988 .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8852c_rf_ul), 2989 .rf_para_ulink = rtw89_btc_8852c_rf_ul, 2990 .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852c_rf_dl), 2991 .rf_para_dlink = rtw89_btc_8852c_rf_dl, 2992 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) | 2993 BIT(RTW89_PS_MODE_CLK_GATED) | 2994 BIT(RTW89_PS_MODE_PWR_GATED), 2995 .low_power_hci_modes = BIT(RTW89_PS_MODE_CLK_GATED) | 2996 BIT(RTW89_PS_MODE_PWR_GATED), 2997 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD_V1, 2998 .hci_func_en_addr = R_AX_HCI_FUNC_EN_V1, 2999 .h2c_desc_size = sizeof(struct rtw89_rxdesc_short), 3000 .txwd_body_size = sizeof(struct rtw89_txwd_body_v1), 3001 .txwd_info_size = sizeof(struct rtw89_txwd_info), 3002 .h2c_ctrl_reg = R_AX_H2CREG_CTRL_V1, 3003 .h2c_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8}, 3004 .h2c_regs = rtw8852c_h2c_regs, 3005 .c2h_ctrl_reg = R_AX_C2HREG_CTRL_V1, 3006 .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8}, 3007 .c2h_regs = rtw8852c_c2h_regs, 3008 .page_regs = &rtw8852c_page_regs, 3009 .wow_reason_reg = R_AX_C2HREG_DATA3_V1 + 3, 3010 .cfo_src_fd = false, 3011 .cfo_hw_comp = false, 3012 .dcfo_comp = &rtw8852c_dcfo_comp, 3013 .dcfo_comp_sft = 12, 3014 .imr_info = &rtw8852c_imr_info, 3015 .imr_dmac_table = NULL, 3016 .imr_cmac_table = NULL, 3017 .rrsr_cfgs = &rtw8852c_rrsr_cfgs, 3018 .bss_clr_vld = {R_BSS_CLR_MAP, B_BSS_CLR_MAP_VLD0}, 3019 .bss_clr_map_reg = R_BSS_CLR_MAP, 3020 .dma_ch_mask = 0, 3021 .edcca_regs = &rtw8852c_edcca_regs, 3022#ifdef CONFIG_PM 3023 .wowlan_stub = &rtw_wowlan_stub_8852c, 3024#endif 3025 .xtal_info = NULL, 3026}; 3027EXPORT_SYMBOL(rtw8852c_chip_info); 3028 3029MODULE_FIRMWARE(RTW8852C_MODULE_FIRMWARE); 3030MODULE_AUTHOR("Realtek Corporation"); 3031MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852C driver"); 3032MODULE_LICENSE("Dual BSD/GPL"); 3033