1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Driver for Aquantia PHY 4 * 5 * Author: Shaohui Xie <Shaohui.Xie@freescale.com> 6 * 7 * Copyright 2015 Freescale Semiconductor, Inc. 8 */ 9 10#include <linux/kernel.h> 11#include <linux/module.h> 12#include <linux/delay.h> 13#include <linux/bitfield.h> 14#include <linux/phy.h> 15 16#include "aquantia.h" 17 18#define PHY_ID_AQ1202 0x03a1b445 19#define PHY_ID_AQ2104 0x03a1b460 20#define PHY_ID_AQR105 0x03a1b4a2 21#define PHY_ID_AQR106 0x03a1b4d0 22#define PHY_ID_AQR107 0x03a1b4e0 23#define PHY_ID_AQCS109 0x03a1b5c2 24#define PHY_ID_AQR405 0x03a1b4b0 25#define PHY_ID_AQR111 0x03a1b610 26#define PHY_ID_AQR111B0 0x03a1b612 27#define PHY_ID_AQR112 0x03a1b662 28#define PHY_ID_AQR412 0x03a1b712 29#define PHY_ID_AQR113 0x31c31c40 30#define PHY_ID_AQR113C 0x31c31c12 31#define PHY_ID_AQR114C 0x31c31c22 32#define PHY_ID_AQR813 0x31c31cb2 33 34#define MDIO_PHYXS_VEND_IF_STATUS 0xe812 35#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3) 36#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0 37#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX 1 38#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI 2 39#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII 3 40#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI 4 41#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII 6 42#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI 7 43#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10 44 45#define MDIO_AN_VEND_PROV 0xc400 46#define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15) 47#define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14) 48#define MDIO_AN_VEND_PROV_5000BASET_FULL BIT(11) 49#define MDIO_AN_VEND_PROV_2500BASET_FULL BIT(10) 50#define MDIO_AN_VEND_PROV_DOWNSHIFT_EN BIT(4) 51#define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK GENMASK(3, 0) 52#define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT 4 53 54#define MDIO_AN_TX_VEND_STATUS1 0xc800 55#define MDIO_AN_TX_VEND_STATUS1_RATE_MASK GENMASK(3, 1) 56#define MDIO_AN_TX_VEND_STATUS1_10BASET 0 57#define MDIO_AN_TX_VEND_STATUS1_100BASETX 1 58#define MDIO_AN_TX_VEND_STATUS1_1000BASET 2 59#define MDIO_AN_TX_VEND_STATUS1_10GBASET 3 60#define MDIO_AN_TX_VEND_STATUS1_2500BASET 4 61#define MDIO_AN_TX_VEND_STATUS1_5000BASET 5 62#define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX BIT(0) 63 64#define MDIO_AN_TX_VEND_INT_STATUS1 0xcc00 65#define MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT BIT(1) 66 67#define MDIO_AN_TX_VEND_INT_STATUS2 0xcc01 68#define MDIO_AN_TX_VEND_INT_STATUS2_MASK BIT(0) 69 70#define MDIO_AN_TX_VEND_INT_MASK2 0xd401 71#define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0) 72 73#define MDIO_AN_RX_LP_STAT1 0xe820 74#define MDIO_AN_RX_LP_STAT1_1000BASET_FULL BIT(15) 75#define MDIO_AN_RX_LP_STAT1_1000BASET_HALF BIT(14) 76#define MDIO_AN_RX_LP_STAT1_SHORT_REACH BIT(13) 77#define MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT BIT(12) 78#define MDIO_AN_RX_LP_STAT1_AQ_PHY BIT(2) 79 80#define MDIO_AN_RX_LP_STAT4 0xe823 81#define MDIO_AN_RX_LP_STAT4_FW_MAJOR GENMASK(15, 8) 82#define MDIO_AN_RX_LP_STAT4_FW_MINOR GENMASK(7, 0) 83 84#define MDIO_AN_RX_VEND_STAT3 0xe832 85#define MDIO_AN_RX_VEND_STAT3_AFR BIT(0) 86 87/* MDIO_MMD_C22EXT */ 88#define MDIO_C22EXT_STAT_SGMII_RX_GOOD_FRAMES 0xd292 89#define MDIO_C22EXT_STAT_SGMII_RX_BAD_FRAMES 0xd294 90#define MDIO_C22EXT_STAT_SGMII_RX_FALSE_CARRIER 0xd297 91#define MDIO_C22EXT_STAT_SGMII_TX_GOOD_FRAMES 0xd313 92#define MDIO_C22EXT_STAT_SGMII_TX_BAD_FRAMES 0xd315 93#define MDIO_C22EXT_STAT_SGMII_TX_FALSE_CARRIER 0xd317 94#define MDIO_C22EXT_STAT_SGMII_TX_COLLISIONS 0xd318 95#define MDIO_C22EXT_STAT_SGMII_TX_LINE_COLLISIONS 0xd319 96#define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR 0xd31a 97#define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES 0xd31b 98 99/* Sleep and timeout for checking if the Processor-Intensive 100 * MDIO operation is finished 101 */ 102#define AQR107_OP_IN_PROG_SLEEP 1000 103#define AQR107_OP_IN_PROG_TIMEOUT 100000 104 105struct aqr107_hw_stat { 106 const char *name; 107 int reg; 108 int size; 109}; 110 111#define SGMII_STAT(n, r, s) { n, MDIO_C22EXT_STAT_SGMII_ ## r, s } 112static const struct aqr107_hw_stat aqr107_hw_stats[] = { 113 SGMII_STAT("sgmii_rx_good_frames", RX_GOOD_FRAMES, 26), 114 SGMII_STAT("sgmii_rx_bad_frames", RX_BAD_FRAMES, 26), 115 SGMII_STAT("sgmii_rx_false_carrier_events", RX_FALSE_CARRIER, 8), 116 SGMII_STAT("sgmii_tx_good_frames", TX_GOOD_FRAMES, 26), 117 SGMII_STAT("sgmii_tx_bad_frames", TX_BAD_FRAMES, 26), 118 SGMII_STAT("sgmii_tx_false_carrier_events", TX_FALSE_CARRIER, 8), 119 SGMII_STAT("sgmii_tx_collisions", TX_COLLISIONS, 8), 120 SGMII_STAT("sgmii_tx_line_collisions", TX_LINE_COLLISIONS, 8), 121 SGMII_STAT("sgmii_tx_frame_alignment_err", TX_FRAME_ALIGN_ERR, 16), 122 SGMII_STAT("sgmii_tx_runt_frames", TX_RUNT_FRAMES, 22), 123}; 124#define AQR107_SGMII_STAT_SZ ARRAY_SIZE(aqr107_hw_stats) 125 126struct aqr107_priv { 127 u64 sgmii_stats[AQR107_SGMII_STAT_SZ]; 128}; 129 130static int aqr107_get_sset_count(struct phy_device *phydev) 131{ 132 return AQR107_SGMII_STAT_SZ; 133} 134 135static void aqr107_get_strings(struct phy_device *phydev, u8 *data) 136{ 137 int i; 138 139 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) 140 strscpy(data + i * ETH_GSTRING_LEN, aqr107_hw_stats[i].name, 141 ETH_GSTRING_LEN); 142} 143 144static u64 aqr107_get_stat(struct phy_device *phydev, int index) 145{ 146 const struct aqr107_hw_stat *stat = aqr107_hw_stats + index; 147 int len_l = min(stat->size, 16); 148 int len_h = stat->size - len_l; 149 u64 ret; 150 int val; 151 152 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg); 153 if (val < 0) 154 return U64_MAX; 155 156 ret = val & GENMASK(len_l - 1, 0); 157 if (len_h) { 158 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1); 159 if (val < 0) 160 return U64_MAX; 161 162 ret += (val & GENMASK(len_h - 1, 0)) << 16; 163 } 164 165 return ret; 166} 167 168static void aqr107_get_stats(struct phy_device *phydev, 169 struct ethtool_stats *stats, u64 *data) 170{ 171 struct aqr107_priv *priv = phydev->priv; 172 u64 val; 173 int i; 174 175 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) { 176 val = aqr107_get_stat(phydev, i); 177 if (val == U64_MAX) 178 phydev_err(phydev, "Reading HW Statistics failed for %s\n", 179 aqr107_hw_stats[i].name); 180 else 181 priv->sgmii_stats[i] += val; 182 183 data[i] = priv->sgmii_stats[i]; 184 } 185} 186 187static int aqr_config_aneg(struct phy_device *phydev) 188{ 189 bool changed = false; 190 u16 reg; 191 int ret; 192 193 if (phydev->autoneg == AUTONEG_DISABLE) 194 return genphy_c45_pma_setup_forced(phydev); 195 196 ret = genphy_c45_an_config_aneg(phydev); 197 if (ret < 0) 198 return ret; 199 if (ret > 0) 200 changed = true; 201 202 /* Clause 45 has no standardized support for 1000BaseT, therefore 203 * use vendor registers for this mode. 204 */ 205 reg = 0; 206 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 207 phydev->advertising)) 208 reg |= MDIO_AN_VEND_PROV_1000BASET_FULL; 209 210 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 211 phydev->advertising)) 212 reg |= MDIO_AN_VEND_PROV_1000BASET_HALF; 213 214 /* Handle the case when the 2.5G and 5G speeds are not advertised */ 215 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 216 phydev->advertising)) 217 reg |= MDIO_AN_VEND_PROV_2500BASET_FULL; 218 219 if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, 220 phydev->advertising)) 221 reg |= MDIO_AN_VEND_PROV_5000BASET_FULL; 222 223 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, 224 MDIO_AN_VEND_PROV_1000BASET_HALF | 225 MDIO_AN_VEND_PROV_1000BASET_FULL | 226 MDIO_AN_VEND_PROV_2500BASET_FULL | 227 MDIO_AN_VEND_PROV_5000BASET_FULL, reg); 228 if (ret < 0) 229 return ret; 230 if (ret > 0) 231 changed = true; 232 233 return genphy_c45_check_and_restart_aneg(phydev, changed); 234} 235 236static int aqr_config_intr(struct phy_device *phydev) 237{ 238 bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED; 239 int err; 240 241 if (en) { 242 /* Clear any pending interrupts before enabling them */ 243 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2); 244 if (err < 0) 245 return err; 246 } 247 248 err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2, 249 en ? MDIO_AN_TX_VEND_INT_MASK2_LINK : 0); 250 if (err < 0) 251 return err; 252 253 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK, 254 en ? VEND1_GLOBAL_INT_STD_MASK_ALL : 0); 255 if (err < 0) 256 return err; 257 258 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK, 259 en ? VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 | 260 VEND1_GLOBAL_INT_VEND_MASK_AN : 0); 261 if (err < 0) 262 return err; 263 264 if (!en) { 265 /* Clear any pending interrupts after we have disabled them */ 266 err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2); 267 if (err < 0) 268 return err; 269 } 270 271 return 0; 272} 273 274static irqreturn_t aqr_handle_interrupt(struct phy_device *phydev) 275{ 276 int irq_status; 277 278 irq_status = phy_read_mmd(phydev, MDIO_MMD_AN, 279 MDIO_AN_TX_VEND_INT_STATUS2); 280 if (irq_status < 0) { 281 phy_error(phydev); 282 return IRQ_NONE; 283 } 284 285 if (!(irq_status & MDIO_AN_TX_VEND_INT_STATUS2_MASK)) 286 return IRQ_NONE; 287 288 phy_trigger_machine(phydev); 289 290 return IRQ_HANDLED; 291} 292 293static int aqr_read_status(struct phy_device *phydev) 294{ 295 int val; 296 297 if (phydev->autoneg == AUTONEG_ENABLE) { 298 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); 299 if (val < 0) 300 return val; 301 302 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 303 phydev->lp_advertising, 304 val & MDIO_AN_RX_LP_STAT1_1000BASET_FULL); 305 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 306 phydev->lp_advertising, 307 val & MDIO_AN_RX_LP_STAT1_1000BASET_HALF); 308 } 309 310 return genphy_c45_read_status(phydev); 311} 312 313static int aqr107_read_rate(struct phy_device *phydev) 314{ 315 u32 config_reg; 316 int val; 317 318 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1); 319 if (val < 0) 320 return val; 321 322 if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX) 323 phydev->duplex = DUPLEX_FULL; 324 else 325 phydev->duplex = DUPLEX_HALF; 326 327 switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) { 328 case MDIO_AN_TX_VEND_STATUS1_10BASET: 329 phydev->speed = SPEED_10; 330 config_reg = VEND1_GLOBAL_CFG_10M; 331 break; 332 case MDIO_AN_TX_VEND_STATUS1_100BASETX: 333 phydev->speed = SPEED_100; 334 config_reg = VEND1_GLOBAL_CFG_100M; 335 break; 336 case MDIO_AN_TX_VEND_STATUS1_1000BASET: 337 phydev->speed = SPEED_1000; 338 config_reg = VEND1_GLOBAL_CFG_1G; 339 break; 340 case MDIO_AN_TX_VEND_STATUS1_2500BASET: 341 phydev->speed = SPEED_2500; 342 config_reg = VEND1_GLOBAL_CFG_2_5G; 343 break; 344 case MDIO_AN_TX_VEND_STATUS1_5000BASET: 345 phydev->speed = SPEED_5000; 346 config_reg = VEND1_GLOBAL_CFG_5G; 347 break; 348 case MDIO_AN_TX_VEND_STATUS1_10GBASET: 349 phydev->speed = SPEED_10000; 350 config_reg = VEND1_GLOBAL_CFG_10G; 351 break; 352 default: 353 phydev->speed = SPEED_UNKNOWN; 354 return 0; 355 } 356 357 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, config_reg); 358 if (val < 0) 359 return val; 360 361 if (FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val) == 362 VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE) 363 phydev->rate_matching = RATE_MATCH_PAUSE; 364 else 365 phydev->rate_matching = RATE_MATCH_NONE; 366 367 return 0; 368} 369 370static int aqr107_read_status(struct phy_device *phydev) 371{ 372 int val, ret; 373 374 ret = aqr_read_status(phydev); 375 if (ret) 376 return ret; 377 378 if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE) 379 return 0; 380 381 val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS); 382 if (val < 0) 383 return val; 384 385 switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) { 386 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR: 387 phydev->interface = PHY_INTERFACE_MODE_10GKR; 388 break; 389 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX: 390 phydev->interface = PHY_INTERFACE_MODE_1000BASEKX; 391 break; 392 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI: 393 phydev->interface = PHY_INTERFACE_MODE_10GBASER; 394 break; 395 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII: 396 phydev->interface = PHY_INTERFACE_MODE_USXGMII; 397 break; 398 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI: 399 phydev->interface = PHY_INTERFACE_MODE_XAUI; 400 break; 401 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII: 402 phydev->interface = PHY_INTERFACE_MODE_SGMII; 403 break; 404 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI: 405 phydev->interface = PHY_INTERFACE_MODE_RXAUI; 406 break; 407 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII: 408 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 409 break; 410 default: 411 phydev->interface = PHY_INTERFACE_MODE_NA; 412 break; 413 } 414 415 /* Read possibly downshifted rate from vendor register */ 416 return aqr107_read_rate(phydev); 417} 418 419static int aqr107_get_downshift(struct phy_device *phydev, u8 *data) 420{ 421 int val, cnt, enable; 422 423 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV); 424 if (val < 0) 425 return val; 426 427 enable = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_EN, val); 428 cnt = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); 429 430 *data = enable && cnt ? cnt : DOWNSHIFT_DEV_DISABLE; 431 432 return 0; 433} 434 435static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt) 436{ 437 int val = 0; 438 439 if (!FIELD_FIT(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt)) 440 return -E2BIG; 441 442 if (cnt != DOWNSHIFT_DEV_DISABLE) { 443 val = MDIO_AN_VEND_PROV_DOWNSHIFT_EN; 444 val |= FIELD_PREP(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt); 445 } 446 447 return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, 448 MDIO_AN_VEND_PROV_DOWNSHIFT_EN | 449 MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); 450} 451 452static int aqr107_get_tunable(struct phy_device *phydev, 453 struct ethtool_tunable *tuna, void *data) 454{ 455 switch (tuna->id) { 456 case ETHTOOL_PHY_DOWNSHIFT: 457 return aqr107_get_downshift(phydev, data); 458 default: 459 return -EOPNOTSUPP; 460 } 461} 462 463static int aqr107_set_tunable(struct phy_device *phydev, 464 struct ethtool_tunable *tuna, const void *data) 465{ 466 switch (tuna->id) { 467 case ETHTOOL_PHY_DOWNSHIFT: 468 return aqr107_set_downshift(phydev, *(const u8 *)data); 469 default: 470 return -EOPNOTSUPP; 471 } 472} 473 474/* If we configure settings whilst firmware is still initializing the chip, 475 * then these settings may be overwritten. Therefore make sure chip 476 * initialization has completed. Use presence of the firmware ID as 477 * indicator for initialization having completed. 478 * The chip also provides a "reset completed" bit, but it's cleared after 479 * read. Therefore function would time out if called again. 480 */ 481static int aqr107_wait_reset_complete(struct phy_device *phydev) 482{ 483 int val; 484 485 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 486 VEND1_GLOBAL_FW_ID, val, val != 0, 487 20000, 2000000, false); 488} 489 490static void aqr107_chip_info(struct phy_device *phydev) 491{ 492 u8 fw_major, fw_minor, build_id, prov_id; 493 int val; 494 495 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID); 496 if (val < 0) 497 return; 498 499 fw_major = FIELD_GET(VEND1_GLOBAL_FW_ID_MAJOR, val); 500 fw_minor = FIELD_GET(VEND1_GLOBAL_FW_ID_MINOR, val); 501 502 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1); 503 if (val < 0) 504 return; 505 506 build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val); 507 prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val); 508 509 phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n", 510 fw_major, fw_minor, build_id, prov_id); 511} 512 513static int aqr107_config_init(struct phy_device *phydev) 514{ 515 int ret; 516 517 /* Check that the PHY interface type is compatible */ 518 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 519 phydev->interface != PHY_INTERFACE_MODE_1000BASEKX && 520 phydev->interface != PHY_INTERFACE_MODE_2500BASEX && 521 phydev->interface != PHY_INTERFACE_MODE_XGMII && 522 phydev->interface != PHY_INTERFACE_MODE_USXGMII && 523 phydev->interface != PHY_INTERFACE_MODE_10GKR && 524 phydev->interface != PHY_INTERFACE_MODE_10GBASER && 525 phydev->interface != PHY_INTERFACE_MODE_XAUI && 526 phydev->interface != PHY_INTERFACE_MODE_RXAUI) 527 return -ENODEV; 528 529 WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII, 530 "Your devicetree is out of date, please update it. The AQR107 family doesn't support XGMII, maybe you mean USXGMII.\n"); 531 532 ret = aqr107_wait_reset_complete(phydev); 533 if (!ret) 534 aqr107_chip_info(phydev); 535 536 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); 537} 538 539static int aqcs109_config_init(struct phy_device *phydev) 540{ 541 int ret; 542 543 /* Check that the PHY interface type is compatible */ 544 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 545 phydev->interface != PHY_INTERFACE_MODE_2500BASEX) 546 return -ENODEV; 547 548 ret = aqr107_wait_reset_complete(phydev); 549 if (!ret) 550 aqr107_chip_info(phydev); 551 552 /* AQCS109 belongs to a chip family partially supporting 10G and 5G. 553 * PMA speed ability bits are the same for all members of the family, 554 * AQCS109 however supports speeds up to 2.5G only. 555 */ 556 phy_set_max_speed(phydev, SPEED_2500); 557 558 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); 559} 560 561static void aqr107_link_change_notify(struct phy_device *phydev) 562{ 563 u8 fw_major, fw_minor; 564 bool downshift, short_reach, afr; 565 int mode, val; 566 567 if (phydev->state != PHY_RUNNING || phydev->autoneg == AUTONEG_DISABLE) 568 return; 569 570 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); 571 /* call failed or link partner is no Aquantia PHY */ 572 if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY)) 573 return; 574 575 short_reach = val & MDIO_AN_RX_LP_STAT1_SHORT_REACH; 576 downshift = val & MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT; 577 578 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4); 579 if (val < 0) 580 return; 581 582 fw_major = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MAJOR, val); 583 fw_minor = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MINOR, val); 584 585 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3); 586 if (val < 0) 587 return; 588 589 afr = val & MDIO_AN_RX_VEND_STAT3_AFR; 590 591 phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n", 592 fw_major, fw_minor, 593 short_reach ? ", short reach mode" : "", 594 downshift ? ", fast-retrain downshift advertised" : "", 595 afr ? ", fast reframe advertised" : ""); 596 597 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9); 598 if (val < 0) 599 return; 600 601 mode = FIELD_GET(VEND1_GLOBAL_RSVD_STAT9_MODE, val); 602 if (mode == VEND1_GLOBAL_RSVD_STAT9_1000BT2) 603 phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n"); 604} 605 606static int aqr107_wait_processor_intensive_op(struct phy_device *phydev) 607{ 608 int val, err; 609 610 /* The datasheet notes to wait at least 1ms after issuing a 611 * processor intensive operation before checking. 612 * We cannot use the 'sleep_before_read' parameter of read_poll_timeout 613 * because that just determines the maximum time slept, not the minimum. 614 */ 615 usleep_range(1000, 5000); 616 617 err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 618 VEND1_GLOBAL_GEN_STAT2, val, 619 !(val & VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG), 620 AQR107_OP_IN_PROG_SLEEP, 621 AQR107_OP_IN_PROG_TIMEOUT, false); 622 if (err) { 623 phydev_err(phydev, "timeout: processor-intensive MDIO operation\n"); 624 return err; 625 } 626 627 return 0; 628} 629 630static int aqr107_get_rate_matching(struct phy_device *phydev, 631 phy_interface_t iface) 632{ 633 if (iface == PHY_INTERFACE_MODE_10GBASER || 634 iface == PHY_INTERFACE_MODE_2500BASEX || 635 iface == PHY_INTERFACE_MODE_NA) 636 return RATE_MATCH_PAUSE; 637 return RATE_MATCH_NONE; 638} 639 640static int aqr107_suspend(struct phy_device *phydev) 641{ 642 int err; 643 644 err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, 645 MDIO_CTRL1_LPOWER); 646 if (err) 647 return err; 648 649 return aqr107_wait_processor_intensive_op(phydev); 650} 651 652static int aqr107_resume(struct phy_device *phydev) 653{ 654 int err; 655 656 err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, 657 MDIO_CTRL1_LPOWER); 658 if (err) 659 return err; 660 661 return aqr107_wait_processor_intensive_op(phydev); 662} 663 664static const u16 aqr_global_cfg_regs[] = { 665 VEND1_GLOBAL_CFG_10M, 666 VEND1_GLOBAL_CFG_100M, 667 VEND1_GLOBAL_CFG_1G, 668 VEND1_GLOBAL_CFG_2_5G, 669 VEND1_GLOBAL_CFG_5G, 670 VEND1_GLOBAL_CFG_10G 671}; 672 673static int aqr107_fill_interface_modes(struct phy_device *phydev) 674{ 675 unsigned long *possible = phydev->possible_interfaces; 676 unsigned int serdes_mode, rate_adapt; 677 phy_interface_t interface; 678 int i, val; 679 680 /* Walk the media-speed configuration registers to determine which 681 * host-side serdes modes may be used by the PHY depending on the 682 * negotiated media speed. 683 */ 684 for (i = 0; i < ARRAY_SIZE(aqr_global_cfg_regs); i++) { 685 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, 686 aqr_global_cfg_regs[i]); 687 if (val < 0) 688 return val; 689 690 serdes_mode = FIELD_GET(VEND1_GLOBAL_CFG_SERDES_MODE, val); 691 rate_adapt = FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val); 692 693 switch (serdes_mode) { 694 case VEND1_GLOBAL_CFG_SERDES_MODE_XFI: 695 if (rate_adapt == VEND1_GLOBAL_CFG_RATE_ADAPT_USX) 696 interface = PHY_INTERFACE_MODE_USXGMII; 697 else 698 interface = PHY_INTERFACE_MODE_10GBASER; 699 break; 700 701 case VEND1_GLOBAL_CFG_SERDES_MODE_XFI5G: 702 interface = PHY_INTERFACE_MODE_5GBASER; 703 break; 704 705 case VEND1_GLOBAL_CFG_SERDES_MODE_OCSGMII: 706 interface = PHY_INTERFACE_MODE_2500BASEX; 707 break; 708 709 case VEND1_GLOBAL_CFG_SERDES_MODE_SGMII: 710 interface = PHY_INTERFACE_MODE_SGMII; 711 break; 712 713 default: 714 phydev_warn(phydev, "unrecognised serdes mode %u\n", 715 serdes_mode); 716 interface = PHY_INTERFACE_MODE_NA; 717 break; 718 } 719 720 if (interface != PHY_INTERFACE_MODE_NA) 721 __set_bit(interface, possible); 722 } 723 724 return 0; 725} 726 727static int aqr113c_config_init(struct phy_device *phydev) 728{ 729 int ret; 730 731 ret = aqr107_config_init(phydev); 732 if (ret < 0) 733 return ret; 734 735 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_TXDIS, 736 MDIO_PMD_TXDIS_GLOBAL); 737 if (ret) 738 return ret; 739 740 ret = aqr107_wait_processor_intensive_op(phydev); 741 if (ret) 742 return ret; 743 744 return aqr107_fill_interface_modes(phydev); 745} 746 747static int aqr107_probe(struct phy_device *phydev) 748{ 749 int ret; 750 751 phydev->priv = devm_kzalloc(&phydev->mdio.dev, 752 sizeof(struct aqr107_priv), GFP_KERNEL); 753 if (!phydev->priv) 754 return -ENOMEM; 755 756 ret = aqr_firmware_load(phydev); 757 if (ret) 758 return ret; 759 760 return aqr_hwmon_probe(phydev); 761} 762 763static int aqr111_config_init(struct phy_device *phydev) 764{ 765 /* AQR111 reports supporting speed up to 10G, 766 * however only speeds up to 5G are supported. 767 */ 768 phy_set_max_speed(phydev, SPEED_5000); 769 770 return aqr107_config_init(phydev); 771} 772 773static struct phy_driver aqr_driver[] = { 774{ 775 PHY_ID_MATCH_MODEL(PHY_ID_AQ1202), 776 .name = "Aquantia AQ1202", 777 .config_aneg = aqr_config_aneg, 778 .config_intr = aqr_config_intr, 779 .handle_interrupt = aqr_handle_interrupt, 780 .read_status = aqr_read_status, 781}, 782{ 783 PHY_ID_MATCH_MODEL(PHY_ID_AQ2104), 784 .name = "Aquantia AQ2104", 785 .config_aneg = aqr_config_aneg, 786 .config_intr = aqr_config_intr, 787 .handle_interrupt = aqr_handle_interrupt, 788 .read_status = aqr_read_status, 789}, 790{ 791 PHY_ID_MATCH_MODEL(PHY_ID_AQR105), 792 .name = "Aquantia AQR105", 793 .config_aneg = aqr_config_aneg, 794 .config_intr = aqr_config_intr, 795 .handle_interrupt = aqr_handle_interrupt, 796 .read_status = aqr_read_status, 797 .suspend = aqr107_suspend, 798 .resume = aqr107_resume, 799}, 800{ 801 PHY_ID_MATCH_MODEL(PHY_ID_AQR106), 802 .name = "Aquantia AQR106", 803 .config_aneg = aqr_config_aneg, 804 .config_intr = aqr_config_intr, 805 .handle_interrupt = aqr_handle_interrupt, 806 .read_status = aqr_read_status, 807}, 808{ 809 PHY_ID_MATCH_MODEL(PHY_ID_AQR107), 810 .name = "Aquantia AQR107", 811 .probe = aqr107_probe, 812 .get_rate_matching = aqr107_get_rate_matching, 813 .config_init = aqr107_config_init, 814 .config_aneg = aqr_config_aneg, 815 .config_intr = aqr_config_intr, 816 .handle_interrupt = aqr_handle_interrupt, 817 .read_status = aqr107_read_status, 818 .get_tunable = aqr107_get_tunable, 819 .set_tunable = aqr107_set_tunable, 820 .suspend = aqr107_suspend, 821 .resume = aqr107_resume, 822 .get_sset_count = aqr107_get_sset_count, 823 .get_strings = aqr107_get_strings, 824 .get_stats = aqr107_get_stats, 825 .link_change_notify = aqr107_link_change_notify, 826}, 827{ 828 PHY_ID_MATCH_MODEL(PHY_ID_AQCS109), 829 .name = "Aquantia AQCS109", 830 .probe = aqr107_probe, 831 .get_rate_matching = aqr107_get_rate_matching, 832 .config_init = aqcs109_config_init, 833 .config_aneg = aqr_config_aneg, 834 .config_intr = aqr_config_intr, 835 .handle_interrupt = aqr_handle_interrupt, 836 .read_status = aqr107_read_status, 837 .get_tunable = aqr107_get_tunable, 838 .set_tunable = aqr107_set_tunable, 839 .suspend = aqr107_suspend, 840 .resume = aqr107_resume, 841 .get_sset_count = aqr107_get_sset_count, 842 .get_strings = aqr107_get_strings, 843 .get_stats = aqr107_get_stats, 844 .link_change_notify = aqr107_link_change_notify, 845}, 846{ 847 PHY_ID_MATCH_MODEL(PHY_ID_AQR111), 848 .name = "Aquantia AQR111", 849 .probe = aqr107_probe, 850 .get_rate_matching = aqr107_get_rate_matching, 851 .config_init = aqr111_config_init, 852 .config_aneg = aqr_config_aneg, 853 .config_intr = aqr_config_intr, 854 .handle_interrupt = aqr_handle_interrupt, 855 .read_status = aqr107_read_status, 856 .get_tunable = aqr107_get_tunable, 857 .set_tunable = aqr107_set_tunable, 858 .suspend = aqr107_suspend, 859 .resume = aqr107_resume, 860 .get_sset_count = aqr107_get_sset_count, 861 .get_strings = aqr107_get_strings, 862 .get_stats = aqr107_get_stats, 863 .link_change_notify = aqr107_link_change_notify, 864}, 865{ 866 PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0), 867 .name = "Aquantia AQR111B0", 868 .probe = aqr107_probe, 869 .get_rate_matching = aqr107_get_rate_matching, 870 .config_init = aqr111_config_init, 871 .config_aneg = aqr_config_aneg, 872 .config_intr = aqr_config_intr, 873 .handle_interrupt = aqr_handle_interrupt, 874 .read_status = aqr107_read_status, 875 .get_tunable = aqr107_get_tunable, 876 .set_tunable = aqr107_set_tunable, 877 .suspend = aqr107_suspend, 878 .resume = aqr107_resume, 879 .get_sset_count = aqr107_get_sset_count, 880 .get_strings = aqr107_get_strings, 881 .get_stats = aqr107_get_stats, 882 .link_change_notify = aqr107_link_change_notify, 883}, 884{ 885 PHY_ID_MATCH_MODEL(PHY_ID_AQR405), 886 .name = "Aquantia AQR405", 887 .config_aneg = aqr_config_aneg, 888 .config_intr = aqr_config_intr, 889 .handle_interrupt = aqr_handle_interrupt, 890 .read_status = aqr_read_status, 891}, 892{ 893 PHY_ID_MATCH_MODEL(PHY_ID_AQR112), 894 .name = "Aquantia AQR112", 895 .probe = aqr107_probe, 896 .config_aneg = aqr_config_aneg, 897 .config_intr = aqr_config_intr, 898 .handle_interrupt = aqr_handle_interrupt, 899 .get_tunable = aqr107_get_tunable, 900 .set_tunable = aqr107_set_tunable, 901 .suspend = aqr107_suspend, 902 .resume = aqr107_resume, 903 .read_status = aqr107_read_status, 904 .get_rate_matching = aqr107_get_rate_matching, 905 .get_sset_count = aqr107_get_sset_count, 906 .get_strings = aqr107_get_strings, 907 .get_stats = aqr107_get_stats, 908 .link_change_notify = aqr107_link_change_notify, 909}, 910{ 911 PHY_ID_MATCH_MODEL(PHY_ID_AQR412), 912 .name = "Aquantia AQR412", 913 .probe = aqr107_probe, 914 .config_aneg = aqr_config_aneg, 915 .config_intr = aqr_config_intr, 916 .handle_interrupt = aqr_handle_interrupt, 917 .get_tunable = aqr107_get_tunable, 918 .set_tunable = aqr107_set_tunable, 919 .suspend = aqr107_suspend, 920 .resume = aqr107_resume, 921 .read_status = aqr107_read_status, 922 .get_rate_matching = aqr107_get_rate_matching, 923 .get_sset_count = aqr107_get_sset_count, 924 .get_strings = aqr107_get_strings, 925 .get_stats = aqr107_get_stats, 926 .link_change_notify = aqr107_link_change_notify, 927}, 928{ 929 PHY_ID_MATCH_MODEL(PHY_ID_AQR113), 930 .name = "Aquantia AQR113", 931 .probe = aqr107_probe, 932 .get_rate_matching = aqr107_get_rate_matching, 933 .config_init = aqr113c_config_init, 934 .config_aneg = aqr_config_aneg, 935 .config_intr = aqr_config_intr, 936 .handle_interrupt = aqr_handle_interrupt, 937 .read_status = aqr107_read_status, 938 .get_tunable = aqr107_get_tunable, 939 .set_tunable = aqr107_set_tunable, 940 .suspend = aqr107_suspend, 941 .resume = aqr107_resume, 942 .get_sset_count = aqr107_get_sset_count, 943 .get_strings = aqr107_get_strings, 944 .get_stats = aqr107_get_stats, 945 .link_change_notify = aqr107_link_change_notify, 946}, 947{ 948 PHY_ID_MATCH_MODEL(PHY_ID_AQR113C), 949 .name = "Aquantia AQR113C", 950 .probe = aqr107_probe, 951 .get_rate_matching = aqr107_get_rate_matching, 952 .config_init = aqr113c_config_init, 953 .config_aneg = aqr_config_aneg, 954 .config_intr = aqr_config_intr, 955 .handle_interrupt = aqr_handle_interrupt, 956 .read_status = aqr107_read_status, 957 .get_tunable = aqr107_get_tunable, 958 .set_tunable = aqr107_set_tunable, 959 .suspend = aqr107_suspend, 960 .resume = aqr107_resume, 961 .get_sset_count = aqr107_get_sset_count, 962 .get_strings = aqr107_get_strings, 963 .get_stats = aqr107_get_stats, 964 .link_change_notify = aqr107_link_change_notify, 965}, 966{ 967 PHY_ID_MATCH_MODEL(PHY_ID_AQR114C), 968 .name = "Aquantia AQR114C", 969 .probe = aqr107_probe, 970 .get_rate_matching = aqr107_get_rate_matching, 971 .config_init = aqr111_config_init, 972 .config_aneg = aqr_config_aneg, 973 .config_intr = aqr_config_intr, 974 .handle_interrupt = aqr_handle_interrupt, 975 .read_status = aqr107_read_status, 976 .get_tunable = aqr107_get_tunable, 977 .set_tunable = aqr107_set_tunable, 978 .suspend = aqr107_suspend, 979 .resume = aqr107_resume, 980 .get_sset_count = aqr107_get_sset_count, 981 .get_strings = aqr107_get_strings, 982 .get_stats = aqr107_get_stats, 983 .link_change_notify = aqr107_link_change_notify, 984}, 985{ 986 PHY_ID_MATCH_MODEL(PHY_ID_AQR813), 987 .name = "Aquantia AQR813", 988 .probe = aqr107_probe, 989 .get_rate_matching = aqr107_get_rate_matching, 990 .config_init = aqr107_config_init, 991 .config_aneg = aqr_config_aneg, 992 .config_intr = aqr_config_intr, 993 .handle_interrupt = aqr_handle_interrupt, 994 .read_status = aqr107_read_status, 995 .get_tunable = aqr107_get_tunable, 996 .set_tunable = aqr107_set_tunable, 997 .suspend = aqr107_suspend, 998 .resume = aqr107_resume, 999 .get_sset_count = aqr107_get_sset_count, 1000 .get_strings = aqr107_get_strings, 1001 .get_stats = aqr107_get_stats, 1002 .link_change_notify = aqr107_link_change_notify, 1003}, 1004}; 1005 1006module_phy_driver(aqr_driver); 1007 1008static struct mdio_device_id __maybe_unused aqr_tbl[] = { 1009 { PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) }, 1010 { PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) }, 1011 { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) }, 1012 { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) }, 1013 { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) }, 1014 { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) }, 1015 { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) }, 1016 { PHY_ID_MATCH_MODEL(PHY_ID_AQR111) }, 1017 { PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0) }, 1018 { PHY_ID_MATCH_MODEL(PHY_ID_AQR112) }, 1019 { PHY_ID_MATCH_MODEL(PHY_ID_AQR412) }, 1020 { PHY_ID_MATCH_MODEL(PHY_ID_AQR113) }, 1021 { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) }, 1022 { PHY_ID_MATCH_MODEL(PHY_ID_AQR114C) }, 1023 { PHY_ID_MATCH_MODEL(PHY_ID_AQR813) }, 1024 { } 1025}; 1026 1027MODULE_DEVICE_TABLE(mdio, aqr_tbl); 1028 1029MODULE_DESCRIPTION("Aquantia PHY driver"); 1030MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie@freescale.com>"); 1031MODULE_LICENSE("GPL v2"); 1032