1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * i8042 keyboard and mouse controller driver for Linux 4 * 5 * Copyright (c) 1999-2004 Vojtech Pavlik 6 */ 7 8 9#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11#include <linux/types.h> 12#include <linux/delay.h> 13#include <linux/module.h> 14#include <linux/interrupt.h> 15#include <linux/ioport.h> 16#include <linux/init.h> 17#include <linux/serio.h> 18#include <linux/err.h> 19#include <linux/rcupdate.h> 20#include <linux/platform_device.h> 21#include <linux/i8042.h> 22#include <linux/slab.h> 23#include <linux/suspend.h> 24#include <linux/property.h> 25 26#include <asm/io.h> 27 28MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>"); 29MODULE_DESCRIPTION("i8042 keyboard and mouse controller driver"); 30MODULE_LICENSE("GPL"); 31 32static bool i8042_nokbd; 33module_param_named(nokbd, i8042_nokbd, bool, 0); 34MODULE_PARM_DESC(nokbd, "Do not probe or use KBD port."); 35 36static bool i8042_noaux; 37module_param_named(noaux, i8042_noaux, bool, 0); 38MODULE_PARM_DESC(noaux, "Do not probe or use AUX (mouse) port."); 39 40static bool i8042_nomux; 41module_param_named(nomux, i8042_nomux, bool, 0); 42MODULE_PARM_DESC(nomux, "Do not check whether an active multiplexing controller is present."); 43 44static bool i8042_unlock; 45module_param_named(unlock, i8042_unlock, bool, 0); 46MODULE_PARM_DESC(unlock, "Ignore keyboard lock."); 47 48static bool i8042_probe_defer; 49module_param_named(probe_defer, i8042_probe_defer, bool, 0); 50MODULE_PARM_DESC(probe_defer, "Allow deferred probing."); 51 52enum i8042_controller_reset_mode { 53 I8042_RESET_NEVER, 54 I8042_RESET_ALWAYS, 55 I8042_RESET_ON_S2RAM, 56#define I8042_RESET_DEFAULT I8042_RESET_ON_S2RAM 57}; 58static enum i8042_controller_reset_mode i8042_reset = I8042_RESET_DEFAULT; 59static int i8042_set_reset(const char *val, const struct kernel_param *kp) 60{ 61 enum i8042_controller_reset_mode *arg = kp->arg; 62 int error; 63 bool reset; 64 65 if (val) { 66 error = kstrtobool(val, &reset); 67 if (error) 68 return error; 69 } else { 70 reset = true; 71 } 72 73 *arg = reset ? I8042_RESET_ALWAYS : I8042_RESET_NEVER; 74 return 0; 75} 76 77static const struct kernel_param_ops param_ops_reset_param = { 78 .flags = KERNEL_PARAM_OPS_FL_NOARG, 79 .set = i8042_set_reset, 80}; 81#define param_check_reset_param(name, p) \ 82 __param_check(name, p, enum i8042_controller_reset_mode) 83module_param_named(reset, i8042_reset, reset_param, 0); 84MODULE_PARM_DESC(reset, "Reset controller on resume, cleanup or both"); 85 86static bool i8042_direct; 87module_param_named(direct, i8042_direct, bool, 0); 88MODULE_PARM_DESC(direct, "Put keyboard port into non-translated mode."); 89 90static bool i8042_dumbkbd; 91module_param_named(dumbkbd, i8042_dumbkbd, bool, 0); 92MODULE_PARM_DESC(dumbkbd, "Pretend that controller can only read data from keyboard"); 93 94static bool i8042_noloop; 95module_param_named(noloop, i8042_noloop, bool, 0); 96MODULE_PARM_DESC(noloop, "Disable the AUX Loopback command while probing for the AUX port"); 97 98static bool i8042_notimeout; 99module_param_named(notimeout, i8042_notimeout, bool, 0); 100MODULE_PARM_DESC(notimeout, "Ignore timeouts signalled by i8042"); 101 102static bool i8042_kbdreset; 103module_param_named(kbdreset, i8042_kbdreset, bool, 0); 104MODULE_PARM_DESC(kbdreset, "Reset device connected to KBD port"); 105 106#ifdef CONFIG_X86 107static bool i8042_dritek; 108module_param_named(dritek, i8042_dritek, bool, 0); 109MODULE_PARM_DESC(dritek, "Force enable the Dritek keyboard extension"); 110#endif 111 112#ifdef CONFIG_PNP 113static bool i8042_nopnp; 114module_param_named(nopnp, i8042_nopnp, bool, 0); 115MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings"); 116#endif 117 118#define DEBUG 119#ifdef DEBUG 120static bool i8042_debug; 121module_param_named(debug, i8042_debug, bool, 0600); 122MODULE_PARM_DESC(debug, "Turn i8042 debugging mode on and off"); 123 124static bool i8042_unmask_kbd_data; 125module_param_named(unmask_kbd_data, i8042_unmask_kbd_data, bool, 0600); 126MODULE_PARM_DESC(unmask_kbd_data, "Unconditional enable (may reveal sensitive data) of normally sanitize-filtered kbd data traffic debug log [pre-condition: i8042.debug=1 enabled]"); 127#endif 128 129static bool i8042_present; 130static bool i8042_bypass_aux_irq_test; 131static char i8042_kbd_firmware_id[128]; 132static char i8042_aux_firmware_id[128]; 133static struct fwnode_handle *i8042_kbd_fwnode; 134 135#include "i8042.h" 136 137/* 138 * i8042_lock protects serialization between i8042_command and 139 * the interrupt handler. 140 */ 141static DEFINE_SPINLOCK(i8042_lock); 142 143/* 144 * Writers to AUX and KBD ports as well as users issuing i8042_command 145 * directly should acquire i8042_mutex (by means of calling 146 * i8042_lock_chip() and i8042_unlock_chip() helpers) to ensure that 147 * they do not disturb each other (unfortunately in many i8042 148 * implementations write to one of the ports will immediately abort 149 * command that is being processed by another port). 150 */ 151static DEFINE_MUTEX(i8042_mutex); 152 153struct i8042_port { 154 struct serio *serio; 155 int irq; 156 bool exists; 157 bool driver_bound; 158 signed char mux; 159}; 160 161#define I8042_KBD_PORT_NO 0 162#define I8042_AUX_PORT_NO 1 163#define I8042_MUX_PORT_NO 2 164#define I8042_NUM_PORTS (I8042_NUM_MUX_PORTS + 2) 165 166static struct i8042_port i8042_ports[I8042_NUM_PORTS]; 167 168static unsigned char i8042_initial_ctr; 169static unsigned char i8042_ctr; 170static bool i8042_mux_present; 171static bool i8042_kbd_irq_registered; 172static bool i8042_aux_irq_registered; 173static unsigned char i8042_suppress_kbd_ack; 174static struct platform_device *i8042_platform_device; 175static struct notifier_block i8042_kbd_bind_notifier_block; 176 177static irqreturn_t i8042_interrupt(int irq, void *dev_id); 178static bool (*i8042_platform_filter)(unsigned char data, unsigned char str, 179 struct serio *serio); 180 181void i8042_lock_chip(void) 182{ 183 mutex_lock(&i8042_mutex); 184} 185EXPORT_SYMBOL(i8042_lock_chip); 186 187void i8042_unlock_chip(void) 188{ 189 mutex_unlock(&i8042_mutex); 190} 191EXPORT_SYMBOL(i8042_unlock_chip); 192 193int i8042_install_filter(bool (*filter)(unsigned char data, unsigned char str, 194 struct serio *serio)) 195{ 196 unsigned long flags; 197 int ret = 0; 198 199 spin_lock_irqsave(&i8042_lock, flags); 200 201 if (i8042_platform_filter) { 202 ret = -EBUSY; 203 goto out; 204 } 205 206 i8042_platform_filter = filter; 207 208out: 209 spin_unlock_irqrestore(&i8042_lock, flags); 210 return ret; 211} 212EXPORT_SYMBOL(i8042_install_filter); 213 214int i8042_remove_filter(bool (*filter)(unsigned char data, unsigned char str, 215 struct serio *port)) 216{ 217 unsigned long flags; 218 int ret = 0; 219 220 spin_lock_irqsave(&i8042_lock, flags); 221 222 if (i8042_platform_filter != filter) { 223 ret = -EINVAL; 224 goto out; 225 } 226 227 i8042_platform_filter = NULL; 228 229out: 230 spin_unlock_irqrestore(&i8042_lock, flags); 231 return ret; 232} 233EXPORT_SYMBOL(i8042_remove_filter); 234 235/* 236 * The i8042_wait_read() and i8042_wait_write functions wait for the i8042 to 237 * be ready for reading values from it / writing values to it. 238 * Called always with i8042_lock held. 239 */ 240 241static int i8042_wait_read(void) 242{ 243 int i = 0; 244 245 while ((~i8042_read_status() & I8042_STR_OBF) && (i < I8042_CTL_TIMEOUT)) { 246 udelay(50); 247 i++; 248 } 249 return -(i == I8042_CTL_TIMEOUT); 250} 251 252static int i8042_wait_write(void) 253{ 254 int i = 0; 255 256 while ((i8042_read_status() & I8042_STR_IBF) && (i < I8042_CTL_TIMEOUT)) { 257 udelay(50); 258 i++; 259 } 260 return -(i == I8042_CTL_TIMEOUT); 261} 262 263/* 264 * i8042_flush() flushes all data that may be in the keyboard and mouse buffers 265 * of the i8042 down the toilet. 266 */ 267 268static int i8042_flush(void) 269{ 270 unsigned long flags; 271 unsigned char data, str; 272 int count = 0; 273 int retval = 0; 274 275 spin_lock_irqsave(&i8042_lock, flags); 276 277 while ((str = i8042_read_status()) & I8042_STR_OBF) { 278 if (count++ < I8042_BUFFER_SIZE) { 279 udelay(50); 280 data = i8042_read_data(); 281 dbg("%02x <- i8042 (flush, %s)\n", 282 data, str & I8042_STR_AUXDATA ? "aux" : "kbd"); 283 } else { 284 retval = -EIO; 285 break; 286 } 287 } 288 289 spin_unlock_irqrestore(&i8042_lock, flags); 290 291 return retval; 292} 293 294/* 295 * i8042_command() executes a command on the i8042. It also sends the input 296 * parameter(s) of the commands to it, and receives the output value(s). The 297 * parameters are to be stored in the param array, and the output is placed 298 * into the same array. The number of the parameters and output values is 299 * encoded in bits 8-11 of the command number. 300 */ 301 302static int __i8042_command(unsigned char *param, int command) 303{ 304 int i, error; 305 306 if (i8042_noloop && command == I8042_CMD_AUX_LOOP) 307 return -1; 308 309 error = i8042_wait_write(); 310 if (error) 311 return error; 312 313 dbg("%02x -> i8042 (command)\n", command & 0xff); 314 i8042_write_command(command & 0xff); 315 316 for (i = 0; i < ((command >> 12) & 0xf); i++) { 317 error = i8042_wait_write(); 318 if (error) { 319 dbg(" -- i8042 (wait write timeout)\n"); 320 return error; 321 } 322 dbg("%02x -> i8042 (parameter)\n", param[i]); 323 i8042_write_data(param[i]); 324 } 325 326 for (i = 0; i < ((command >> 8) & 0xf); i++) { 327 error = i8042_wait_read(); 328 if (error) { 329 dbg(" -- i8042 (wait read timeout)\n"); 330 return error; 331 } 332 333 if (command == I8042_CMD_AUX_LOOP && 334 !(i8042_read_status() & I8042_STR_AUXDATA)) { 335 dbg(" -- i8042 (auxerr)\n"); 336 return -1; 337 } 338 339 param[i] = i8042_read_data(); 340 dbg("%02x <- i8042 (return)\n", param[i]); 341 } 342 343 return 0; 344} 345 346int i8042_command(unsigned char *param, int command) 347{ 348 unsigned long flags; 349 int retval; 350 351 if (!i8042_present) 352 return -1; 353 354 spin_lock_irqsave(&i8042_lock, flags); 355 retval = __i8042_command(param, command); 356 spin_unlock_irqrestore(&i8042_lock, flags); 357 358 return retval; 359} 360EXPORT_SYMBOL(i8042_command); 361 362/* 363 * i8042_kbd_write() sends a byte out through the keyboard interface. 364 */ 365 366static int i8042_kbd_write(struct serio *port, unsigned char c) 367{ 368 unsigned long flags; 369 int retval = 0; 370 371 spin_lock_irqsave(&i8042_lock, flags); 372 373 if (!(retval = i8042_wait_write())) { 374 dbg("%02x -> i8042 (kbd-data)\n", c); 375 i8042_write_data(c); 376 } 377 378 spin_unlock_irqrestore(&i8042_lock, flags); 379 380 return retval; 381} 382 383/* 384 * i8042_aux_write() sends a byte out through the aux interface. 385 */ 386 387static int i8042_aux_write(struct serio *serio, unsigned char c) 388{ 389 struct i8042_port *port = serio->port_data; 390 391 return i8042_command(&c, port->mux == -1 ? 392 I8042_CMD_AUX_SEND : 393 I8042_CMD_MUX_SEND + port->mux); 394} 395 396 397/* 398 * i8042_port_close attempts to clear AUX or KBD port state by disabling 399 * and then re-enabling it. 400 */ 401 402static void i8042_port_close(struct serio *serio) 403{ 404 int irq_bit; 405 int disable_bit; 406 const char *port_name; 407 408 if (serio == i8042_ports[I8042_AUX_PORT_NO].serio) { 409 irq_bit = I8042_CTR_AUXINT; 410 disable_bit = I8042_CTR_AUXDIS; 411 port_name = "AUX"; 412 } else { 413 irq_bit = I8042_CTR_KBDINT; 414 disable_bit = I8042_CTR_KBDDIS; 415 port_name = "KBD"; 416 } 417 418 i8042_ctr &= ~irq_bit; 419 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 420 pr_warn("Can't write CTR while closing %s port\n", port_name); 421 422 udelay(50); 423 424 i8042_ctr &= ~disable_bit; 425 i8042_ctr |= irq_bit; 426 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 427 pr_err("Can't reactivate %s port\n", port_name); 428 429 /* 430 * See if there is any data appeared while we were messing with 431 * port state. 432 */ 433 i8042_interrupt(0, NULL); 434} 435 436/* 437 * i8042_start() is called by serio core when port is about to finish 438 * registering. It will mark port as existing so i8042_interrupt can 439 * start sending data through it. 440 */ 441static int i8042_start(struct serio *serio) 442{ 443 struct i8042_port *port = serio->port_data; 444 445 device_set_wakeup_capable(&serio->dev, true); 446 447 /* 448 * On platforms using suspend-to-idle, allow the keyboard to 449 * wake up the system from sleep by enabling keyboard wakeups 450 * by default. This is consistent with keyboard wakeup 451 * behavior on many platforms using suspend-to-RAM (ACPI S3) 452 * by default. 453 */ 454 if (pm_suspend_default_s2idle() && 455 serio == i8042_ports[I8042_KBD_PORT_NO].serio) { 456 device_set_wakeup_enable(&serio->dev, true); 457 } 458 459 spin_lock_irq(&i8042_lock); 460 port->exists = true; 461 spin_unlock_irq(&i8042_lock); 462 463 return 0; 464} 465 466/* 467 * i8042_stop() marks serio port as non-existing so i8042_interrupt 468 * will not try to send data to the port that is about to go away. 469 * The function is called by serio core as part of unregister procedure. 470 */ 471static void i8042_stop(struct serio *serio) 472{ 473 struct i8042_port *port = serio->port_data; 474 475 spin_lock_irq(&i8042_lock); 476 port->exists = false; 477 port->serio = NULL; 478 spin_unlock_irq(&i8042_lock); 479 480 /* 481 * We need to make sure that interrupt handler finishes using 482 * our serio port before we return from this function. 483 * We synchronize with both AUX and KBD IRQs because there is 484 * a (very unlikely) chance that AUX IRQ is raised for KBD port 485 * and vice versa. 486 */ 487 synchronize_irq(I8042_AUX_IRQ); 488 synchronize_irq(I8042_KBD_IRQ); 489} 490 491/* 492 * i8042_filter() filters out unwanted bytes from the input data stream. 493 * It is called from i8042_interrupt and thus is running with interrupts 494 * off and i8042_lock held. 495 */ 496static bool i8042_filter(unsigned char data, unsigned char str, 497 struct serio *serio) 498{ 499 if (unlikely(i8042_suppress_kbd_ack)) { 500 if ((~str & I8042_STR_AUXDATA) && 501 (data == 0xfa || data == 0xfe)) { 502 i8042_suppress_kbd_ack--; 503 dbg("Extra keyboard ACK - filtered out\n"); 504 return true; 505 } 506 } 507 508 if (i8042_platform_filter && i8042_platform_filter(data, str, serio)) { 509 dbg("Filtered out by platform filter\n"); 510 return true; 511 } 512 513 return false; 514} 515 516/* 517 * i8042_interrupt() is the most important function in this driver - 518 * it handles the interrupts from the i8042, and sends incoming bytes 519 * to the upper layers. 520 */ 521 522static irqreturn_t i8042_interrupt(int irq, void *dev_id) 523{ 524 struct i8042_port *port; 525 struct serio *serio; 526 unsigned long flags; 527 unsigned char str, data; 528 unsigned int dfl; 529 unsigned int port_no; 530 bool filtered; 531 int ret = 1; 532 533 spin_lock_irqsave(&i8042_lock, flags); 534 535 str = i8042_read_status(); 536 if (unlikely(~str & I8042_STR_OBF)) { 537 spin_unlock_irqrestore(&i8042_lock, flags); 538 if (irq) 539 dbg("Interrupt %d, without any data\n", irq); 540 ret = 0; 541 goto out; 542 } 543 544 data = i8042_read_data(); 545 546 if (i8042_mux_present && (str & I8042_STR_AUXDATA)) { 547 static unsigned long last_transmit; 548 static unsigned char last_str; 549 550 dfl = 0; 551 if (str & I8042_STR_MUXERR) { 552 dbg("MUX error, status is %02x, data is %02x\n", 553 str, data); 554/* 555 * When MUXERR condition is signalled the data register can only contain 556 * 0xfd, 0xfe or 0xff if implementation follows the spec. Unfortunately 557 * it is not always the case. Some KBCs also report 0xfc when there is 558 * nothing connected to the port while others sometimes get confused which 559 * port the data came from and signal error leaving the data intact. They 560 * _do not_ revert to legacy mode (actually I've never seen KBC reverting 561 * to legacy mode yet, when we see one we'll add proper handling). 562 * Anyway, we process 0xfc, 0xfd, 0xfe and 0xff as timeouts, and for the 563 * rest assume that the data came from the same serio last byte 564 * was transmitted (if transmission happened not too long ago). 565 */ 566 567 switch (data) { 568 default: 569 if (time_before(jiffies, last_transmit + HZ/10)) { 570 str = last_str; 571 break; 572 } 573 fallthrough; /* report timeout */ 574 case 0xfc: 575 case 0xfd: 576 case 0xfe: dfl = SERIO_TIMEOUT; data = 0xfe; break; 577 case 0xff: dfl = SERIO_PARITY; data = 0xfe; break; 578 } 579 } 580 581 port_no = I8042_MUX_PORT_NO + ((str >> 6) & 3); 582 last_str = str; 583 last_transmit = jiffies; 584 } else { 585 586 dfl = ((str & I8042_STR_PARITY) ? SERIO_PARITY : 0) | 587 ((str & I8042_STR_TIMEOUT && !i8042_notimeout) ? SERIO_TIMEOUT : 0); 588 589 port_no = (str & I8042_STR_AUXDATA) ? 590 I8042_AUX_PORT_NO : I8042_KBD_PORT_NO; 591 } 592 593 port = &i8042_ports[port_no]; 594 serio = port->exists ? port->serio : NULL; 595 596 filter_dbg(port->driver_bound, data, "<- i8042 (interrupt, %d, %d%s%s)\n", 597 port_no, irq, 598 dfl & SERIO_PARITY ? ", bad parity" : "", 599 dfl & SERIO_TIMEOUT ? ", timeout" : ""); 600 601 filtered = i8042_filter(data, str, serio); 602 603 spin_unlock_irqrestore(&i8042_lock, flags); 604 605 if (likely(serio && !filtered)) 606 serio_interrupt(serio, data, dfl); 607 608 out: 609 return IRQ_RETVAL(ret); 610} 611 612/* 613 * i8042_enable_kbd_port enables keyboard port on chip 614 */ 615 616static int i8042_enable_kbd_port(void) 617{ 618 i8042_ctr &= ~I8042_CTR_KBDDIS; 619 i8042_ctr |= I8042_CTR_KBDINT; 620 621 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 622 i8042_ctr &= ~I8042_CTR_KBDINT; 623 i8042_ctr |= I8042_CTR_KBDDIS; 624 pr_err("Failed to enable KBD port\n"); 625 return -EIO; 626 } 627 628 return 0; 629} 630 631/* 632 * i8042_enable_aux_port enables AUX (mouse) port on chip 633 */ 634 635static int i8042_enable_aux_port(void) 636{ 637 i8042_ctr &= ~I8042_CTR_AUXDIS; 638 i8042_ctr |= I8042_CTR_AUXINT; 639 640 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 641 i8042_ctr &= ~I8042_CTR_AUXINT; 642 i8042_ctr |= I8042_CTR_AUXDIS; 643 pr_err("Failed to enable AUX port\n"); 644 return -EIO; 645 } 646 647 return 0; 648} 649 650/* 651 * i8042_enable_mux_ports enables 4 individual AUX ports after 652 * the controller has been switched into Multiplexed mode 653 */ 654 655static int i8042_enable_mux_ports(void) 656{ 657 unsigned char param; 658 int i; 659 660 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { 661 i8042_command(¶m, I8042_CMD_MUX_PFX + i); 662 i8042_command(¶m, I8042_CMD_AUX_ENABLE); 663 } 664 665 return i8042_enable_aux_port(); 666} 667 668/* 669 * i8042_set_mux_mode checks whether the controller has an 670 * active multiplexor and puts the chip into Multiplexed (true) 671 * or Legacy (false) mode. 672 */ 673 674static int i8042_set_mux_mode(bool multiplex, unsigned char *mux_version) 675{ 676 677 unsigned char param, val; 678/* 679 * Get rid of bytes in the queue. 680 */ 681 682 i8042_flush(); 683 684/* 685 * Internal loopback test - send three bytes, they should come back from the 686 * mouse interface, the last should be version. 687 */ 688 689 param = val = 0xf0; 690 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val) 691 return -1; 692 param = val = multiplex ? 0x56 : 0xf6; 693 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param != val) 694 return -1; 695 param = val = multiplex ? 0xa4 : 0xa5; 696 if (i8042_command(¶m, I8042_CMD_AUX_LOOP) || param == val) 697 return -1; 698 699/* 700 * Workaround for interference with USB Legacy emulation 701 * that causes a v10.12 MUX to be found. 702 */ 703 if (param == 0xac) 704 return -1; 705 706 if (mux_version) 707 *mux_version = param; 708 709 return 0; 710} 711 712/* 713 * i8042_check_mux() checks whether the controller supports the PS/2 Active 714 * Multiplexing specification by Synaptics, Phoenix, Insyde and 715 * LCS/Telegraphics. 716 */ 717 718static int i8042_check_mux(void) 719{ 720 unsigned char mux_version; 721 722 if (i8042_set_mux_mode(true, &mux_version)) 723 return -1; 724 725 pr_info("Detected active multiplexing controller, rev %d.%d\n", 726 (mux_version >> 4) & 0xf, mux_version & 0xf); 727 728/* 729 * Disable all muxed ports by disabling AUX. 730 */ 731 i8042_ctr |= I8042_CTR_AUXDIS; 732 i8042_ctr &= ~I8042_CTR_AUXINT; 733 734 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 735 pr_err("Failed to disable AUX port, can't use MUX\n"); 736 return -EIO; 737 } 738 739 i8042_mux_present = true; 740 741 return 0; 742} 743 744/* 745 * The following is used to test AUX IRQ delivery. 746 */ 747static struct completion i8042_aux_irq_delivered; 748static bool i8042_irq_being_tested; 749 750static irqreturn_t i8042_aux_test_irq(int irq, void *dev_id) 751{ 752 unsigned long flags; 753 unsigned char str, data; 754 int ret = 0; 755 756 spin_lock_irqsave(&i8042_lock, flags); 757 str = i8042_read_status(); 758 if (str & I8042_STR_OBF) { 759 data = i8042_read_data(); 760 dbg("%02x <- i8042 (aux_test_irq, %s)\n", 761 data, str & I8042_STR_AUXDATA ? "aux" : "kbd"); 762 if (i8042_irq_being_tested && 763 data == 0xa5 && (str & I8042_STR_AUXDATA)) 764 complete(&i8042_aux_irq_delivered); 765 ret = 1; 766 } 767 spin_unlock_irqrestore(&i8042_lock, flags); 768 769 return IRQ_RETVAL(ret); 770} 771 772/* 773 * i8042_toggle_aux - enables or disables AUX port on i8042 via command and 774 * verifies success by readinng CTR. Used when testing for presence of AUX 775 * port. 776 */ 777static int i8042_toggle_aux(bool on) 778{ 779 unsigned char param; 780 int i; 781 782 if (i8042_command(¶m, 783 on ? I8042_CMD_AUX_ENABLE : I8042_CMD_AUX_DISABLE)) 784 return -1; 785 786 /* some chips need some time to set the I8042_CTR_AUXDIS bit */ 787 for (i = 0; i < 100; i++) { 788 udelay(50); 789 790 if (i8042_command(¶m, I8042_CMD_CTL_RCTR)) 791 return -1; 792 793 if (!(param & I8042_CTR_AUXDIS) == on) 794 return 0; 795 } 796 797 return -1; 798} 799 800/* 801 * i8042_check_aux() applies as much paranoia as it can at detecting 802 * the presence of an AUX interface. 803 */ 804 805static int i8042_check_aux(void) 806{ 807 int retval = -1; 808 bool irq_registered = false; 809 bool aux_loop_broken = false; 810 unsigned long flags; 811 unsigned char param; 812 813/* 814 * Get rid of bytes in the queue. 815 */ 816 817 i8042_flush(); 818 819/* 820 * Internal loopback test - filters out AT-type i8042's. Unfortunately 821 * SiS screwed up and their 5597 doesn't support the LOOP command even 822 * though it has an AUX port. 823 */ 824 825 param = 0x5a; 826 retval = i8042_command(¶m, I8042_CMD_AUX_LOOP); 827 if (retval || param != 0x5a) { 828 829/* 830 * External connection test - filters out AT-soldered PS/2 i8042's 831 * 0x00 - no error, 0x01-0x03 - clock/data stuck, 0xff - general error 832 * 0xfa - no error on some notebooks which ignore the spec 833 * Because it's common for chipsets to return error on perfectly functioning 834 * AUX ports, we test for this only when the LOOP command failed. 835 */ 836 837 if (i8042_command(¶m, I8042_CMD_AUX_TEST) || 838 (param && param != 0xfa && param != 0xff)) 839 return -1; 840 841/* 842 * If AUX_LOOP completed without error but returned unexpected data 843 * mark it as broken 844 */ 845 if (!retval) 846 aux_loop_broken = true; 847 } 848 849/* 850 * Bit assignment test - filters out PS/2 i8042's in AT mode 851 */ 852 853 if (i8042_toggle_aux(false)) { 854 pr_warn("Failed to disable AUX port, but continuing anyway... Is this a SiS?\n"); 855 pr_warn("If AUX port is really absent please use the 'i8042.noaux' option\n"); 856 } 857 858 if (i8042_toggle_aux(true)) 859 return -1; 860 861/* 862 * Reset keyboard (needed on some laptops to successfully detect 863 * touchpad, e.g., some Gigabyte laptop models with Elantech 864 * touchpads). 865 */ 866 if (i8042_kbdreset) { 867 pr_warn("Attempting to reset device connected to KBD port\n"); 868 i8042_kbd_write(NULL, (unsigned char) 0xff); 869 } 870 871/* 872 * Test AUX IRQ delivery to make sure BIOS did not grab the IRQ and 873 * used it for a PCI card or somethig else. 874 */ 875 876 if (i8042_noloop || i8042_bypass_aux_irq_test || aux_loop_broken) { 877/* 878 * Without LOOP command we can't test AUX IRQ delivery. Assume the port 879 * is working and hope we are right. 880 */ 881 retval = 0; 882 goto out; 883 } 884 885 if (request_irq(I8042_AUX_IRQ, i8042_aux_test_irq, IRQF_SHARED, 886 "i8042", i8042_platform_device)) 887 goto out; 888 889 irq_registered = true; 890 891 if (i8042_enable_aux_port()) 892 goto out; 893 894 spin_lock_irqsave(&i8042_lock, flags); 895 896 init_completion(&i8042_aux_irq_delivered); 897 i8042_irq_being_tested = true; 898 899 param = 0xa5; 900 retval = __i8042_command(¶m, I8042_CMD_AUX_LOOP & 0xf0ff); 901 902 spin_unlock_irqrestore(&i8042_lock, flags); 903 904 if (retval) 905 goto out; 906 907 if (wait_for_completion_timeout(&i8042_aux_irq_delivered, 908 msecs_to_jiffies(250)) == 0) { 909/* 910 * AUX IRQ was never delivered so we need to flush the controller to 911 * get rid of the byte we put there; otherwise keyboard may not work. 912 */ 913 dbg(" -- i8042 (aux irq test timeout)\n"); 914 i8042_flush(); 915 retval = -1; 916 } 917 918 out: 919 920/* 921 * Disable the interface. 922 */ 923 924 i8042_ctr |= I8042_CTR_AUXDIS; 925 i8042_ctr &= ~I8042_CTR_AUXINT; 926 927 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 928 retval = -1; 929 930 if (irq_registered) 931 free_irq(I8042_AUX_IRQ, i8042_platform_device); 932 933 return retval; 934} 935 936static int i8042_controller_check(void) 937{ 938 if (i8042_flush()) { 939 pr_info("No controller found\n"); 940 return -ENODEV; 941 } 942 943 return 0; 944} 945 946static int i8042_controller_selftest(void) 947{ 948 unsigned char param; 949 int i = 0; 950 951 /* 952 * We try this 5 times; on some really fragile systems this does not 953 * take the first time... 954 */ 955 do { 956 957 if (i8042_command(¶m, I8042_CMD_CTL_TEST)) { 958 pr_err("i8042 controller selftest timeout\n"); 959 return -ENODEV; 960 } 961 962 if (param == I8042_RET_CTL_TEST) 963 return 0; 964 965 dbg("i8042 controller selftest: %#x != %#x\n", 966 param, I8042_RET_CTL_TEST); 967 msleep(50); 968 } while (i++ < 5); 969 970#ifdef CONFIG_X86 971 /* 972 * On x86, we don't fail entire i8042 initialization if controller 973 * reset fails in hopes that keyboard port will still be functional 974 * and user will still get a working keyboard. This is especially 975 * important on netbooks. On other arches we trust hardware more. 976 */ 977 pr_info("giving up on controller selftest, continuing anyway...\n"); 978 return 0; 979#else 980 pr_err("i8042 controller selftest failed\n"); 981 return -EIO; 982#endif 983} 984 985/* 986 * i8042_controller_init initializes the i8042 controller, and, 987 * most importantly, sets it into non-xlated mode if that's 988 * desired. 989 */ 990 991static int i8042_controller_init(void) 992{ 993 unsigned long flags; 994 int n = 0; 995 unsigned char ctr[2]; 996 997/* 998 * Save the CTR for restore on unload / reboot. 999 */ 1000 1001 do { 1002 if (n >= 10) { 1003 pr_err("Unable to get stable CTR read\n"); 1004 return -EIO; 1005 } 1006 1007 if (n != 0) 1008 udelay(50); 1009 1010 if (i8042_command(&ctr[n++ % 2], I8042_CMD_CTL_RCTR)) { 1011 pr_err("Can't read CTR while initializing i8042\n"); 1012 return i8042_probe_defer ? -EPROBE_DEFER : -EIO; 1013 } 1014 1015 } while (n < 2 || ctr[0] != ctr[1]); 1016 1017 i8042_initial_ctr = i8042_ctr = ctr[0]; 1018 1019/* 1020 * Disable the keyboard interface and interrupt. 1021 */ 1022 1023 i8042_ctr |= I8042_CTR_KBDDIS; 1024 i8042_ctr &= ~I8042_CTR_KBDINT; 1025 1026/* 1027 * Handle keylock. 1028 */ 1029 1030 spin_lock_irqsave(&i8042_lock, flags); 1031 if (~i8042_read_status() & I8042_STR_KEYLOCK) { 1032 if (i8042_unlock) 1033 i8042_ctr |= I8042_CTR_IGNKEYLOCK; 1034 else 1035 pr_warn("Warning: Keylock active\n"); 1036 } 1037 spin_unlock_irqrestore(&i8042_lock, flags); 1038 1039/* 1040 * If the chip is configured into nontranslated mode by the BIOS, don't 1041 * bother enabling translating and be happy. 1042 */ 1043 1044 if (~i8042_ctr & I8042_CTR_XLATE) 1045 i8042_direct = true; 1046 1047/* 1048 * Set nontranslated mode for the kbd interface if requested by an option. 1049 * After this the kbd interface becomes a simple serial in/out, like the aux 1050 * interface is. We don't do this by default, since it can confuse notebook 1051 * BIOSes. 1052 */ 1053 1054 if (i8042_direct) 1055 i8042_ctr &= ~I8042_CTR_XLATE; 1056 1057/* 1058 * Write CTR back. 1059 */ 1060 1061 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 1062 pr_err("Can't write CTR while initializing i8042\n"); 1063 return -EIO; 1064 } 1065 1066/* 1067 * Flush whatever accumulated while we were disabling keyboard port. 1068 */ 1069 1070 i8042_flush(); 1071 1072 return 0; 1073} 1074 1075 1076/* 1077 * Reset the controller and reset CRT to the original value set by BIOS. 1078 */ 1079 1080static void i8042_controller_reset(bool s2r_wants_reset) 1081{ 1082 i8042_flush(); 1083 1084/* 1085 * Disable both KBD and AUX interfaces so they don't get in the way 1086 */ 1087 1088 i8042_ctr |= I8042_CTR_KBDDIS | I8042_CTR_AUXDIS; 1089 i8042_ctr &= ~(I8042_CTR_KBDINT | I8042_CTR_AUXINT); 1090 1091 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) 1092 pr_warn("Can't write CTR while resetting\n"); 1093 1094/* 1095 * Disable MUX mode if present. 1096 */ 1097 1098 if (i8042_mux_present) 1099 i8042_set_mux_mode(false, NULL); 1100 1101/* 1102 * Reset the controller if requested. 1103 */ 1104 1105 if (i8042_reset == I8042_RESET_ALWAYS || 1106 (i8042_reset == I8042_RESET_ON_S2RAM && s2r_wants_reset)) { 1107 i8042_controller_selftest(); 1108 } 1109 1110/* 1111 * Restore the original control register setting. 1112 */ 1113 1114 if (i8042_command(&i8042_initial_ctr, I8042_CMD_CTL_WCTR)) 1115 pr_warn("Can't restore CTR\n"); 1116} 1117 1118 1119/* 1120 * i8042_panic_blink() will turn the keyboard LEDs on or off and is called 1121 * when kernel panics. Flashing LEDs is useful for users running X who may 1122 * not see the console and will help distinguishing panics from "real" 1123 * lockups. 1124 * 1125 * Note that DELAY has a limit of 10ms so we will not get stuck here 1126 * waiting for KBC to free up even if KBD interrupt is off 1127 */ 1128 1129#define DELAY do { mdelay(1); if (++delay > 10) return delay; } while(0) 1130 1131static long i8042_panic_blink(int state) 1132{ 1133 long delay = 0; 1134 char led; 1135 1136 led = (state) ? 0x01 | 0x04 : 0; 1137 while (i8042_read_status() & I8042_STR_IBF) 1138 DELAY; 1139 dbg("%02x -> i8042 (panic blink)\n", 0xed); 1140 i8042_suppress_kbd_ack = 2; 1141 i8042_write_data(0xed); /* set leds */ 1142 DELAY; 1143 while (i8042_read_status() & I8042_STR_IBF) 1144 DELAY; 1145 DELAY; 1146 dbg("%02x -> i8042 (panic blink)\n", led); 1147 i8042_write_data(led); 1148 DELAY; 1149 return delay; 1150} 1151 1152#undef DELAY 1153 1154#ifdef CONFIG_X86 1155static void i8042_dritek_enable(void) 1156{ 1157 unsigned char param = 0x90; 1158 int error; 1159 1160 error = i8042_command(¶m, 0x1059); 1161 if (error) 1162 pr_warn("Failed to enable DRITEK extension: %d\n", error); 1163} 1164#endif 1165 1166#ifdef CONFIG_PM 1167 1168/* 1169 * Here we try to reset everything back to a state we had 1170 * before suspending. 1171 */ 1172 1173static int i8042_controller_resume(bool s2r_wants_reset) 1174{ 1175 int error; 1176 1177 error = i8042_controller_check(); 1178 if (error) 1179 return error; 1180 1181 if (i8042_reset == I8042_RESET_ALWAYS || 1182 (i8042_reset == I8042_RESET_ON_S2RAM && s2r_wants_reset)) { 1183 error = i8042_controller_selftest(); 1184 if (error) 1185 return error; 1186 } 1187 1188/* 1189 * Restore original CTR value and disable all ports 1190 */ 1191 1192 i8042_ctr = i8042_initial_ctr; 1193 if (i8042_direct) 1194 i8042_ctr &= ~I8042_CTR_XLATE; 1195 i8042_ctr |= I8042_CTR_AUXDIS | I8042_CTR_KBDDIS; 1196 i8042_ctr &= ~(I8042_CTR_AUXINT | I8042_CTR_KBDINT); 1197 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 1198 pr_warn("Can't write CTR to resume, retrying...\n"); 1199 msleep(50); 1200 if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) { 1201 pr_err("CTR write retry failed\n"); 1202 return -EIO; 1203 } 1204 } 1205 1206 1207#ifdef CONFIG_X86 1208 if (i8042_dritek) 1209 i8042_dritek_enable(); 1210#endif 1211 1212 if (i8042_mux_present) { 1213 if (i8042_set_mux_mode(true, NULL) || i8042_enable_mux_ports()) 1214 pr_warn("failed to resume active multiplexor, mouse won't work\n"); 1215 } else if (i8042_ports[I8042_AUX_PORT_NO].serio) 1216 i8042_enable_aux_port(); 1217 1218 if (i8042_ports[I8042_KBD_PORT_NO].serio) 1219 i8042_enable_kbd_port(); 1220 1221 i8042_interrupt(0, NULL); 1222 1223 return 0; 1224} 1225 1226/* 1227 * Here we try to restore the original BIOS settings to avoid 1228 * upsetting it. 1229 */ 1230 1231static int i8042_pm_suspend(struct device *dev) 1232{ 1233 int i; 1234 1235 if (pm_suspend_via_firmware()) 1236 i8042_controller_reset(true); 1237 1238 /* Set up serio interrupts for system wakeup. */ 1239 for (i = 0; i < I8042_NUM_PORTS; i++) { 1240 struct serio *serio = i8042_ports[i].serio; 1241 1242 if (serio && device_may_wakeup(&serio->dev)) 1243 enable_irq_wake(i8042_ports[i].irq); 1244 } 1245 1246 return 0; 1247} 1248 1249static int i8042_pm_resume_noirq(struct device *dev) 1250{ 1251 if (!pm_resume_via_firmware()) 1252 i8042_interrupt(0, NULL); 1253 1254 return 0; 1255} 1256 1257static int i8042_pm_resume(struct device *dev) 1258{ 1259 bool want_reset; 1260 int i; 1261 1262 for (i = 0; i < I8042_NUM_PORTS; i++) { 1263 struct serio *serio = i8042_ports[i].serio; 1264 1265 if (serio && device_may_wakeup(&serio->dev)) 1266 disable_irq_wake(i8042_ports[i].irq); 1267 } 1268 1269 /* 1270 * If platform firmware was not going to be involved in suspend, we did 1271 * not restore the controller state to whatever it had been at boot 1272 * time, so we do not need to do anything. 1273 */ 1274 if (!pm_suspend_via_firmware()) 1275 return 0; 1276 1277 /* 1278 * We only need to reset the controller if we are resuming after handing 1279 * off control to the platform firmware, otherwise we can simply restore 1280 * the mode. 1281 */ 1282 want_reset = pm_resume_via_firmware(); 1283 1284 return i8042_controller_resume(want_reset); 1285} 1286 1287static int i8042_pm_thaw(struct device *dev) 1288{ 1289 i8042_interrupt(0, NULL); 1290 1291 return 0; 1292} 1293 1294static int i8042_pm_reset(struct device *dev) 1295{ 1296 i8042_controller_reset(false); 1297 1298 return 0; 1299} 1300 1301static int i8042_pm_restore(struct device *dev) 1302{ 1303 return i8042_controller_resume(false); 1304} 1305 1306static const struct dev_pm_ops i8042_pm_ops = { 1307 .suspend = i8042_pm_suspend, 1308 .resume_noirq = i8042_pm_resume_noirq, 1309 .resume = i8042_pm_resume, 1310 .thaw = i8042_pm_thaw, 1311 .poweroff = i8042_pm_reset, 1312 .restore = i8042_pm_restore, 1313}; 1314 1315#endif /* CONFIG_PM */ 1316 1317/* 1318 * We need to reset the 8042 back to original mode on system shutdown, 1319 * because otherwise BIOSes will be confused. 1320 */ 1321 1322static void i8042_shutdown(struct platform_device *dev) 1323{ 1324 i8042_controller_reset(false); 1325} 1326 1327static int i8042_create_kbd_port(void) 1328{ 1329 struct serio *serio; 1330 struct i8042_port *port = &i8042_ports[I8042_KBD_PORT_NO]; 1331 1332 serio = kzalloc(sizeof(struct serio), GFP_KERNEL); 1333 if (!serio) 1334 return -ENOMEM; 1335 1336 serio->id.type = i8042_direct ? SERIO_8042 : SERIO_8042_XL; 1337 serio->write = i8042_dumbkbd ? NULL : i8042_kbd_write; 1338 serio->start = i8042_start; 1339 serio->stop = i8042_stop; 1340 serio->close = i8042_port_close; 1341 serio->ps2_cmd_mutex = &i8042_mutex; 1342 serio->port_data = port; 1343 serio->dev.parent = &i8042_platform_device->dev; 1344 strscpy(serio->name, "i8042 KBD port", sizeof(serio->name)); 1345 strscpy(serio->phys, I8042_KBD_PHYS_DESC, sizeof(serio->phys)); 1346 strscpy(serio->firmware_id, i8042_kbd_firmware_id, 1347 sizeof(serio->firmware_id)); 1348 set_primary_fwnode(&serio->dev, i8042_kbd_fwnode); 1349 1350 port->serio = serio; 1351 port->irq = I8042_KBD_IRQ; 1352 1353 return 0; 1354} 1355 1356static int i8042_create_aux_port(int idx) 1357{ 1358 struct serio *serio; 1359 int port_no = idx < 0 ? I8042_AUX_PORT_NO : I8042_MUX_PORT_NO + idx; 1360 struct i8042_port *port = &i8042_ports[port_no]; 1361 1362 serio = kzalloc(sizeof(struct serio), GFP_KERNEL); 1363 if (!serio) 1364 return -ENOMEM; 1365 1366 serio->id.type = SERIO_8042; 1367 serio->write = i8042_aux_write; 1368 serio->start = i8042_start; 1369 serio->stop = i8042_stop; 1370 serio->ps2_cmd_mutex = &i8042_mutex; 1371 serio->port_data = port; 1372 serio->dev.parent = &i8042_platform_device->dev; 1373 if (idx < 0) { 1374 strscpy(serio->name, "i8042 AUX port", sizeof(serio->name)); 1375 strscpy(serio->phys, I8042_AUX_PHYS_DESC, sizeof(serio->phys)); 1376 strscpy(serio->firmware_id, i8042_aux_firmware_id, 1377 sizeof(serio->firmware_id)); 1378 serio->close = i8042_port_close; 1379 } else { 1380 snprintf(serio->name, sizeof(serio->name), "i8042 AUX%d port", idx); 1381 snprintf(serio->phys, sizeof(serio->phys), I8042_MUX_PHYS_DESC, idx + 1); 1382 strscpy(serio->firmware_id, i8042_aux_firmware_id, 1383 sizeof(serio->firmware_id)); 1384 } 1385 1386 port->serio = serio; 1387 port->mux = idx; 1388 port->irq = I8042_AUX_IRQ; 1389 1390 return 0; 1391} 1392 1393static void i8042_free_kbd_port(void) 1394{ 1395 kfree(i8042_ports[I8042_KBD_PORT_NO].serio); 1396 i8042_ports[I8042_KBD_PORT_NO].serio = NULL; 1397} 1398 1399static void i8042_free_aux_ports(void) 1400{ 1401 int i; 1402 1403 for (i = I8042_AUX_PORT_NO; i < I8042_NUM_PORTS; i++) { 1404 kfree(i8042_ports[i].serio); 1405 i8042_ports[i].serio = NULL; 1406 } 1407} 1408 1409static void i8042_register_ports(void) 1410{ 1411 int i; 1412 1413 for (i = 0; i < I8042_NUM_PORTS; i++) { 1414 struct serio *serio = i8042_ports[i].serio; 1415 1416 if (!serio) 1417 continue; 1418 1419 printk(KERN_INFO "serio: %s at %#lx,%#lx irq %d\n", 1420 serio->name, 1421 (unsigned long) I8042_DATA_REG, 1422 (unsigned long) I8042_COMMAND_REG, 1423 i8042_ports[i].irq); 1424 serio_register_port(serio); 1425 } 1426} 1427 1428static void i8042_unregister_ports(void) 1429{ 1430 int i; 1431 1432 for (i = 0; i < I8042_NUM_PORTS; i++) { 1433 if (i8042_ports[i].serio) { 1434 serio_unregister_port(i8042_ports[i].serio); 1435 i8042_ports[i].serio = NULL; 1436 } 1437 } 1438} 1439 1440static void i8042_free_irqs(void) 1441{ 1442 if (i8042_aux_irq_registered) 1443 free_irq(I8042_AUX_IRQ, i8042_platform_device); 1444 if (i8042_kbd_irq_registered) 1445 free_irq(I8042_KBD_IRQ, i8042_platform_device); 1446 1447 i8042_aux_irq_registered = i8042_kbd_irq_registered = false; 1448} 1449 1450static int i8042_setup_aux(void) 1451{ 1452 int (*aux_enable)(void); 1453 int error; 1454 int i; 1455 1456 if (i8042_check_aux()) 1457 return -ENODEV; 1458 1459 if (i8042_nomux || i8042_check_mux()) { 1460 error = i8042_create_aux_port(-1); 1461 if (error) 1462 goto err_free_ports; 1463 aux_enable = i8042_enable_aux_port; 1464 } else { 1465 for (i = 0; i < I8042_NUM_MUX_PORTS; i++) { 1466 error = i8042_create_aux_port(i); 1467 if (error) 1468 goto err_free_ports; 1469 } 1470 aux_enable = i8042_enable_mux_ports; 1471 } 1472 1473 error = request_irq(I8042_AUX_IRQ, i8042_interrupt, IRQF_SHARED, 1474 "i8042", i8042_platform_device); 1475 if (error) 1476 goto err_free_ports; 1477 1478 error = aux_enable(); 1479 if (error) 1480 goto err_free_irq; 1481 1482 i8042_aux_irq_registered = true; 1483 return 0; 1484 1485 err_free_irq: 1486 free_irq(I8042_AUX_IRQ, i8042_platform_device); 1487 err_free_ports: 1488 i8042_free_aux_ports(); 1489 return error; 1490} 1491 1492static int i8042_setup_kbd(void) 1493{ 1494 int error; 1495 1496 error = i8042_create_kbd_port(); 1497 if (error) 1498 return error; 1499 1500 error = request_irq(I8042_KBD_IRQ, i8042_interrupt, IRQF_SHARED, 1501 "i8042", i8042_platform_device); 1502 if (error) 1503 goto err_free_port; 1504 1505 error = i8042_enable_kbd_port(); 1506 if (error) 1507 goto err_free_irq; 1508 1509 i8042_kbd_irq_registered = true; 1510 return 0; 1511 1512 err_free_irq: 1513 free_irq(I8042_KBD_IRQ, i8042_platform_device); 1514 err_free_port: 1515 i8042_free_kbd_port(); 1516 return error; 1517} 1518 1519static int i8042_kbd_bind_notifier(struct notifier_block *nb, 1520 unsigned long action, void *data) 1521{ 1522 struct device *dev = data; 1523 struct serio *serio = to_serio_port(dev); 1524 struct i8042_port *port = serio->port_data; 1525 1526 if (serio != i8042_ports[I8042_KBD_PORT_NO].serio) 1527 return 0; 1528 1529 switch (action) { 1530 case BUS_NOTIFY_BOUND_DRIVER: 1531 port->driver_bound = true; 1532 break; 1533 1534 case BUS_NOTIFY_UNBIND_DRIVER: 1535 port->driver_bound = false; 1536 break; 1537 } 1538 1539 return 0; 1540} 1541 1542static int i8042_probe(struct platform_device *dev) 1543{ 1544 int error; 1545 1546 if (i8042_reset == I8042_RESET_ALWAYS) { 1547 error = i8042_controller_selftest(); 1548 if (error) 1549 return error; 1550 } 1551 1552 error = i8042_controller_init(); 1553 if (error) 1554 return error; 1555 1556#ifdef CONFIG_X86 1557 if (i8042_dritek) 1558 i8042_dritek_enable(); 1559#endif 1560 1561 if (!i8042_noaux) { 1562 error = i8042_setup_aux(); 1563 if (error && error != -ENODEV && error != -EBUSY) 1564 goto out_fail; 1565 } 1566 1567 if (!i8042_nokbd) { 1568 error = i8042_setup_kbd(); 1569 if (error) 1570 goto out_fail; 1571 } 1572/* 1573 * Ok, everything is ready, let's register all serio ports 1574 */ 1575 i8042_register_ports(); 1576 1577 return 0; 1578 1579 out_fail: 1580 i8042_free_aux_ports(); /* in case KBD failed but AUX not */ 1581 i8042_free_irqs(); 1582 i8042_controller_reset(false); 1583 1584 return error; 1585} 1586 1587static void i8042_remove(struct platform_device *dev) 1588{ 1589 i8042_unregister_ports(); 1590 i8042_free_irqs(); 1591 i8042_controller_reset(false); 1592} 1593 1594static struct platform_driver i8042_driver = { 1595 .driver = { 1596 .name = "i8042", 1597#ifdef CONFIG_PM 1598 .pm = &i8042_pm_ops, 1599#endif 1600 }, 1601 .probe = i8042_probe, 1602 .remove_new = i8042_remove, 1603 .shutdown = i8042_shutdown, 1604}; 1605 1606static struct notifier_block i8042_kbd_bind_notifier_block = { 1607 .notifier_call = i8042_kbd_bind_notifier, 1608}; 1609 1610static int __init i8042_init(void) 1611{ 1612 int err; 1613 1614 dbg_init(); 1615 1616 err = i8042_platform_init(); 1617 if (err) 1618 return (err == -ENODEV) ? 0 : err; 1619 1620 err = i8042_controller_check(); 1621 if (err) 1622 goto err_platform_exit; 1623 1624 /* Set this before creating the dev to allow i8042_command to work right away */ 1625 i8042_present = true; 1626 1627 err = platform_driver_register(&i8042_driver); 1628 if (err) 1629 goto err_platform_exit; 1630 1631 i8042_platform_device = platform_device_alloc("i8042", -1); 1632 if (!i8042_platform_device) { 1633 err = -ENOMEM; 1634 goto err_unregister_driver; 1635 } 1636 1637 err = platform_device_add(i8042_platform_device); 1638 if (err) 1639 goto err_free_device; 1640 1641 bus_register_notifier(&serio_bus, &i8042_kbd_bind_notifier_block); 1642 panic_blink = i8042_panic_blink; 1643 1644 return 0; 1645 1646err_free_device: 1647 platform_device_put(i8042_platform_device); 1648err_unregister_driver: 1649 platform_driver_unregister(&i8042_driver); 1650 err_platform_exit: 1651 i8042_platform_exit(); 1652 return err; 1653} 1654 1655static void __exit i8042_exit(void) 1656{ 1657 if (!i8042_present) 1658 return; 1659 1660 platform_device_unregister(i8042_platform_device); 1661 platform_driver_unregister(&i8042_driver); 1662 i8042_platform_exit(); 1663 1664 bus_unregister_notifier(&serio_bus, &i8042_kbd_bind_notifier_block); 1665 panic_blink = NULL; 1666} 1667 1668module_init(i8042_init); 1669module_exit(i8042_exit); 1670