1// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB 2/* 3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved. 4 * Copyright (c) 2020, Intel Corporation. All rights reserved. 5 */ 6 7#include <linux/debugfs.h> 8#include <linux/highmem.h> 9#include <linux/module.h> 10#include <linux/init.h> 11#include <linux/errno.h> 12#include <linux/pci.h> 13#include <linux/dma-mapping.h> 14#include <linux/slab.h> 15#include <linux/bitmap.h> 16#include <linux/sched.h> 17#include <linux/sched/mm.h> 18#include <linux/sched/task.h> 19#include <linux/delay.h> 20#include <rdma/ib_user_verbs.h> 21#include <rdma/ib_addr.h> 22#include <rdma/ib_cache.h> 23#include <linux/mlx5/port.h> 24#include <linux/mlx5/vport.h> 25#include <linux/mlx5/fs.h> 26#include <linux/mlx5/eswitch.h> 27#include <linux/mlx5/driver.h> 28#include <linux/list.h> 29#include <rdma/ib_smi.h> 30#include <rdma/ib_umem_odp.h> 31#include <rdma/lag.h> 32#include <linux/in.h> 33#include <linux/etherdevice.h> 34#include "mlx5_ib.h" 35#include "ib_rep.h" 36#include "cmd.h" 37#include "devx.h" 38#include "dm.h" 39#include "fs.h" 40#include "srq.h" 41#include "qp.h" 42#include "wr.h" 43#include "restrack.h" 44#include "counters.h" 45#include "umr.h" 46#include <rdma/uverbs_std_types.h> 47#include <rdma/uverbs_ioctl.h> 48#include <rdma/mlx5_user_ioctl_verbs.h> 49#include <rdma/mlx5_user_ioctl_cmds.h> 50#include "macsec.h" 51 52#define UVERBS_MODULE_NAME mlx5_ib 53#include <rdma/uverbs_named_ioctl.h> 54 55MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>"); 56MODULE_DESCRIPTION("Mellanox 5th generation network adapters (ConnectX series) IB driver"); 57MODULE_LICENSE("Dual BSD/GPL"); 58 59struct mlx5_ib_event_work { 60 struct work_struct work; 61 union { 62 struct mlx5_ib_dev *dev; 63 struct mlx5_ib_multiport_info *mpi; 64 }; 65 bool is_slave; 66 unsigned int event; 67 void *param; 68}; 69 70enum { 71 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 72}; 73 74static struct workqueue_struct *mlx5_ib_event_wq; 75static LIST_HEAD(mlx5_ib_unaffiliated_port_list); 76static LIST_HEAD(mlx5_ib_dev_list); 77/* 78 * This mutex should be held when accessing either of the above lists 79 */ 80static DEFINE_MUTEX(mlx5_ib_multiport_mutex); 81 82struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi) 83{ 84 struct mlx5_ib_dev *dev; 85 86 mutex_lock(&mlx5_ib_multiport_mutex); 87 dev = mpi->ibdev; 88 mutex_unlock(&mlx5_ib_multiport_mutex); 89 return dev; 90} 91 92static enum rdma_link_layer 93mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 94{ 95 switch (port_type_cap) { 96 case MLX5_CAP_PORT_TYPE_IB: 97 return IB_LINK_LAYER_INFINIBAND; 98 case MLX5_CAP_PORT_TYPE_ETH: 99 return IB_LINK_LAYER_ETHERNET; 100 default: 101 return IB_LINK_LAYER_UNSPECIFIED; 102 } 103} 104 105static enum rdma_link_layer 106mlx5_ib_port_link_layer(struct ib_device *device, u32 port_num) 107{ 108 struct mlx5_ib_dev *dev = to_mdev(device); 109 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 110 111 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 112} 113 114static int get_port_state(struct ib_device *ibdev, 115 u32 port_num, 116 enum ib_port_state *state) 117{ 118 struct ib_port_attr attr; 119 int ret; 120 121 memset(&attr, 0, sizeof(attr)); 122 ret = ibdev->ops.query_port(ibdev, port_num, &attr); 123 if (!ret) 124 *state = attr.state; 125 return ret; 126} 127 128static struct mlx5_roce *mlx5_get_rep_roce(struct mlx5_ib_dev *dev, 129 struct net_device *ndev, 130 struct net_device *upper, 131 u32 *port_num) 132{ 133 struct net_device *rep_ndev; 134 struct mlx5_ib_port *port; 135 int i; 136 137 for (i = 0; i < dev->num_ports; i++) { 138 port = &dev->port[i]; 139 if (!port->rep) 140 continue; 141 142 if (upper == ndev && port->rep->vport == MLX5_VPORT_UPLINK) { 143 *port_num = i + 1; 144 return &port->roce; 145 } 146 147 if (upper && port->rep->vport == MLX5_VPORT_UPLINK) 148 continue; 149 150 read_lock(&port->roce.netdev_lock); 151 rep_ndev = mlx5_ib_get_rep_netdev(port->rep->esw, 152 port->rep->vport); 153 if (rep_ndev == ndev) { 154 read_unlock(&port->roce.netdev_lock); 155 *port_num = i + 1; 156 return &port->roce; 157 } 158 read_unlock(&port->roce.netdev_lock); 159 } 160 161 return NULL; 162} 163 164static int mlx5_netdev_event(struct notifier_block *this, 165 unsigned long event, void *ptr) 166{ 167 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb); 168 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 169 u32 port_num = roce->native_port_num; 170 struct mlx5_core_dev *mdev; 171 struct mlx5_ib_dev *ibdev; 172 173 ibdev = roce->dev; 174 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 175 if (!mdev) 176 return NOTIFY_DONE; 177 178 switch (event) { 179 case NETDEV_REGISTER: 180 /* Should already be registered during the load */ 181 if (ibdev->is_rep) 182 break; 183 write_lock(&roce->netdev_lock); 184 if (ndev->dev.parent == mdev->device) 185 roce->netdev = ndev; 186 write_unlock(&roce->netdev_lock); 187 break; 188 189 case NETDEV_UNREGISTER: 190 /* In case of reps, ib device goes away before the netdevs */ 191 write_lock(&roce->netdev_lock); 192 if (roce->netdev == ndev) 193 roce->netdev = NULL; 194 write_unlock(&roce->netdev_lock); 195 break; 196 197 case NETDEV_CHANGE: 198 case NETDEV_UP: 199 case NETDEV_DOWN: { 200 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev); 201 struct net_device *upper = NULL; 202 203 if (lag_ndev) { 204 upper = netdev_master_upper_dev_get(lag_ndev); 205 dev_put(lag_ndev); 206 } 207 208 if (ibdev->is_rep) 209 roce = mlx5_get_rep_roce(ibdev, ndev, upper, &port_num); 210 if (!roce) 211 return NOTIFY_DONE; 212 if ((upper == ndev || 213 ((!upper || ibdev->is_rep) && ndev == roce->netdev)) && 214 ibdev->ib_active) { 215 struct ib_event ibev = { }; 216 enum ib_port_state port_state; 217 218 if (get_port_state(&ibdev->ib_dev, port_num, 219 &port_state)) 220 goto done; 221 222 if (roce->last_port_state == port_state) 223 goto done; 224 225 roce->last_port_state = port_state; 226 ibev.device = &ibdev->ib_dev; 227 if (port_state == IB_PORT_DOWN) 228 ibev.event = IB_EVENT_PORT_ERR; 229 else if (port_state == IB_PORT_ACTIVE) 230 ibev.event = IB_EVENT_PORT_ACTIVE; 231 else 232 goto done; 233 234 ibev.element.port_num = port_num; 235 ib_dispatch_event(&ibev); 236 } 237 break; 238 } 239 240 default: 241 break; 242 } 243done: 244 mlx5_ib_put_native_port_mdev(ibdev, port_num); 245 return NOTIFY_DONE; 246} 247 248static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 249 u32 port_num) 250{ 251 struct mlx5_ib_dev *ibdev = to_mdev(device); 252 struct net_device *ndev; 253 struct mlx5_core_dev *mdev; 254 255 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL); 256 if (!mdev) 257 return NULL; 258 259 ndev = mlx5_lag_get_roce_netdev(mdev); 260 if (ndev) 261 goto out; 262 263 /* Ensure ndev does not disappear before we invoke dev_hold() 264 */ 265 read_lock(&ibdev->port[port_num - 1].roce.netdev_lock); 266 ndev = ibdev->port[port_num - 1].roce.netdev; 267 dev_hold(ndev); 268 read_unlock(&ibdev->port[port_num - 1].roce.netdev_lock); 269 270out: 271 mlx5_ib_put_native_port_mdev(ibdev, port_num); 272 return ndev; 273} 274 275struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev, 276 u32 ib_port_num, 277 u32 *native_port_num) 278{ 279 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 280 ib_port_num); 281 struct mlx5_core_dev *mdev = NULL; 282 struct mlx5_ib_multiport_info *mpi; 283 struct mlx5_ib_port *port; 284 285 if (!mlx5_core_mp_enabled(ibdev->mdev) || 286 ll != IB_LINK_LAYER_ETHERNET) { 287 if (native_port_num) 288 *native_port_num = ib_port_num; 289 return ibdev->mdev; 290 } 291 292 if (native_port_num) 293 *native_port_num = 1; 294 295 port = &ibdev->port[ib_port_num - 1]; 296 spin_lock(&port->mp.mpi_lock); 297 mpi = ibdev->port[ib_port_num - 1].mp.mpi; 298 if (mpi && !mpi->unaffiliate) { 299 mdev = mpi->mdev; 300 /* If it's the master no need to refcount, it'll exist 301 * as long as the ib_dev exists. 302 */ 303 if (!mpi->is_master) 304 mpi->mdev_refcnt++; 305 } 306 spin_unlock(&port->mp.mpi_lock); 307 308 return mdev; 309} 310 311void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u32 port_num) 312{ 313 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev, 314 port_num); 315 struct mlx5_ib_multiport_info *mpi; 316 struct mlx5_ib_port *port; 317 318 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 319 return; 320 321 port = &ibdev->port[port_num - 1]; 322 323 spin_lock(&port->mp.mpi_lock); 324 mpi = ibdev->port[port_num - 1].mp.mpi; 325 if (mpi->is_master) 326 goto out; 327 328 mpi->mdev_refcnt--; 329 if (mpi->unaffiliate) 330 complete(&mpi->unref_comp); 331out: 332 spin_unlock(&port->mp.mpi_lock); 333} 334 335static int translate_eth_legacy_proto_oper(u32 eth_proto_oper, 336 u16 *active_speed, u8 *active_width) 337{ 338 switch (eth_proto_oper) { 339 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 340 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 341 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 342 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 343 *active_width = IB_WIDTH_1X; 344 *active_speed = IB_SPEED_SDR; 345 break; 346 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 347 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 348 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 349 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 350 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 351 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 352 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER): 353 *active_width = IB_WIDTH_1X; 354 *active_speed = IB_SPEED_QDR; 355 break; 356 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 357 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 358 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 359 *active_width = IB_WIDTH_1X; 360 *active_speed = IB_SPEED_EDR; 361 break; 362 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 363 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 364 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 365 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4): 366 *active_width = IB_WIDTH_4X; 367 *active_speed = IB_SPEED_QDR; 368 break; 369 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 370 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 371 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 372 *active_width = IB_WIDTH_1X; 373 *active_speed = IB_SPEED_HDR; 374 break; 375 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 376 *active_width = IB_WIDTH_4X; 377 *active_speed = IB_SPEED_FDR; 378 break; 379 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 380 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 381 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 382 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 383 *active_width = IB_WIDTH_4X; 384 *active_speed = IB_SPEED_EDR; 385 break; 386 default: 387 return -EINVAL; 388 } 389 390 return 0; 391} 392 393static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u16 *active_speed, 394 u8 *active_width) 395{ 396 switch (eth_proto_oper) { 397 case MLX5E_PROT_MASK(MLX5E_SGMII_100M): 398 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII): 399 *active_width = IB_WIDTH_1X; 400 *active_speed = IB_SPEED_SDR; 401 break; 402 case MLX5E_PROT_MASK(MLX5E_5GBASE_R): 403 *active_width = IB_WIDTH_1X; 404 *active_speed = IB_SPEED_DDR; 405 break; 406 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1): 407 *active_width = IB_WIDTH_1X; 408 *active_speed = IB_SPEED_QDR; 409 break; 410 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4): 411 *active_width = IB_WIDTH_4X; 412 *active_speed = IB_SPEED_QDR; 413 break; 414 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR): 415 *active_width = IB_WIDTH_1X; 416 *active_speed = IB_SPEED_EDR; 417 break; 418 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2): 419 *active_width = IB_WIDTH_2X; 420 *active_speed = IB_SPEED_EDR; 421 break; 422 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR): 423 *active_width = IB_WIDTH_1X; 424 *active_speed = IB_SPEED_HDR; 425 break; 426 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4): 427 *active_width = IB_WIDTH_4X; 428 *active_speed = IB_SPEED_EDR; 429 break; 430 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2): 431 *active_width = IB_WIDTH_2X; 432 *active_speed = IB_SPEED_HDR; 433 break; 434 case MLX5E_PROT_MASK(MLX5E_100GAUI_1_100GBASE_CR_KR): 435 *active_width = IB_WIDTH_1X; 436 *active_speed = IB_SPEED_NDR; 437 break; 438 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4): 439 *active_width = IB_WIDTH_4X; 440 *active_speed = IB_SPEED_HDR; 441 break; 442 case MLX5E_PROT_MASK(MLX5E_200GAUI_2_200GBASE_CR2_KR2): 443 *active_width = IB_WIDTH_2X; 444 *active_speed = IB_SPEED_NDR; 445 break; 446 case MLX5E_PROT_MASK(MLX5E_400GAUI_8_400GBASE_CR8): 447 *active_width = IB_WIDTH_8X; 448 *active_speed = IB_SPEED_HDR; 449 break; 450 case MLX5E_PROT_MASK(MLX5E_400GAUI_4_400GBASE_CR4_KR4): 451 *active_width = IB_WIDTH_4X; 452 *active_speed = IB_SPEED_NDR; 453 break; 454 case MLX5E_PROT_MASK(MLX5E_800GAUI_8_800GBASE_CR8_KR8): 455 *active_width = IB_WIDTH_8X; 456 *active_speed = IB_SPEED_NDR; 457 break; 458 default: 459 return -EINVAL; 460 } 461 462 return 0; 463} 464 465static int translate_eth_proto_oper(u32 eth_proto_oper, u16 *active_speed, 466 u8 *active_width, bool ext) 467{ 468 return ext ? 469 translate_eth_ext_proto_oper(eth_proto_oper, active_speed, 470 active_width) : 471 translate_eth_legacy_proto_oper(eth_proto_oper, active_speed, 472 active_width); 473} 474 475static int mlx5_query_port_roce(struct ib_device *device, u32 port_num, 476 struct ib_port_attr *props) 477{ 478 struct mlx5_ib_dev *dev = to_mdev(device); 479 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0}; 480 struct mlx5_core_dev *mdev; 481 struct net_device *ndev, *upper; 482 enum ib_mtu ndev_ib_mtu; 483 bool put_mdev = true; 484 u32 eth_prot_oper; 485 u32 mdev_port_num; 486 bool ext; 487 int err; 488 489 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 490 if (!mdev) { 491 /* This means the port isn't affiliated yet. Get the 492 * info for the master port instead. 493 */ 494 put_mdev = false; 495 mdev = dev->mdev; 496 mdev_port_num = 1; 497 port_num = 1; 498 } 499 500 /* Possible bad flows are checked before filling out props so in case 501 * of an error it will still be zeroed out. 502 * Use native port in case of reps 503 */ 504 if (dev->is_rep) 505 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 506 1); 507 else 508 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 509 mdev_port_num); 510 if (err) 511 goto out; 512 ext = !!MLX5_GET_ETH_PROTO(ptys_reg, out, true, eth_proto_capability); 513 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper); 514 515 props->active_width = IB_WIDTH_4X; 516 props->active_speed = IB_SPEED_QDR; 517 518 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 519 &props->active_width, ext); 520 521 if (!dev->is_rep && dev->mdev->roce.roce_en) { 522 u16 qkey_viol_cntr; 523 524 props->port_cap_flags |= IB_PORT_CM_SUP; 525 props->ip_gids = true; 526 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 527 roce_address_table_size); 528 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr); 529 props->qkey_viol_cntr = qkey_viol_cntr; 530 } 531 props->max_mtu = IB_MTU_4096; 532 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 533 props->pkey_tbl_len = 1; 534 props->state = IB_PORT_DOWN; 535 props->phys_state = IB_PORT_PHYS_STATE_DISABLED; 536 537 /* If this is a stub query for an unaffiliated port stop here */ 538 if (!put_mdev) 539 goto out; 540 541 ndev = mlx5_ib_get_netdev(device, port_num); 542 if (!ndev) 543 goto out; 544 545 if (dev->lag_active) { 546 rcu_read_lock(); 547 upper = netdev_master_upper_dev_get_rcu(ndev); 548 if (upper) { 549 dev_put(ndev); 550 ndev = upper; 551 dev_hold(ndev); 552 } 553 rcu_read_unlock(); 554 } 555 556 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 557 props->state = IB_PORT_ACTIVE; 558 props->phys_state = IB_PORT_PHYS_STATE_LINK_UP; 559 } 560 561 ndev_ib_mtu = iboe_get_mtu(ndev->mtu); 562 563 dev_put(ndev); 564 565 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 566out: 567 if (put_mdev) 568 mlx5_ib_put_native_port_mdev(dev, port_num); 569 return err; 570} 571 572int set_roce_addr(struct mlx5_ib_dev *dev, u32 port_num, 573 unsigned int index, const union ib_gid *gid, 574 const struct ib_gid_attr *attr) 575{ 576 enum ib_gid_type gid_type; 577 u16 vlan_id = 0xffff; 578 u8 roce_version = 0; 579 u8 roce_l3_type = 0; 580 u8 mac[ETH_ALEN]; 581 int ret; 582 583 gid_type = attr->gid_type; 584 if (gid) { 585 ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]); 586 if (ret) 587 return ret; 588 } 589 590 switch (gid_type) { 591 case IB_GID_TYPE_ROCE: 592 roce_version = MLX5_ROCE_VERSION_1; 593 break; 594 case IB_GID_TYPE_ROCE_UDP_ENCAP: 595 roce_version = MLX5_ROCE_VERSION_2; 596 if (gid && ipv6_addr_v4mapped((void *)gid)) 597 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4; 598 else 599 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6; 600 break; 601 602 default: 603 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type); 604 } 605 606 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version, 607 roce_l3_type, gid->raw, mac, 608 vlan_id < VLAN_CFI_MASK, vlan_id, 609 port_num); 610} 611 612static int mlx5_ib_add_gid(const struct ib_gid_attr *attr, 613 __always_unused void **context) 614{ 615 int ret; 616 617 ret = mlx5r_add_gid_macsec_operations(attr); 618 if (ret) 619 return ret; 620 621 return set_roce_addr(to_mdev(attr->device), attr->port_num, 622 attr->index, &attr->gid, attr); 623} 624 625static int mlx5_ib_del_gid(const struct ib_gid_attr *attr, 626 __always_unused void **context) 627{ 628 int ret; 629 630 ret = set_roce_addr(to_mdev(attr->device), attr->port_num, 631 attr->index, NULL, attr); 632 if (ret) 633 return ret; 634 635 mlx5r_del_gid_macsec_operations(attr); 636 return 0; 637} 638 639__be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev, 640 const struct ib_gid_attr *attr) 641{ 642 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 643 return 0; 644 645 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 646} 647 648static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 649{ 650 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 651 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 652 return 0; 653} 654 655enum { 656 MLX5_VPORT_ACCESS_METHOD_MAD, 657 MLX5_VPORT_ACCESS_METHOD_HCA, 658 MLX5_VPORT_ACCESS_METHOD_NIC, 659}; 660 661static int mlx5_get_vport_access_method(struct ib_device *ibdev) 662{ 663 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 664 return MLX5_VPORT_ACCESS_METHOD_MAD; 665 666 if (mlx5_ib_port_link_layer(ibdev, 1) == 667 IB_LINK_LAYER_ETHERNET) 668 return MLX5_VPORT_ACCESS_METHOD_NIC; 669 670 return MLX5_VPORT_ACCESS_METHOD_HCA; 671} 672 673static void get_atomic_caps(struct mlx5_ib_dev *dev, 674 u8 atomic_size_qp, 675 struct ib_device_attr *props) 676{ 677 u8 tmp; 678 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 679 u8 atomic_req_8B_endianness_mode = 680 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode); 681 682 /* Check if HW supports 8 bytes standard atomic operations and capable 683 * of host endianness respond 684 */ 685 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 686 if (((atomic_operations & tmp) == tmp) && 687 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 688 (atomic_req_8B_endianness_mode)) { 689 props->atomic_cap = IB_ATOMIC_HCA; 690 } else { 691 props->atomic_cap = IB_ATOMIC_NONE; 692 } 693} 694 695static void get_atomic_caps_qp(struct mlx5_ib_dev *dev, 696 struct ib_device_attr *props) 697{ 698 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 699 700 get_atomic_caps(dev, atomic_size_qp, props); 701} 702 703static int mlx5_query_system_image_guid(struct ib_device *ibdev, 704 __be64 *sys_image_guid) 705{ 706 struct mlx5_ib_dev *dev = to_mdev(ibdev); 707 struct mlx5_core_dev *mdev = dev->mdev; 708 u64 tmp; 709 int err; 710 711 switch (mlx5_get_vport_access_method(ibdev)) { 712 case MLX5_VPORT_ACCESS_METHOD_MAD: 713 return mlx5_query_mad_ifc_system_image_guid(ibdev, 714 sys_image_guid); 715 716 case MLX5_VPORT_ACCESS_METHOD_HCA: 717 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 718 break; 719 720 case MLX5_VPORT_ACCESS_METHOD_NIC: 721 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 722 break; 723 724 default: 725 return -EINVAL; 726 } 727 728 if (!err) 729 *sys_image_guid = cpu_to_be64(tmp); 730 731 return err; 732 733} 734 735static int mlx5_query_max_pkeys(struct ib_device *ibdev, 736 u16 *max_pkeys) 737{ 738 struct mlx5_ib_dev *dev = to_mdev(ibdev); 739 struct mlx5_core_dev *mdev = dev->mdev; 740 741 switch (mlx5_get_vport_access_method(ibdev)) { 742 case MLX5_VPORT_ACCESS_METHOD_MAD: 743 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 744 745 case MLX5_VPORT_ACCESS_METHOD_HCA: 746 case MLX5_VPORT_ACCESS_METHOD_NIC: 747 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 748 pkey_table_size)); 749 return 0; 750 751 default: 752 return -EINVAL; 753 } 754} 755 756static int mlx5_query_vendor_id(struct ib_device *ibdev, 757 u32 *vendor_id) 758{ 759 struct mlx5_ib_dev *dev = to_mdev(ibdev); 760 761 switch (mlx5_get_vport_access_method(ibdev)) { 762 case MLX5_VPORT_ACCESS_METHOD_MAD: 763 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 764 765 case MLX5_VPORT_ACCESS_METHOD_HCA: 766 case MLX5_VPORT_ACCESS_METHOD_NIC: 767 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 768 769 default: 770 return -EINVAL; 771 } 772} 773 774static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 775 __be64 *node_guid) 776{ 777 u64 tmp; 778 int err; 779 780 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 781 case MLX5_VPORT_ACCESS_METHOD_MAD: 782 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 783 784 case MLX5_VPORT_ACCESS_METHOD_HCA: 785 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 786 break; 787 788 case MLX5_VPORT_ACCESS_METHOD_NIC: 789 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 790 break; 791 792 default: 793 return -EINVAL; 794 } 795 796 if (!err) 797 *node_guid = cpu_to_be64(tmp); 798 799 return err; 800} 801 802struct mlx5_reg_node_desc { 803 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 804}; 805 806static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 807{ 808 struct mlx5_reg_node_desc in; 809 810 if (mlx5_use_mad_ifc(dev)) 811 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 812 813 memset(&in, 0, sizeof(in)); 814 815 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 816 sizeof(struct mlx5_reg_node_desc), 817 MLX5_REG_NODE_DESC, 0, 0); 818} 819 820static void fill_esw_mgr_reg_c0(struct mlx5_core_dev *mdev, 821 struct mlx5_ib_query_device_resp *resp) 822{ 823 struct mlx5_eswitch *esw = mdev->priv.eswitch; 824 u16 vport = mlx5_eswitch_manager_vport(mdev); 825 826 resp->reg_c0.value = mlx5_eswitch_get_vport_metadata_for_match(esw, 827 vport); 828 resp->reg_c0.mask = mlx5_eswitch_get_vport_metadata_mask(); 829} 830 831static int mlx5_ib_query_device(struct ib_device *ibdev, 832 struct ib_device_attr *props, 833 struct ib_udata *uhw) 834{ 835 size_t uhw_outlen = (uhw) ? uhw->outlen : 0; 836 struct mlx5_ib_dev *dev = to_mdev(ibdev); 837 struct mlx5_core_dev *mdev = dev->mdev; 838 int err = -ENOMEM; 839 int max_sq_desc; 840 int max_rq_sg; 841 int max_sq_sg; 842 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 843 bool raw_support = !mlx5_core_mp_enabled(mdev); 844 struct mlx5_ib_query_device_resp resp = {}; 845 size_t resp_len; 846 u64 max_tso; 847 848 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 849 if (uhw_outlen && uhw_outlen < resp_len) 850 return -EINVAL; 851 852 resp.response_length = resp_len; 853 854 if (uhw && uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 855 return -EINVAL; 856 857 memset(props, 0, sizeof(*props)); 858 err = mlx5_query_system_image_guid(ibdev, 859 &props->sys_image_guid); 860 if (err) 861 return err; 862 863 props->max_pkeys = dev->pkey_table_len; 864 865 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 866 if (err) 867 return err; 868 869 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 870 (fw_rev_min(dev->mdev) << 16) | 871 fw_rev_sub(dev->mdev); 872 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 873 IB_DEVICE_PORT_ACTIVE_EVENT | 874 IB_DEVICE_SYS_IMAGE_GUID | 875 IB_DEVICE_RC_RNR_NAK_GEN; 876 877 if (MLX5_CAP_GEN(mdev, pkv)) 878 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 879 if (MLX5_CAP_GEN(mdev, qkv)) 880 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 881 if (MLX5_CAP_GEN(mdev, apm)) 882 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 883 if (MLX5_CAP_GEN(mdev, xrc)) 884 props->device_cap_flags |= IB_DEVICE_XRC; 885 if (MLX5_CAP_GEN(mdev, imaicl)) { 886 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 887 IB_DEVICE_MEM_WINDOW_TYPE_2B; 888 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 889 /* We support 'Gappy' memory registration too */ 890 props->kernel_cap_flags |= IBK_SG_GAPS_REG; 891 } 892 /* IB_WR_REG_MR always requires changing the entity size with UMR */ 893 if (!MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) 894 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 895 if (MLX5_CAP_GEN(mdev, sho)) { 896 props->kernel_cap_flags |= IBK_INTEGRITY_HANDOVER; 897 /* At this stage no support for signature handover */ 898 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 899 IB_PROT_T10DIF_TYPE_2 | 900 IB_PROT_T10DIF_TYPE_3; 901 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 902 IB_GUARD_T10DIF_CSUM; 903 } 904 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 905 props->kernel_cap_flags |= IBK_BLOCK_MULTICAST_LOOPBACK; 906 907 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) { 908 if (MLX5_CAP_ETH(mdev, csum_cap)) { 909 /* Legacy bit to support old userspace libraries */ 910 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 911 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM; 912 } 913 914 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) 915 props->raw_packet_caps |= 916 IB_RAW_PACKET_CAP_CVLAN_STRIPPING; 917 918 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) { 919 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 920 if (max_tso) { 921 resp.tso_caps.max_tso = 1 << max_tso; 922 resp.tso_caps.supported_qpts |= 923 1 << IB_QPT_RAW_PACKET; 924 resp.response_length += sizeof(resp.tso_caps); 925 } 926 } 927 928 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) { 929 resp.rss_caps.rx_hash_function = 930 MLX5_RX_HASH_FUNC_TOEPLITZ; 931 resp.rss_caps.rx_hash_fields_mask = 932 MLX5_RX_HASH_SRC_IPV4 | 933 MLX5_RX_HASH_DST_IPV4 | 934 MLX5_RX_HASH_SRC_IPV6 | 935 MLX5_RX_HASH_DST_IPV6 | 936 MLX5_RX_HASH_SRC_PORT_TCP | 937 MLX5_RX_HASH_DST_PORT_TCP | 938 MLX5_RX_HASH_SRC_PORT_UDP | 939 MLX5_RX_HASH_DST_PORT_UDP | 940 MLX5_RX_HASH_INNER; 941 resp.response_length += sizeof(resp.rss_caps); 942 } 943 } else { 944 if (offsetofend(typeof(resp), tso_caps) <= uhw_outlen) 945 resp.response_length += sizeof(resp.tso_caps); 946 if (offsetofend(typeof(resp), rss_caps) <= uhw_outlen) 947 resp.response_length += sizeof(resp.rss_caps); 948 } 949 950 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) { 951 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 952 props->kernel_cap_flags |= IBK_UD_TSO; 953 } 954 955 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) && 956 MLX5_CAP_GEN(dev->mdev, general_notification_event) && 957 raw_support) 958 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP; 959 960 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 961 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap)) 962 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 963 964 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 965 MLX5_CAP_ETH(dev->mdev, scatter_fcs) && 966 raw_support) { 967 /* Legacy bit to support old userspace libraries */ 968 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 969 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS; 970 } 971 972 if (MLX5_CAP_DEV_MEM(mdev, memic)) { 973 props->max_dm_size = 974 MLX5_CAP_DEV_MEM(mdev, max_memic_size); 975 } 976 977 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 978 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 979 980 if (MLX5_CAP_GEN(mdev, end_pad)) 981 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING; 982 983 props->vendor_part_id = mdev->pdev->device; 984 props->hw_ver = mdev->pdev->revision; 985 986 props->max_mr_size = ~0ull; 987 props->page_size_cap = ~(min_page_size - 1); 988 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 989 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 990 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 991 sizeof(struct mlx5_wqe_data_seg); 992 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 993 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 994 sizeof(struct mlx5_wqe_raddr_seg)) / 995 sizeof(struct mlx5_wqe_data_seg); 996 props->max_send_sge = max_sq_sg; 997 props->max_recv_sge = max_rq_sg; 998 props->max_sge_rd = MLX5_MAX_SGE_RD; 999 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 1000 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 1001 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 1002 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 1003 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 1004 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 1005 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 1006 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 1007 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 1008 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 1009 props->max_srq_sge = max_rq_sg - 1; 1010 props->max_fast_reg_page_list_len = 1011 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 1012 props->max_pi_fast_reg_page_list_len = 1013 props->max_fast_reg_page_list_len / 2; 1014 props->max_sgl_rd = 1015 MLX5_CAP_GEN(mdev, max_sgl_for_optimized_performance); 1016 get_atomic_caps_qp(dev, props); 1017 props->masked_atomic_cap = IB_ATOMIC_NONE; 1018 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 1019 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 1020 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 1021 props->max_mcast_grp; 1022 props->max_ah = INT_MAX; 1023 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 1024 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 1025 1026 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) { 1027 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT) 1028 props->kernel_cap_flags |= IBK_ON_DEMAND_PAGING; 1029 props->odp_caps = dev->odp_caps; 1030 if (!uhw) { 1031 /* ODP for kernel QPs is not implemented for receive 1032 * WQEs and SRQ WQEs 1033 */ 1034 props->odp_caps.per_transport_caps.rc_odp_caps &= 1035 ~(IB_ODP_SUPPORT_READ | 1036 IB_ODP_SUPPORT_SRQ_RECV); 1037 props->odp_caps.per_transport_caps.uc_odp_caps &= 1038 ~(IB_ODP_SUPPORT_READ | 1039 IB_ODP_SUPPORT_SRQ_RECV); 1040 props->odp_caps.per_transport_caps.ud_odp_caps &= 1041 ~(IB_ODP_SUPPORT_READ | 1042 IB_ODP_SUPPORT_SRQ_RECV); 1043 props->odp_caps.per_transport_caps.xrc_odp_caps &= 1044 ~(IB_ODP_SUPPORT_READ | 1045 IB_ODP_SUPPORT_SRQ_RECV); 1046 } 1047 } 1048 1049 if (mlx5_core_is_vf(mdev)) 1050 props->kernel_cap_flags |= IBK_VIRTUAL_FUNCTION; 1051 1052 if (mlx5_ib_port_link_layer(ibdev, 1) == 1053 IB_LINK_LAYER_ETHERNET && raw_support) { 1054 props->rss_caps.max_rwq_indirection_tables = 1055 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 1056 props->rss_caps.max_rwq_indirection_table_size = 1057 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 1058 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 1059 props->max_wq_type_rq = 1060 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 1061 } 1062 1063 if (MLX5_CAP_GEN(mdev, tag_matching)) { 1064 props->tm_caps.max_num_tags = 1065 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1; 1066 props->tm_caps.max_ops = 1067 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 1068 props->tm_caps.max_sge = MLX5_TM_MAX_SGE; 1069 } 1070 1071 if (MLX5_CAP_GEN(mdev, tag_matching) && 1072 MLX5_CAP_GEN(mdev, rndv_offload_rc)) { 1073 props->tm_caps.flags = IB_TM_CAP_RNDV_RC; 1074 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE; 1075 } 1076 1077 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) { 1078 props->cq_caps.max_cq_moderation_count = 1079 MLX5_MAX_CQ_COUNT; 1080 props->cq_caps.max_cq_moderation_period = 1081 MLX5_MAX_CQ_PERIOD; 1082 } 1083 1084 if (offsetofend(typeof(resp), cqe_comp_caps) <= uhw_outlen) { 1085 resp.response_length += sizeof(resp.cqe_comp_caps); 1086 1087 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) { 1088 resp.cqe_comp_caps.max_num = 1089 MLX5_CAP_GEN(dev->mdev, 1090 cqe_compression_max_num); 1091 1092 resp.cqe_comp_caps.supported_format = 1093 MLX5_IB_CQE_RES_FORMAT_HASH | 1094 MLX5_IB_CQE_RES_FORMAT_CSUM; 1095 1096 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index)) 1097 resp.cqe_comp_caps.supported_format |= 1098 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX; 1099 } 1100 } 1101 1102 if (offsetofend(typeof(resp), packet_pacing_caps) <= uhw_outlen && 1103 raw_support) { 1104 if (MLX5_CAP_QOS(mdev, packet_pacing) && 1105 MLX5_CAP_GEN(mdev, qos)) { 1106 resp.packet_pacing_caps.qp_rate_limit_max = 1107 MLX5_CAP_QOS(mdev, packet_pacing_max_rate); 1108 resp.packet_pacing_caps.qp_rate_limit_min = 1109 MLX5_CAP_QOS(mdev, packet_pacing_min_rate); 1110 resp.packet_pacing_caps.supported_qpts |= 1111 1 << IB_QPT_RAW_PACKET; 1112 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) && 1113 MLX5_CAP_QOS(mdev, packet_pacing_typical_size)) 1114 resp.packet_pacing_caps.cap_flags |= 1115 MLX5_IB_PP_SUPPORT_BURST; 1116 } 1117 resp.response_length += sizeof(resp.packet_pacing_caps); 1118 } 1119 1120 if (offsetofend(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes) <= 1121 uhw_outlen) { 1122 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) 1123 resp.mlx5_ib_support_multi_pkt_send_wqes = 1124 MLX5_IB_ALLOW_MPW; 1125 1126 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) 1127 resp.mlx5_ib_support_multi_pkt_send_wqes |= 1128 MLX5_IB_SUPPORT_EMPW; 1129 1130 resp.response_length += 1131 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes); 1132 } 1133 1134 if (offsetofend(typeof(resp), flags) <= uhw_outlen) { 1135 resp.response_length += sizeof(resp.flags); 1136 1137 if (MLX5_CAP_GEN(mdev, cqe_compression_128)) 1138 resp.flags |= 1139 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP; 1140 1141 if (MLX5_CAP_GEN(mdev, cqe_128_always)) 1142 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD; 1143 if (MLX5_CAP_GEN(mdev, qp_packet_based)) 1144 resp.flags |= 1145 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE; 1146 1147 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_SCAT2CQE_DCT; 1148 } 1149 1150 if (offsetofend(typeof(resp), sw_parsing_caps) <= uhw_outlen) { 1151 resp.response_length += sizeof(resp.sw_parsing_caps); 1152 if (MLX5_CAP_ETH(mdev, swp)) { 1153 resp.sw_parsing_caps.sw_parsing_offloads |= 1154 MLX5_IB_SW_PARSING; 1155 1156 if (MLX5_CAP_ETH(mdev, swp_csum)) 1157 resp.sw_parsing_caps.sw_parsing_offloads |= 1158 MLX5_IB_SW_PARSING_CSUM; 1159 1160 if (MLX5_CAP_ETH(mdev, swp_lso)) 1161 resp.sw_parsing_caps.sw_parsing_offloads |= 1162 MLX5_IB_SW_PARSING_LSO; 1163 1164 if (resp.sw_parsing_caps.sw_parsing_offloads) 1165 resp.sw_parsing_caps.supported_qpts = 1166 BIT(IB_QPT_RAW_PACKET); 1167 } 1168 } 1169 1170 if (offsetofend(typeof(resp), striding_rq_caps) <= uhw_outlen && 1171 raw_support) { 1172 resp.response_length += sizeof(resp.striding_rq_caps); 1173 if (MLX5_CAP_GEN(mdev, striding_rq)) { 1174 resp.striding_rq_caps.min_single_stride_log_num_of_bytes = 1175 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES; 1176 resp.striding_rq_caps.max_single_stride_log_num_of_bytes = 1177 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES; 1178 if (MLX5_CAP_GEN(dev->mdev, ext_stride_num_range)) 1179 resp.striding_rq_caps 1180 .min_single_wqe_log_num_of_strides = 1181 MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1182 else 1183 resp.striding_rq_caps 1184 .min_single_wqe_log_num_of_strides = 1185 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES; 1186 resp.striding_rq_caps.max_single_wqe_log_num_of_strides = 1187 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES; 1188 resp.striding_rq_caps.supported_qpts = 1189 BIT(IB_QPT_RAW_PACKET); 1190 } 1191 } 1192 1193 if (offsetofend(typeof(resp), tunnel_offloads_caps) <= uhw_outlen) { 1194 resp.response_length += sizeof(resp.tunnel_offloads_caps); 1195 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan)) 1196 resp.tunnel_offloads_caps |= 1197 MLX5_IB_TUNNELED_OFFLOADS_VXLAN; 1198 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx)) 1199 resp.tunnel_offloads_caps |= 1200 MLX5_IB_TUNNELED_OFFLOADS_GENEVE; 1201 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) 1202 resp.tunnel_offloads_caps |= 1203 MLX5_IB_TUNNELED_OFFLOADS_GRE; 1204 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre)) 1205 resp.tunnel_offloads_caps |= 1206 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE; 1207 if (MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_udp)) 1208 resp.tunnel_offloads_caps |= 1209 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP; 1210 } 1211 1212 if (offsetofend(typeof(resp), dci_streams_caps) <= uhw_outlen) { 1213 resp.response_length += sizeof(resp.dci_streams_caps); 1214 1215 resp.dci_streams_caps.max_log_num_concurent = 1216 MLX5_CAP_GEN(mdev, log_max_dci_stream_channels); 1217 1218 resp.dci_streams_caps.max_log_num_errored = 1219 MLX5_CAP_GEN(mdev, log_max_dci_errored_streams); 1220 } 1221 1222 if (offsetofend(typeof(resp), reserved) <= uhw_outlen) 1223 resp.response_length += sizeof(resp.reserved); 1224 1225 if (offsetofend(typeof(resp), reg_c0) <= uhw_outlen) { 1226 struct mlx5_eswitch *esw = mdev->priv.eswitch; 1227 1228 resp.response_length += sizeof(resp.reg_c0); 1229 1230 if (mlx5_eswitch_mode(mdev) == MLX5_ESWITCH_OFFLOADS && 1231 mlx5_eswitch_vport_match_metadata_enabled(esw)) 1232 fill_esw_mgr_reg_c0(mdev, &resp); 1233 } 1234 1235 if (uhw_outlen) { 1236 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 1237 1238 if (err) 1239 return err; 1240 } 1241 1242 return 0; 1243} 1244 1245static void translate_active_width(struct ib_device *ibdev, u16 active_width, 1246 u8 *ib_width) 1247{ 1248 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1249 1250 if (active_width & MLX5_PTYS_WIDTH_1X) 1251 *ib_width = IB_WIDTH_1X; 1252 else if (active_width & MLX5_PTYS_WIDTH_2X) 1253 *ib_width = IB_WIDTH_2X; 1254 else if (active_width & MLX5_PTYS_WIDTH_4X) 1255 *ib_width = IB_WIDTH_4X; 1256 else if (active_width & MLX5_PTYS_WIDTH_8X) 1257 *ib_width = IB_WIDTH_8X; 1258 else if (active_width & MLX5_PTYS_WIDTH_12X) 1259 *ib_width = IB_WIDTH_12X; 1260 else { 1261 mlx5_ib_dbg(dev, "Invalid active_width %d, setting width to default value: 4x\n", 1262 active_width); 1263 *ib_width = IB_WIDTH_4X; 1264 } 1265 1266 return; 1267} 1268 1269static int mlx5_mtu_to_ib_mtu(int mtu) 1270{ 1271 switch (mtu) { 1272 case 256: return 1; 1273 case 512: return 2; 1274 case 1024: return 3; 1275 case 2048: return 4; 1276 case 4096: return 5; 1277 default: 1278 pr_warn("invalid mtu\n"); 1279 return -1; 1280 } 1281} 1282 1283enum ib_max_vl_num { 1284 __IB_MAX_VL_0 = 1, 1285 __IB_MAX_VL_0_1 = 2, 1286 __IB_MAX_VL_0_3 = 3, 1287 __IB_MAX_VL_0_7 = 4, 1288 __IB_MAX_VL_0_14 = 5, 1289}; 1290 1291enum mlx5_vl_hw_cap { 1292 MLX5_VL_HW_0 = 1, 1293 MLX5_VL_HW_0_1 = 2, 1294 MLX5_VL_HW_0_2 = 3, 1295 MLX5_VL_HW_0_3 = 4, 1296 MLX5_VL_HW_0_4 = 5, 1297 MLX5_VL_HW_0_5 = 6, 1298 MLX5_VL_HW_0_6 = 7, 1299 MLX5_VL_HW_0_7 = 8, 1300 MLX5_VL_HW_0_14 = 15 1301}; 1302 1303static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 1304 u8 *max_vl_num) 1305{ 1306 switch (vl_hw_cap) { 1307 case MLX5_VL_HW_0: 1308 *max_vl_num = __IB_MAX_VL_0; 1309 break; 1310 case MLX5_VL_HW_0_1: 1311 *max_vl_num = __IB_MAX_VL_0_1; 1312 break; 1313 case MLX5_VL_HW_0_3: 1314 *max_vl_num = __IB_MAX_VL_0_3; 1315 break; 1316 case MLX5_VL_HW_0_7: 1317 *max_vl_num = __IB_MAX_VL_0_7; 1318 break; 1319 case MLX5_VL_HW_0_14: 1320 *max_vl_num = __IB_MAX_VL_0_14; 1321 break; 1322 1323 default: 1324 return -EINVAL; 1325 } 1326 1327 return 0; 1328} 1329 1330static int mlx5_query_hca_port(struct ib_device *ibdev, u32 port, 1331 struct ib_port_attr *props) 1332{ 1333 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1334 struct mlx5_core_dev *mdev = dev->mdev; 1335 struct mlx5_hca_vport_context *rep; 1336 u16 max_mtu; 1337 u16 oper_mtu; 1338 int err; 1339 u16 ib_link_width_oper; 1340 u8 vl_hw_cap; 1341 1342 rep = kzalloc(sizeof(*rep), GFP_KERNEL); 1343 if (!rep) { 1344 err = -ENOMEM; 1345 goto out; 1346 } 1347 1348 /* props being zeroed by the caller, avoid zeroing it here */ 1349 1350 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep); 1351 if (err) 1352 goto out; 1353 1354 props->lid = rep->lid; 1355 props->lmc = rep->lmc; 1356 props->sm_lid = rep->sm_lid; 1357 props->sm_sl = rep->sm_sl; 1358 props->state = rep->vport_state; 1359 props->phys_state = rep->port_physical_state; 1360 props->port_cap_flags = rep->cap_mask1; 1361 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 1362 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 1363 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 1364 props->bad_pkey_cntr = rep->pkey_violation_counter; 1365 props->qkey_viol_cntr = rep->qkey_violation_counter; 1366 props->subnet_timeout = rep->subnet_timeout; 1367 props->init_type_reply = rep->init_type_reply; 1368 1369 if (props->port_cap_flags & IB_PORT_CAP_MASK2_SUP) 1370 props->port_cap_flags2 = rep->cap_mask2; 1371 1372 err = mlx5_query_ib_port_oper(mdev, &ib_link_width_oper, 1373 &props->active_speed, port); 1374 if (err) 1375 goto out; 1376 1377 translate_active_width(ibdev, ib_link_width_oper, &props->active_width); 1378 1379 mlx5_query_port_max_mtu(mdev, &max_mtu, port); 1380 1381 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu); 1382 1383 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port); 1384 1385 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu); 1386 1387 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port); 1388 if (err) 1389 goto out; 1390 1391 err = translate_max_vl_num(ibdev, vl_hw_cap, 1392 &props->max_vl_num); 1393out: 1394 kfree(rep); 1395 return err; 1396} 1397 1398int mlx5_ib_query_port(struct ib_device *ibdev, u32 port, 1399 struct ib_port_attr *props) 1400{ 1401 unsigned int count; 1402 int ret; 1403 1404 switch (mlx5_get_vport_access_method(ibdev)) { 1405 case MLX5_VPORT_ACCESS_METHOD_MAD: 1406 ret = mlx5_query_mad_ifc_port(ibdev, port, props); 1407 break; 1408 1409 case MLX5_VPORT_ACCESS_METHOD_HCA: 1410 ret = mlx5_query_hca_port(ibdev, port, props); 1411 break; 1412 1413 case MLX5_VPORT_ACCESS_METHOD_NIC: 1414 ret = mlx5_query_port_roce(ibdev, port, props); 1415 break; 1416 1417 default: 1418 ret = -EINVAL; 1419 } 1420 1421 if (!ret && props) { 1422 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1423 struct mlx5_core_dev *mdev; 1424 bool put_mdev = true; 1425 1426 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL); 1427 if (!mdev) { 1428 /* If the port isn't affiliated yet query the master. 1429 * The master and slave will have the same values. 1430 */ 1431 mdev = dev->mdev; 1432 port = 1; 1433 put_mdev = false; 1434 } 1435 count = mlx5_core_reserved_gids_count(mdev); 1436 if (put_mdev) 1437 mlx5_ib_put_native_port_mdev(dev, port); 1438 props->gid_tbl_len -= count; 1439 } 1440 return ret; 1441} 1442 1443static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u32 port, 1444 struct ib_port_attr *props) 1445{ 1446 return mlx5_query_port_roce(ibdev, port, props); 1447} 1448 1449static int mlx5_ib_rep_query_pkey(struct ib_device *ibdev, u32 port, u16 index, 1450 u16 *pkey) 1451{ 1452 /* Default special Pkey for representor device port as per the 1453 * IB specification 1.3 section 10.9.1.2. 1454 */ 1455 *pkey = 0xffff; 1456 return 0; 1457} 1458 1459static int mlx5_ib_query_gid(struct ib_device *ibdev, u32 port, int index, 1460 union ib_gid *gid) 1461{ 1462 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1463 struct mlx5_core_dev *mdev = dev->mdev; 1464 1465 switch (mlx5_get_vport_access_method(ibdev)) { 1466 case MLX5_VPORT_ACCESS_METHOD_MAD: 1467 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1468 1469 case MLX5_VPORT_ACCESS_METHOD_HCA: 1470 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid); 1471 1472 default: 1473 return -EINVAL; 1474 } 1475 1476} 1477 1478static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u32 port, 1479 u16 index, u16 *pkey) 1480{ 1481 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1482 struct mlx5_core_dev *mdev; 1483 bool put_mdev = true; 1484 u32 mdev_port_num; 1485 int err; 1486 1487 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num); 1488 if (!mdev) { 1489 /* The port isn't affiliated yet, get the PKey from the master 1490 * port. For RoCE the PKey tables will be the same. 1491 */ 1492 put_mdev = false; 1493 mdev = dev->mdev; 1494 mdev_port_num = 1; 1495 } 1496 1497 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0, 1498 index, pkey); 1499 if (put_mdev) 1500 mlx5_ib_put_native_port_mdev(dev, port); 1501 1502 return err; 1503} 1504 1505static int mlx5_ib_query_pkey(struct ib_device *ibdev, u32 port, u16 index, 1506 u16 *pkey) 1507{ 1508 switch (mlx5_get_vport_access_method(ibdev)) { 1509 case MLX5_VPORT_ACCESS_METHOD_MAD: 1510 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1511 1512 case MLX5_VPORT_ACCESS_METHOD_HCA: 1513 case MLX5_VPORT_ACCESS_METHOD_NIC: 1514 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey); 1515 default: 1516 return -EINVAL; 1517 } 1518} 1519 1520static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1521 struct ib_device_modify *props) 1522{ 1523 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1524 struct mlx5_reg_node_desc in; 1525 struct mlx5_reg_node_desc out; 1526 int err; 1527 1528 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1529 return -EOPNOTSUPP; 1530 1531 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1532 return 0; 1533 1534 /* 1535 * If possible, pass node desc to FW, so it can generate 1536 * a 144 trap. If cmd fails, just ignore. 1537 */ 1538 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1539 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1540 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1541 if (err) 1542 return err; 1543 1544 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1545 1546 return err; 1547} 1548 1549static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u32 port_num, u32 mask, 1550 u32 value) 1551{ 1552 struct mlx5_hca_vport_context ctx = {}; 1553 struct mlx5_core_dev *mdev; 1554 u32 mdev_port_num; 1555 int err; 1556 1557 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num); 1558 if (!mdev) 1559 return -ENODEV; 1560 1561 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx); 1562 if (err) 1563 goto out; 1564 1565 if (~ctx.cap_mask1_perm & mask) { 1566 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n", 1567 mask, ctx.cap_mask1_perm); 1568 err = -EINVAL; 1569 goto out; 1570 } 1571 1572 ctx.cap_mask1 = value; 1573 ctx.cap_mask1_perm = mask; 1574 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num, 1575 0, &ctx); 1576 1577out: 1578 mlx5_ib_put_native_port_mdev(dev, port_num); 1579 1580 return err; 1581} 1582 1583static int mlx5_ib_modify_port(struct ib_device *ibdev, u32 port, int mask, 1584 struct ib_port_modify *props) 1585{ 1586 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1587 struct ib_port_attr attr; 1588 u32 tmp; 1589 int err; 1590 u32 change_mask; 1591 u32 value; 1592 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) == 1593 IB_LINK_LAYER_INFINIBAND); 1594 1595 /* CM layer calls ib_modify_port() regardless of the link layer. For 1596 * Ethernet ports, qkey violation and Port capabilities are meaningless. 1597 */ 1598 if (!is_ib) 1599 return 0; 1600 1601 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) { 1602 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask; 1603 value = ~props->clr_port_cap_mask | props->set_port_cap_mask; 1604 return set_port_caps_atomic(dev, port, change_mask, value); 1605 } 1606 1607 mutex_lock(&dev->cap_mask_mutex); 1608 1609 err = ib_query_port(ibdev, port, &attr); 1610 if (err) 1611 goto out; 1612 1613 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1614 ~props->clr_port_cap_mask; 1615 1616 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1617 1618out: 1619 mutex_unlock(&dev->cap_mask_mutex); 1620 return err; 1621} 1622 1623static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps) 1624{ 1625 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n", 1626 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n"); 1627} 1628 1629static u16 calc_dynamic_bfregs(int uars_per_sys_page) 1630{ 1631 /* Large page with non 4k uar support might limit the dynamic size */ 1632 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096) 1633 return MLX5_MIN_DYN_BFREGS; 1634 1635 return MLX5_MAX_DYN_BFREGS; 1636} 1637 1638static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k, 1639 struct mlx5_ib_alloc_ucontext_req_v2 *req, 1640 struct mlx5_bfreg_info *bfregi) 1641{ 1642 int uars_per_sys_page; 1643 int bfregs_per_sys_page; 1644 int ref_bfregs = req->total_num_bfregs; 1645 1646 if (req->total_num_bfregs == 0) 1647 return -EINVAL; 1648 1649 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE); 1650 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE); 1651 1652 if (req->total_num_bfregs > MLX5_MAX_BFREGS) 1653 return -ENOMEM; 1654 1655 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k); 1656 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR; 1657 /* This holds the required static allocation asked by the user */ 1658 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page); 1659 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1) 1660 return -EINVAL; 1661 1662 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page; 1663 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page); 1664 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs; 1665 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page; 1666 1667 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n", 1668 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no", 1669 lib_uar_4k ? "yes" : "no", ref_bfregs, 1670 req->total_num_bfregs, bfregi->total_num_bfregs, 1671 bfregi->num_sys_pages); 1672 1673 return 0; 1674} 1675 1676static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context) 1677{ 1678 struct mlx5_bfreg_info *bfregi; 1679 int err; 1680 int i; 1681 1682 bfregi = &context->bfregi; 1683 for (i = 0; i < bfregi->num_static_sys_pages; i++) { 1684 err = mlx5_cmd_uar_alloc(dev->mdev, &bfregi->sys_pages[i], 1685 context->devx_uid); 1686 if (err) 1687 goto error; 1688 1689 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]); 1690 } 1691 1692 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++) 1693 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX; 1694 1695 return 0; 1696 1697error: 1698 for (--i; i >= 0; i--) 1699 if (mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i], 1700 context->devx_uid)) 1701 mlx5_ib_warn(dev, "failed to free uar %d\n", i); 1702 1703 return err; 1704} 1705 1706static void deallocate_uars(struct mlx5_ib_dev *dev, 1707 struct mlx5_ib_ucontext *context) 1708{ 1709 struct mlx5_bfreg_info *bfregi; 1710 int i; 1711 1712 bfregi = &context->bfregi; 1713 for (i = 0; i < bfregi->num_sys_pages; i++) 1714 if (i < bfregi->num_static_sys_pages || 1715 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX) 1716 mlx5_cmd_uar_dealloc(dev->mdev, bfregi->sys_pages[i], 1717 context->devx_uid); 1718} 1719 1720int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1721{ 1722 int err = 0; 1723 1724 mutex_lock(&dev->lb.mutex); 1725 if (td) 1726 dev->lb.user_td++; 1727 if (qp) 1728 dev->lb.qps++; 1729 1730 if (dev->lb.user_td == 2 || 1731 dev->lb.qps == 1) { 1732 if (!dev->lb.enabled) { 1733 err = mlx5_nic_vport_update_local_lb(dev->mdev, true); 1734 dev->lb.enabled = true; 1735 } 1736 } 1737 1738 mutex_unlock(&dev->lb.mutex); 1739 1740 return err; 1741} 1742 1743void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp) 1744{ 1745 mutex_lock(&dev->lb.mutex); 1746 if (td) 1747 dev->lb.user_td--; 1748 if (qp) 1749 dev->lb.qps--; 1750 1751 if (dev->lb.user_td == 1 && 1752 dev->lb.qps == 0) { 1753 if (dev->lb.enabled) { 1754 mlx5_nic_vport_update_local_lb(dev->mdev, false); 1755 dev->lb.enabled = false; 1756 } 1757 } 1758 1759 mutex_unlock(&dev->lb.mutex); 1760} 1761 1762static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn, 1763 u16 uid) 1764{ 1765 int err; 1766 1767 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1768 return 0; 1769 1770 err = mlx5_cmd_alloc_transport_domain(dev->mdev, tdn, uid); 1771 if (err) 1772 return err; 1773 1774 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1775 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1776 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1777 return err; 1778 1779 return mlx5_ib_enable_lb(dev, true, false); 1780} 1781 1782static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn, 1783 u16 uid) 1784{ 1785 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1786 return; 1787 1788 mlx5_cmd_dealloc_transport_domain(dev->mdev, tdn, uid); 1789 1790 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) || 1791 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) && 1792 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 1793 return; 1794 1795 mlx5_ib_disable_lb(dev, true, false); 1796} 1797 1798static int set_ucontext_resp(struct ib_ucontext *uctx, 1799 struct mlx5_ib_alloc_ucontext_resp *resp) 1800{ 1801 struct ib_device *ibdev = uctx->device; 1802 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1803 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1804 struct mlx5_bfreg_info *bfregi = &context->bfregi; 1805 1806 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) { 1807 resp->dump_fill_mkey = dev->mkeys.dump_fill_mkey; 1808 resp->comp_mask |= 1809 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY; 1810 } 1811 1812 resp->qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1813 if (dev->wc_support) 1814 resp->bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, 1815 log_bf_reg_size); 1816 resp->cache_line_size = cache_line_size(); 1817 resp->max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1818 resp->max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1819 resp->max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1820 resp->max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1821 resp->max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1822 resp->cqe_version = context->cqe_version; 1823 resp->log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1824 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT; 1825 resp->num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1826 MLX5_CAP_GEN(dev->mdev, 1827 num_of_uars_per_page) : 1; 1828 resp->tot_bfregs = bfregi->lib_uar_dyn ? 0 : 1829 bfregi->total_num_bfregs - bfregi->num_dyn_bfregs; 1830 resp->num_ports = dev->num_ports; 1831 resp->cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1832 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1833 1834 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) { 1835 mlx5_query_min_inline(dev->mdev, &resp->eth_min_inline); 1836 resp->eth_min_inline++; 1837 } 1838 1839 if (dev->mdev->clock_info) 1840 resp->clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1); 1841 1842 /* 1843 * We don't want to expose information from the PCI bar that is located 1844 * after 4096 bytes, so if the arch only supports larger pages, let's 1845 * pretend we don't support reading the HCA's core clock. This is also 1846 * forced by mmap function. 1847 */ 1848 if (PAGE_SIZE <= 4096) { 1849 resp->comp_mask |= 1850 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1851 resp->hca_core_clock_offset = 1852 offsetof(struct mlx5_init_seg, 1853 internal_timer_h) % PAGE_SIZE; 1854 } 1855 1856 if (MLX5_CAP_GEN(dev->mdev, ece_support)) 1857 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE; 1858 1859 if (rt_supported(MLX5_CAP_GEN(dev->mdev, sq_ts_format)) && 1860 rt_supported(MLX5_CAP_GEN(dev->mdev, rq_ts_format)) && 1861 rt_supported(MLX5_CAP_ROCE(dev->mdev, qp_ts_format))) 1862 resp->comp_mask |= 1863 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS; 1864 1865 resp->num_dyn_bfregs = bfregi->num_dyn_bfregs; 1866 1867 if (MLX5_CAP_GEN(dev->mdev, drain_sigerr)) 1868 resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS; 1869 1870 resp->comp_mask |= 1871 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_MKEY_UPDATE_TAG; 1872 1873 return 0; 1874} 1875 1876static int mlx5_ib_alloc_ucontext(struct ib_ucontext *uctx, 1877 struct ib_udata *udata) 1878{ 1879 struct ib_device *ibdev = uctx->device; 1880 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1881 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1882 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1883 struct mlx5_ib_ucontext *context = to_mucontext(uctx); 1884 struct mlx5_bfreg_info *bfregi; 1885 int ver; 1886 int err; 1887 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1888 max_cqe_version); 1889 bool lib_uar_4k; 1890 bool lib_uar_dyn; 1891 1892 if (!dev->ib_active) 1893 return -EAGAIN; 1894 1895 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1896 ver = 0; 1897 else if (udata->inlen >= min_req_v2) 1898 ver = 2; 1899 else 1900 return -EINVAL; 1901 1902 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req))); 1903 if (err) 1904 return err; 1905 1906 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX) 1907 return -EOPNOTSUPP; 1908 1909 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1910 return -EOPNOTSUPP; 1911 1912 req.total_num_bfregs = ALIGN(req.total_num_bfregs, 1913 MLX5_NON_FP_BFREGS_PER_UAR); 1914 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1) 1915 return -EINVAL; 1916 1917 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) { 1918 err = mlx5_ib_devx_create(dev, true); 1919 if (err < 0) 1920 goto out_ctx; 1921 context->devx_uid = err; 1922 } 1923 1924 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR; 1925 lib_uar_dyn = req.lib_caps & MLX5_LIB_CAP_DYN_UAR; 1926 bfregi = &context->bfregi; 1927 1928 if (lib_uar_dyn) { 1929 bfregi->lib_uar_dyn = lib_uar_dyn; 1930 goto uar_done; 1931 } 1932 1933 /* updates req->total_num_bfregs */ 1934 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi); 1935 if (err) 1936 goto out_devx; 1937 1938 mutex_init(&bfregi->lock); 1939 bfregi->lib_uar_4k = lib_uar_4k; 1940 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count), 1941 GFP_KERNEL); 1942 if (!bfregi->count) { 1943 err = -ENOMEM; 1944 goto out_devx; 1945 } 1946 1947 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages, 1948 sizeof(*bfregi->sys_pages), 1949 GFP_KERNEL); 1950 if (!bfregi->sys_pages) { 1951 err = -ENOMEM; 1952 goto out_count; 1953 } 1954 1955 err = allocate_uars(dev, context); 1956 if (err) 1957 goto out_sys_pages; 1958 1959uar_done: 1960 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn, 1961 context->devx_uid); 1962 if (err) 1963 goto out_uars; 1964 1965 INIT_LIST_HEAD(&context->db_page_list); 1966 mutex_init(&context->db_page_mutex); 1967 1968 context->cqe_version = min_t(__u8, 1969 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1970 req.max_cqe_version); 1971 1972 err = set_ucontext_resp(uctx, &resp); 1973 if (err) 1974 goto out_mdev; 1975 1976 resp.response_length = min(udata->outlen, sizeof(resp)); 1977 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1978 if (err) 1979 goto out_mdev; 1980 1981 bfregi->ver = ver; 1982 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs; 1983 context->lib_caps = req.lib_caps; 1984 print_lib_caps(dev, context->lib_caps); 1985 1986 if (mlx5_ib_lag_should_assign_affinity(dev)) { 1987 u32 port = mlx5_core_native_port_num(dev->mdev) - 1; 1988 1989 atomic_set(&context->tx_port_affinity, 1990 atomic_add_return( 1991 1, &dev->port[port].roce.tx_port_affinity)); 1992 } 1993 1994 return 0; 1995 1996out_mdev: 1997 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 1998 1999out_uars: 2000 deallocate_uars(dev, context); 2001 2002out_sys_pages: 2003 kfree(bfregi->sys_pages); 2004 2005out_count: 2006 kfree(bfregi->count); 2007 2008out_devx: 2009 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) 2010 mlx5_ib_devx_destroy(dev, context->devx_uid); 2011 2012out_ctx: 2013 return err; 2014} 2015 2016static int mlx5_ib_query_ucontext(struct ib_ucontext *ibcontext, 2017 struct uverbs_attr_bundle *attrs) 2018{ 2019 struct mlx5_ib_alloc_ucontext_resp uctx_resp = {}; 2020 int ret; 2021 2022 ret = set_ucontext_resp(ibcontext, &uctx_resp); 2023 if (ret) 2024 return ret; 2025 2026 uctx_resp.response_length = 2027 min_t(size_t, 2028 uverbs_attr_get_len(attrs, 2029 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX), 2030 sizeof(uctx_resp)); 2031 2032 ret = uverbs_copy_to_struct_or_zero(attrs, 2033 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 2034 &uctx_resp, 2035 sizeof(uctx_resp)); 2036 return ret; 2037} 2038 2039static void mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 2040{ 2041 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2042 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2043 struct mlx5_bfreg_info *bfregi; 2044 2045 bfregi = &context->bfregi; 2046 mlx5_ib_dealloc_transport_domain(dev, context->tdn, context->devx_uid); 2047 2048 deallocate_uars(dev, context); 2049 kfree(bfregi->sys_pages); 2050 kfree(bfregi->count); 2051 2052 if (context->devx_uid) 2053 mlx5_ib_devx_destroy(dev, context->devx_uid); 2054} 2055 2056static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, 2057 int uar_idx) 2058{ 2059 int fw_uars_per_page; 2060 2061 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1; 2062 2063 return (dev->mdev->bar_addr >> PAGE_SHIFT) + uar_idx / fw_uars_per_page; 2064} 2065 2066static u64 uar_index2paddress(struct mlx5_ib_dev *dev, 2067 int uar_idx) 2068{ 2069 unsigned int fw_uars_per_page; 2070 2071 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? 2072 MLX5_UARS_IN_PAGE : 1; 2073 2074 return (dev->mdev->bar_addr + (uar_idx / fw_uars_per_page) * PAGE_SIZE); 2075} 2076 2077static int get_command(unsigned long offset) 2078{ 2079 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 2080} 2081 2082static int get_arg(unsigned long offset) 2083{ 2084 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 2085} 2086 2087static int get_index(unsigned long offset) 2088{ 2089 return get_arg(offset); 2090} 2091 2092/* Index resides in an extra byte to enable larger values than 255 */ 2093static int get_extended_index(unsigned long offset) 2094{ 2095 return get_arg(offset) | ((offset >> 16) & 0xff) << 8; 2096} 2097 2098 2099static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 2100{ 2101} 2102 2103static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 2104{ 2105 switch (cmd) { 2106 case MLX5_IB_MMAP_WC_PAGE: 2107 return "WC"; 2108 case MLX5_IB_MMAP_REGULAR_PAGE: 2109 return "best effort WC"; 2110 case MLX5_IB_MMAP_NC_PAGE: 2111 return "NC"; 2112 case MLX5_IB_MMAP_DEVICE_MEM: 2113 return "Device Memory"; 2114 default: 2115 return "Unknown"; 2116 } 2117} 2118 2119static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev, 2120 struct vm_area_struct *vma, 2121 struct mlx5_ib_ucontext *context) 2122{ 2123 if ((vma->vm_end - vma->vm_start != PAGE_SIZE) || 2124 !(vma->vm_flags & VM_SHARED)) 2125 return -EINVAL; 2126 2127 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1) 2128 return -EOPNOTSUPP; 2129 2130 if (vma->vm_flags & (VM_WRITE | VM_EXEC)) 2131 return -EPERM; 2132 vm_flags_clear(vma, VM_MAYWRITE); 2133 2134 if (!dev->mdev->clock_info) 2135 return -EOPNOTSUPP; 2136 2137 return vm_insert_page(vma, vma->vm_start, 2138 virt_to_page(dev->mdev->clock_info)); 2139} 2140 2141static void mlx5_ib_mmap_free(struct rdma_user_mmap_entry *entry) 2142{ 2143 struct mlx5_user_mmap_entry *mentry = to_mmmap(entry); 2144 struct mlx5_ib_dev *dev = to_mdev(entry->ucontext->device); 2145 struct mlx5_var_table *var_table = &dev->var_table; 2146 struct mlx5_ib_ucontext *context = to_mucontext(entry->ucontext); 2147 2148 switch (mentry->mmap_flag) { 2149 case MLX5_IB_MMAP_TYPE_MEMIC: 2150 case MLX5_IB_MMAP_TYPE_MEMIC_OP: 2151 mlx5_ib_dm_mmap_free(dev, mentry); 2152 break; 2153 case MLX5_IB_MMAP_TYPE_VAR: 2154 mutex_lock(&var_table->bitmap_lock); 2155 clear_bit(mentry->page_idx, var_table->bitmap); 2156 mutex_unlock(&var_table->bitmap_lock); 2157 kfree(mentry); 2158 break; 2159 case MLX5_IB_MMAP_TYPE_UAR_WC: 2160 case MLX5_IB_MMAP_TYPE_UAR_NC: 2161 mlx5_cmd_uar_dealloc(dev->mdev, mentry->page_idx, 2162 context->devx_uid); 2163 kfree(mentry); 2164 break; 2165 default: 2166 WARN_ON(true); 2167 } 2168} 2169 2170static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 2171 struct vm_area_struct *vma, 2172 struct mlx5_ib_ucontext *context) 2173{ 2174 struct mlx5_bfreg_info *bfregi = &context->bfregi; 2175 int err; 2176 unsigned long idx; 2177 phys_addr_t pfn; 2178 pgprot_t prot; 2179 u32 bfreg_dyn_idx = 0; 2180 u32 uar_index; 2181 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC); 2182 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages : 2183 bfregi->num_static_sys_pages; 2184 2185 if (bfregi->lib_uar_dyn) 2186 return -EINVAL; 2187 2188 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2189 return -EINVAL; 2190 2191 if (dyn_uar) 2192 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages; 2193 else 2194 idx = get_index(vma->vm_pgoff); 2195 2196 if (idx >= max_valid_idx) { 2197 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n", 2198 idx, max_valid_idx); 2199 return -EINVAL; 2200 } 2201 2202 switch (cmd) { 2203 case MLX5_IB_MMAP_WC_PAGE: 2204 case MLX5_IB_MMAP_ALLOC_WC: 2205 case MLX5_IB_MMAP_REGULAR_PAGE: 2206 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 2207 prot = pgprot_writecombine(vma->vm_page_prot); 2208 break; 2209 case MLX5_IB_MMAP_NC_PAGE: 2210 prot = pgprot_noncached(vma->vm_page_prot); 2211 break; 2212 default: 2213 return -EINVAL; 2214 } 2215 2216 if (dyn_uar) { 2217 int uars_per_page; 2218 2219 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k); 2220 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR); 2221 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) { 2222 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n", 2223 bfreg_dyn_idx, bfregi->total_num_bfregs); 2224 return -EINVAL; 2225 } 2226 2227 mutex_lock(&bfregi->lock); 2228 /* Fail if uar already allocated, first bfreg index of each 2229 * page holds its count. 2230 */ 2231 if (bfregi->count[bfreg_dyn_idx]) { 2232 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx); 2233 mutex_unlock(&bfregi->lock); 2234 return -EINVAL; 2235 } 2236 2237 bfregi->count[bfreg_dyn_idx]++; 2238 mutex_unlock(&bfregi->lock); 2239 2240 err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index, 2241 context->devx_uid); 2242 if (err) { 2243 mlx5_ib_warn(dev, "UAR alloc failed\n"); 2244 goto free_bfreg; 2245 } 2246 } else { 2247 uar_index = bfregi->sys_pages[idx]; 2248 } 2249 2250 pfn = uar_index2pfn(dev, uar_index); 2251 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 2252 2253 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE, 2254 prot, NULL); 2255 if (err) { 2256 mlx5_ib_err(dev, 2257 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n", 2258 err, mmap_cmd2str(cmd)); 2259 goto err; 2260 } 2261 2262 if (dyn_uar) 2263 bfregi->sys_pages[idx] = uar_index; 2264 return 0; 2265 2266err: 2267 if (!dyn_uar) 2268 return err; 2269 2270 mlx5_cmd_uar_dealloc(dev->mdev, idx, context->devx_uid); 2271 2272free_bfreg: 2273 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx); 2274 2275 return err; 2276} 2277 2278static unsigned long mlx5_vma_to_pgoff(struct vm_area_struct *vma) 2279{ 2280 unsigned long idx; 2281 u8 command; 2282 2283 command = get_command(vma->vm_pgoff); 2284 idx = get_extended_index(vma->vm_pgoff); 2285 2286 return (command << 16 | idx); 2287} 2288 2289static int mlx5_ib_mmap_offset(struct mlx5_ib_dev *dev, 2290 struct vm_area_struct *vma, 2291 struct ib_ucontext *ucontext) 2292{ 2293 struct mlx5_user_mmap_entry *mentry; 2294 struct rdma_user_mmap_entry *entry; 2295 unsigned long pgoff; 2296 pgprot_t prot; 2297 phys_addr_t pfn; 2298 int ret; 2299 2300 pgoff = mlx5_vma_to_pgoff(vma); 2301 entry = rdma_user_mmap_entry_get_pgoff(ucontext, pgoff); 2302 if (!entry) 2303 return -EINVAL; 2304 2305 mentry = to_mmmap(entry); 2306 pfn = (mentry->address >> PAGE_SHIFT); 2307 if (mentry->mmap_flag == MLX5_IB_MMAP_TYPE_VAR || 2308 mentry->mmap_flag == MLX5_IB_MMAP_TYPE_UAR_NC) 2309 prot = pgprot_noncached(vma->vm_page_prot); 2310 else 2311 prot = pgprot_writecombine(vma->vm_page_prot); 2312 ret = rdma_user_mmap_io(ucontext, vma, pfn, 2313 entry->npages * PAGE_SIZE, 2314 prot, 2315 entry); 2316 rdma_user_mmap_entry_put(&mentry->rdma_entry); 2317 return ret; 2318} 2319 2320static u64 mlx5_entry_to_mmap_offset(struct mlx5_user_mmap_entry *entry) 2321{ 2322 u64 cmd = (entry->rdma_entry.start_pgoff >> 16) & 0xFFFF; 2323 u64 index = entry->rdma_entry.start_pgoff & 0xFFFF; 2324 2325 return (((index >> 8) << 16) | (cmd << MLX5_IB_MMAP_CMD_SHIFT) | 2326 (index & 0xFF)) << PAGE_SHIFT; 2327} 2328 2329static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 2330{ 2331 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 2332 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 2333 unsigned long command; 2334 phys_addr_t pfn; 2335 2336 command = get_command(vma->vm_pgoff); 2337 switch (command) { 2338 case MLX5_IB_MMAP_WC_PAGE: 2339 case MLX5_IB_MMAP_ALLOC_WC: 2340 if (!dev->wc_support) 2341 return -EPERM; 2342 fallthrough; 2343 case MLX5_IB_MMAP_NC_PAGE: 2344 case MLX5_IB_MMAP_REGULAR_PAGE: 2345 return uar_mmap(dev, command, vma, context); 2346 2347 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 2348 return -ENOSYS; 2349 2350 case MLX5_IB_MMAP_CORE_CLOCK: 2351 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 2352 return -EINVAL; 2353 2354 if (vma->vm_flags & VM_WRITE) 2355 return -EPERM; 2356 vm_flags_clear(vma, VM_MAYWRITE); 2357 2358 /* Don't expose to user-space information it shouldn't have */ 2359 if (PAGE_SIZE > 4096) 2360 return -EOPNOTSUPP; 2361 2362 pfn = (dev->mdev->iseg_base + 2363 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 2364 PAGE_SHIFT; 2365 return rdma_user_mmap_io(&context->ibucontext, vma, pfn, 2366 PAGE_SIZE, 2367 pgprot_noncached(vma->vm_page_prot), 2368 NULL); 2369 case MLX5_IB_MMAP_CLOCK_INFO: 2370 return mlx5_ib_mmap_clock_info_page(dev, vma, context); 2371 2372 default: 2373 return mlx5_ib_mmap_offset(dev, vma, ibcontext); 2374 } 2375 2376 return 0; 2377} 2378 2379static int mlx5_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 2380{ 2381 struct mlx5_ib_pd *pd = to_mpd(ibpd); 2382 struct ib_device *ibdev = ibpd->device; 2383 struct mlx5_ib_alloc_pd_resp resp; 2384 int err; 2385 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {}; 2386 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {}; 2387 u16 uid = 0; 2388 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 2389 udata, struct mlx5_ib_ucontext, ibucontext); 2390 2391 uid = context ? context->devx_uid : 0; 2392 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD); 2393 MLX5_SET(alloc_pd_in, in, uid, uid); 2394 err = mlx5_cmd_exec_inout(to_mdev(ibdev)->mdev, alloc_pd, in, out); 2395 if (err) 2396 return err; 2397 2398 pd->pdn = MLX5_GET(alloc_pd_out, out, pd); 2399 pd->uid = uid; 2400 if (udata) { 2401 resp.pdn = pd->pdn; 2402 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 2403 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid); 2404 return -EFAULT; 2405 } 2406 } 2407 2408 return 0; 2409} 2410 2411static int mlx5_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata) 2412{ 2413 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 2414 struct mlx5_ib_pd *mpd = to_mpd(pd); 2415 2416 return mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid); 2417} 2418 2419static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2420{ 2421 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2422 struct mlx5_ib_qp *mqp = to_mqp(ibqp); 2423 int err; 2424 u16 uid; 2425 2426 uid = ibqp->pd ? 2427 to_mpd(ibqp->pd)->uid : 0; 2428 2429 if (mqp->flags & IB_QP_CREATE_SOURCE_QPN) { 2430 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n"); 2431 return -EOPNOTSUPP; 2432 } 2433 2434 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2435 if (err) 2436 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 2437 ibqp->qp_num, gid->raw); 2438 2439 return err; 2440} 2441 2442static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2443{ 2444 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2445 int err; 2446 u16 uid; 2447 2448 uid = ibqp->pd ? 2449 to_mpd(ibqp->pd)->uid : 0; 2450 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid); 2451 if (err) 2452 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 2453 ibqp->qp_num, gid->raw); 2454 2455 return err; 2456} 2457 2458static int init_node_data(struct mlx5_ib_dev *dev) 2459{ 2460 int err; 2461 2462 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 2463 if (err) 2464 return err; 2465 2466 dev->mdev->rev_id = dev->mdev->pdev->revision; 2467 2468 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 2469} 2470 2471static ssize_t fw_pages_show(struct device *device, 2472 struct device_attribute *attr, char *buf) 2473{ 2474 struct mlx5_ib_dev *dev = 2475 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2476 2477 return sysfs_emit(buf, "%d\n", dev->mdev->priv.fw_pages); 2478} 2479static DEVICE_ATTR_RO(fw_pages); 2480 2481static ssize_t reg_pages_show(struct device *device, 2482 struct device_attribute *attr, char *buf) 2483{ 2484 struct mlx5_ib_dev *dev = 2485 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2486 2487 return sysfs_emit(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 2488} 2489static DEVICE_ATTR_RO(reg_pages); 2490 2491static ssize_t hca_type_show(struct device *device, 2492 struct device_attribute *attr, char *buf) 2493{ 2494 struct mlx5_ib_dev *dev = 2495 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2496 2497 return sysfs_emit(buf, "MT%d\n", dev->mdev->pdev->device); 2498} 2499static DEVICE_ATTR_RO(hca_type); 2500 2501static ssize_t hw_rev_show(struct device *device, 2502 struct device_attribute *attr, char *buf) 2503{ 2504 struct mlx5_ib_dev *dev = 2505 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2506 2507 return sysfs_emit(buf, "%x\n", dev->mdev->rev_id); 2508} 2509static DEVICE_ATTR_RO(hw_rev); 2510 2511static ssize_t board_id_show(struct device *device, 2512 struct device_attribute *attr, char *buf) 2513{ 2514 struct mlx5_ib_dev *dev = 2515 rdma_device_to_drv_device(device, struct mlx5_ib_dev, ib_dev); 2516 2517 return sysfs_emit(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2518 dev->mdev->board_id); 2519} 2520static DEVICE_ATTR_RO(board_id); 2521 2522static struct attribute *mlx5_class_attributes[] = { 2523 &dev_attr_hw_rev.attr, 2524 &dev_attr_hca_type.attr, 2525 &dev_attr_board_id.attr, 2526 &dev_attr_fw_pages.attr, 2527 &dev_attr_reg_pages.attr, 2528 NULL, 2529}; 2530 2531static const struct attribute_group mlx5_attr_group = { 2532 .attrs = mlx5_class_attributes, 2533}; 2534 2535static void pkey_change_handler(struct work_struct *work) 2536{ 2537 struct mlx5_ib_port_resources *ports = 2538 container_of(work, struct mlx5_ib_port_resources, 2539 pkey_change_work); 2540 2541 if (!ports->gsi) 2542 /* 2543 * We got this event before device was fully configured 2544 * and MAD registration code wasn't called/finished yet. 2545 */ 2546 return; 2547 2548 mlx5_ib_gsi_pkey_change(ports->gsi); 2549} 2550 2551static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2552{ 2553 struct mlx5_ib_qp *mqp; 2554 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2555 struct mlx5_core_cq *mcq; 2556 struct list_head cq_armed_list; 2557 unsigned long flags_qp; 2558 unsigned long flags_cq; 2559 unsigned long flags; 2560 2561 INIT_LIST_HEAD(&cq_armed_list); 2562 2563 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2564 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2565 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2566 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2567 if (mqp->sq.tail != mqp->sq.head) { 2568 send_mcq = to_mcq(mqp->ibqp.send_cq); 2569 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2570 if (send_mcq->mcq.comp && 2571 mqp->ibqp.send_cq->comp_handler) { 2572 if (!send_mcq->mcq.reset_notify_added) { 2573 send_mcq->mcq.reset_notify_added = 1; 2574 list_add_tail(&send_mcq->mcq.reset_notify, 2575 &cq_armed_list); 2576 } 2577 } 2578 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2579 } 2580 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2581 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 2582 /* no handling is needed for SRQ */ 2583 if (!mqp->ibqp.srq) { 2584 if (mqp->rq.tail != mqp->rq.head) { 2585 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 2586 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 2587 if (recv_mcq->mcq.comp && 2588 mqp->ibqp.recv_cq->comp_handler) { 2589 if (!recv_mcq->mcq.reset_notify_added) { 2590 recv_mcq->mcq.reset_notify_added = 1; 2591 list_add_tail(&recv_mcq->mcq.reset_notify, 2592 &cq_armed_list); 2593 } 2594 } 2595 spin_unlock_irqrestore(&recv_mcq->lock, 2596 flags_cq); 2597 } 2598 } 2599 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 2600 } 2601 /*At that point all inflight post send were put to be executed as of we 2602 * lock/unlock above locks Now need to arm all involved CQs. 2603 */ 2604 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 2605 mcq->comp(mcq, NULL); 2606 } 2607 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 2608} 2609 2610static void delay_drop_handler(struct work_struct *work) 2611{ 2612 int err; 2613 struct mlx5_ib_delay_drop *delay_drop = 2614 container_of(work, struct mlx5_ib_delay_drop, 2615 delay_drop_work); 2616 2617 atomic_inc(&delay_drop->events_cnt); 2618 2619 mutex_lock(&delay_drop->lock); 2620 err = mlx5_core_set_delay_drop(delay_drop->dev, delay_drop->timeout); 2621 if (err) { 2622 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n", 2623 delay_drop->timeout); 2624 delay_drop->activate = false; 2625 } 2626 mutex_unlock(&delay_drop->lock); 2627} 2628 2629static void handle_general_event(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 2630 struct ib_event *ibev) 2631{ 2632 u32 port = (eqe->data.port.port >> 4) & 0xf; 2633 2634 switch (eqe->sub_type) { 2635 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT: 2636 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2637 IB_LINK_LAYER_ETHERNET) 2638 schedule_work(&ibdev->delay_drop.delay_drop_work); 2639 break; 2640 default: /* do nothing */ 2641 return; 2642 } 2643} 2644 2645static int handle_port_change(struct mlx5_ib_dev *ibdev, struct mlx5_eqe *eqe, 2646 struct ib_event *ibev) 2647{ 2648 u32 port = (eqe->data.port.port >> 4) & 0xf; 2649 2650 ibev->element.port_num = port; 2651 2652 switch (eqe->sub_type) { 2653 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 2654 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 2655 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 2656 /* In RoCE, port up/down events are handled in 2657 * mlx5_netdev_event(). 2658 */ 2659 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2660 IB_LINK_LAYER_ETHERNET) 2661 return -EINVAL; 2662 2663 ibev->event = (eqe->sub_type == MLX5_PORT_CHANGE_SUBTYPE_ACTIVE) ? 2664 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 2665 break; 2666 2667 case MLX5_PORT_CHANGE_SUBTYPE_LID: 2668 ibev->event = IB_EVENT_LID_CHANGE; 2669 break; 2670 2671 case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 2672 ibev->event = IB_EVENT_PKEY_CHANGE; 2673 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 2674 break; 2675 2676 case MLX5_PORT_CHANGE_SUBTYPE_GUID: 2677 ibev->event = IB_EVENT_GID_CHANGE; 2678 break; 2679 2680 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 2681 ibev->event = IB_EVENT_CLIENT_REREGISTER; 2682 break; 2683 default: 2684 return -EINVAL; 2685 } 2686 2687 return 0; 2688} 2689 2690static void mlx5_ib_handle_event(struct work_struct *_work) 2691{ 2692 struct mlx5_ib_event_work *work = 2693 container_of(_work, struct mlx5_ib_event_work, work); 2694 struct mlx5_ib_dev *ibdev; 2695 struct ib_event ibev; 2696 bool fatal = false; 2697 2698 if (work->is_slave) { 2699 ibdev = mlx5_ib_get_ibdev_from_mpi(work->mpi); 2700 if (!ibdev) 2701 goto out; 2702 } else { 2703 ibdev = work->dev; 2704 } 2705 2706 switch (work->event) { 2707 case MLX5_DEV_EVENT_SYS_ERROR: 2708 ibev.event = IB_EVENT_DEVICE_FATAL; 2709 mlx5_ib_handle_internal_error(ibdev); 2710 ibev.element.port_num = (u8)(unsigned long)work->param; 2711 fatal = true; 2712 break; 2713 case MLX5_EVENT_TYPE_PORT_CHANGE: 2714 if (handle_port_change(ibdev, work->param, &ibev)) 2715 goto out; 2716 break; 2717 case MLX5_EVENT_TYPE_GENERAL_EVENT: 2718 handle_general_event(ibdev, work->param, &ibev); 2719 fallthrough; 2720 default: 2721 goto out; 2722 } 2723 2724 ibev.device = &ibdev->ib_dev; 2725 2726 if (!rdma_is_port_valid(&ibdev->ib_dev, ibev.element.port_num)) { 2727 mlx5_ib_warn(ibdev, "warning: event on port %d\n", ibev.element.port_num); 2728 goto out; 2729 } 2730 2731 if (ibdev->ib_active) 2732 ib_dispatch_event(&ibev); 2733 2734 if (fatal) 2735 ibdev->ib_active = false; 2736out: 2737 kfree(work); 2738} 2739 2740static int mlx5_ib_event(struct notifier_block *nb, 2741 unsigned long event, void *param) 2742{ 2743 struct mlx5_ib_event_work *work; 2744 2745 work = kmalloc(sizeof(*work), GFP_ATOMIC); 2746 if (!work) 2747 return NOTIFY_DONE; 2748 2749 INIT_WORK(&work->work, mlx5_ib_handle_event); 2750 work->dev = container_of(nb, struct mlx5_ib_dev, mdev_events); 2751 work->is_slave = false; 2752 work->param = param; 2753 work->event = event; 2754 2755 queue_work(mlx5_ib_event_wq, &work->work); 2756 2757 return NOTIFY_OK; 2758} 2759 2760static int mlx5_ib_event_slave_port(struct notifier_block *nb, 2761 unsigned long event, void *param) 2762{ 2763 struct mlx5_ib_event_work *work; 2764 2765 work = kmalloc(sizeof(*work), GFP_ATOMIC); 2766 if (!work) 2767 return NOTIFY_DONE; 2768 2769 INIT_WORK(&work->work, mlx5_ib_handle_event); 2770 work->mpi = container_of(nb, struct mlx5_ib_multiport_info, mdev_events); 2771 work->is_slave = true; 2772 work->param = param; 2773 work->event = event; 2774 queue_work(mlx5_ib_event_wq, &work->work); 2775 2776 return NOTIFY_OK; 2777} 2778 2779static int set_has_smi_cap(struct mlx5_ib_dev *dev) 2780{ 2781 struct mlx5_hca_vport_context vport_ctx; 2782 int err; 2783 int port; 2784 2785 if (MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_IB) 2786 return 0; 2787 2788 for (port = 1; port <= dev->num_ports; port++) { 2789 if (!MLX5_CAP_GEN(dev->mdev, ib_virt)) { 2790 dev->port_caps[port - 1].has_smi = true; 2791 continue; 2792 } 2793 err = mlx5_query_hca_vport_context(dev->mdev, 0, port, 0, 2794 &vport_ctx); 2795 if (err) { 2796 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n", 2797 port, err); 2798 return err; 2799 } 2800 dev->port_caps[port - 1].has_smi = vport_ctx.has_smi; 2801 } 2802 2803 return 0; 2804} 2805 2806static void get_ext_port_caps(struct mlx5_ib_dev *dev) 2807{ 2808 unsigned int port; 2809 2810 rdma_for_each_port (&dev->ib_dev, port) 2811 mlx5_query_ext_port_caps(dev, port); 2812} 2813 2814static u8 mlx5_get_umr_fence(u8 umr_fence_cap) 2815{ 2816 switch (umr_fence_cap) { 2817 case MLX5_CAP_UMR_FENCE_NONE: 2818 return MLX5_FENCE_MODE_NONE; 2819 case MLX5_CAP_UMR_FENCE_SMALL: 2820 return MLX5_FENCE_MODE_INITIATOR_SMALL; 2821 default: 2822 return MLX5_FENCE_MODE_STRONG_ORDERING; 2823 } 2824} 2825 2826static int mlx5_ib_dev_res_init(struct mlx5_ib_dev *dev) 2827{ 2828 struct mlx5_ib_resources *devr = &dev->devr; 2829 struct ib_srq_init_attr attr; 2830 struct ib_device *ibdev; 2831 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 2832 int port; 2833 int ret = 0; 2834 2835 ibdev = &dev->ib_dev; 2836 2837 if (!MLX5_CAP_GEN(dev->mdev, xrc)) 2838 return -EOPNOTSUPP; 2839 2840 devr->p0 = ib_alloc_pd(ibdev, 0); 2841 if (IS_ERR(devr->p0)) 2842 return PTR_ERR(devr->p0); 2843 2844 devr->c0 = ib_create_cq(ibdev, NULL, NULL, NULL, &cq_attr); 2845 if (IS_ERR(devr->c0)) { 2846 ret = PTR_ERR(devr->c0); 2847 goto error1; 2848 } 2849 2850 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn0, 0); 2851 if (ret) 2852 goto error2; 2853 2854 ret = mlx5_cmd_xrcd_alloc(dev->mdev, &devr->xrcdn1, 0); 2855 if (ret) 2856 goto error3; 2857 2858 memset(&attr, 0, sizeof(attr)); 2859 attr.attr.max_sge = 1; 2860 attr.attr.max_wr = 1; 2861 attr.srq_type = IB_SRQT_XRC; 2862 attr.ext.cq = devr->c0; 2863 2864 devr->s0 = ib_create_srq(devr->p0, &attr); 2865 if (IS_ERR(devr->s0)) { 2866 ret = PTR_ERR(devr->s0); 2867 goto err_create; 2868 } 2869 2870 memset(&attr, 0, sizeof(attr)); 2871 attr.attr.max_sge = 1; 2872 attr.attr.max_wr = 1; 2873 attr.srq_type = IB_SRQT_BASIC; 2874 2875 devr->s1 = ib_create_srq(devr->p0, &attr); 2876 if (IS_ERR(devr->s1)) { 2877 ret = PTR_ERR(devr->s1); 2878 goto error6; 2879 } 2880 2881 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 2882 INIT_WORK(&devr->ports[port].pkey_change_work, 2883 pkey_change_handler); 2884 2885 return 0; 2886 2887error6: 2888 ib_destroy_srq(devr->s0); 2889err_create: 2890 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0); 2891error3: 2892 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 2893error2: 2894 ib_destroy_cq(devr->c0); 2895error1: 2896 ib_dealloc_pd(devr->p0); 2897 return ret; 2898} 2899 2900static void mlx5_ib_dev_res_cleanup(struct mlx5_ib_dev *dev) 2901{ 2902 struct mlx5_ib_resources *devr = &dev->devr; 2903 int port; 2904 2905 /* 2906 * Make sure no change P_Key work items are still executing. 2907 * 2908 * At this stage, the mlx5_ib_event should be unregistered 2909 * and it ensures that no new works are added. 2910 */ 2911 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) 2912 cancel_work_sync(&devr->ports[port].pkey_change_work); 2913 2914 ib_destroy_srq(devr->s1); 2915 ib_destroy_srq(devr->s0); 2916 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn1, 0); 2917 mlx5_cmd_xrcd_dealloc(dev->mdev, devr->xrcdn0, 0); 2918 ib_destroy_cq(devr->c0); 2919 ib_dealloc_pd(devr->p0); 2920} 2921 2922static u32 get_core_cap_flags(struct ib_device *ibdev, 2923 struct mlx5_hca_vport_context *rep) 2924{ 2925 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2926 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 2927 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 2928 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 2929 bool raw_support = !mlx5_core_mp_enabled(dev->mdev); 2930 u32 ret = 0; 2931 2932 if (rep->grh_required) 2933 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED; 2934 2935 if (ll == IB_LINK_LAYER_INFINIBAND) 2936 return ret | RDMA_CORE_PORT_IBA_IB; 2937 2938 if (raw_support) 2939 ret |= RDMA_CORE_PORT_RAW_PACKET; 2940 2941 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 2942 return ret; 2943 2944 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 2945 return ret; 2946 2947 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 2948 ret |= RDMA_CORE_PORT_IBA_ROCE; 2949 2950 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 2951 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 2952 2953 return ret; 2954} 2955 2956static int mlx5_port_immutable(struct ib_device *ibdev, u32 port_num, 2957 struct ib_port_immutable *immutable) 2958{ 2959 struct ib_port_attr attr; 2960 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2961 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num); 2962 struct mlx5_hca_vport_context rep = {0}; 2963 int err; 2964 2965 err = ib_query_port(ibdev, port_num, &attr); 2966 if (err) 2967 return err; 2968 2969 if (ll == IB_LINK_LAYER_INFINIBAND) { 2970 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0, 2971 &rep); 2972 if (err) 2973 return err; 2974 } 2975 2976 immutable->pkey_tbl_len = attr.pkey_tbl_len; 2977 immutable->gid_tbl_len = attr.gid_tbl_len; 2978 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep); 2979 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 2980 2981 return 0; 2982} 2983 2984static int mlx5_port_rep_immutable(struct ib_device *ibdev, u32 port_num, 2985 struct ib_port_immutable *immutable) 2986{ 2987 struct ib_port_attr attr; 2988 int err; 2989 2990 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 2991 2992 err = ib_query_port(ibdev, port_num, &attr); 2993 if (err) 2994 return err; 2995 2996 immutable->pkey_tbl_len = attr.pkey_tbl_len; 2997 immutable->gid_tbl_len = attr.gid_tbl_len; 2998 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET; 2999 3000 return 0; 3001} 3002 3003static void get_dev_fw_str(struct ib_device *ibdev, char *str) 3004{ 3005 struct mlx5_ib_dev *dev = 3006 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 3007 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d", 3008 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev), 3009 fw_rev_sub(dev->mdev)); 3010} 3011 3012static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev) 3013{ 3014 struct mlx5_core_dev *mdev = dev->mdev; 3015 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev, 3016 MLX5_FLOW_NAMESPACE_LAG); 3017 struct mlx5_flow_table *ft; 3018 int err; 3019 3020 if (!ns || !mlx5_lag_is_active(mdev)) 3021 return 0; 3022 3023 err = mlx5_cmd_create_vport_lag(mdev); 3024 if (err) 3025 return err; 3026 3027 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0); 3028 if (IS_ERR(ft)) { 3029 err = PTR_ERR(ft); 3030 goto err_destroy_vport_lag; 3031 } 3032 3033 dev->flow_db->lag_demux_ft = ft; 3034 dev->lag_ports = mlx5_lag_get_num_ports(mdev); 3035 dev->lag_active = true; 3036 return 0; 3037 3038err_destroy_vport_lag: 3039 mlx5_cmd_destroy_vport_lag(mdev); 3040 return err; 3041} 3042 3043static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev) 3044{ 3045 struct mlx5_core_dev *mdev = dev->mdev; 3046 3047 if (dev->lag_active) { 3048 dev->lag_active = false; 3049 3050 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft); 3051 dev->flow_db->lag_demux_ft = NULL; 3052 3053 mlx5_cmd_destroy_vport_lag(mdev); 3054 } 3055} 3056 3057static void mlx5_netdev_notifier_register(struct mlx5_roce *roce, 3058 struct net_device *netdev) 3059{ 3060 int err; 3061 3062 if (roce->tracking_netdev) 3063 return; 3064 roce->tracking_netdev = netdev; 3065 roce->nb.notifier_call = mlx5_netdev_event; 3066 err = register_netdevice_notifier_dev_net(netdev, &roce->nb, &roce->nn); 3067 WARN_ON(err); 3068} 3069 3070static void mlx5_netdev_notifier_unregister(struct mlx5_roce *roce) 3071{ 3072 if (!roce->tracking_netdev) 3073 return; 3074 unregister_netdevice_notifier_dev_net(roce->tracking_netdev, &roce->nb, 3075 &roce->nn); 3076 roce->tracking_netdev = NULL; 3077} 3078 3079static int mlx5e_mdev_notifier_event(struct notifier_block *nb, 3080 unsigned long event, void *data) 3081{ 3082 struct mlx5_roce *roce = container_of(nb, struct mlx5_roce, mdev_nb); 3083 struct net_device *netdev = data; 3084 3085 switch (event) { 3086 case MLX5_DRIVER_EVENT_UPLINK_NETDEV: 3087 if (netdev) 3088 mlx5_netdev_notifier_register(roce, netdev); 3089 else 3090 mlx5_netdev_notifier_unregister(roce); 3091 break; 3092 default: 3093 return NOTIFY_DONE; 3094 } 3095 3096 return NOTIFY_OK; 3097} 3098 3099static void mlx5_mdev_netdev_track(struct mlx5_ib_dev *dev, u32 port_num) 3100{ 3101 struct mlx5_roce *roce = &dev->port[port_num].roce; 3102 3103 roce->mdev_nb.notifier_call = mlx5e_mdev_notifier_event; 3104 mlx5_blocking_notifier_register(dev->mdev, &roce->mdev_nb); 3105 mlx5_core_uplink_netdev_event_replay(dev->mdev); 3106} 3107 3108static void mlx5_mdev_netdev_untrack(struct mlx5_ib_dev *dev, u32 port_num) 3109{ 3110 struct mlx5_roce *roce = &dev->port[port_num].roce; 3111 3112 mlx5_blocking_notifier_unregister(dev->mdev, &roce->mdev_nb); 3113 mlx5_netdev_notifier_unregister(roce); 3114} 3115 3116static int mlx5_enable_eth(struct mlx5_ib_dev *dev) 3117{ 3118 int err; 3119 3120 if (!dev->is_rep && dev->profile != &raw_eth_profile) { 3121 err = mlx5_nic_vport_enable_roce(dev->mdev); 3122 if (err) 3123 return err; 3124 } 3125 3126 err = mlx5_eth_lag_init(dev); 3127 if (err) 3128 goto err_disable_roce; 3129 3130 return 0; 3131 3132err_disable_roce: 3133 if (!dev->is_rep && dev->profile != &raw_eth_profile) 3134 mlx5_nic_vport_disable_roce(dev->mdev); 3135 3136 return err; 3137} 3138 3139static void mlx5_disable_eth(struct mlx5_ib_dev *dev) 3140{ 3141 mlx5_eth_lag_cleanup(dev); 3142 if (!dev->is_rep && dev->profile != &raw_eth_profile) 3143 mlx5_nic_vport_disable_roce(dev->mdev); 3144} 3145 3146static int mlx5_ib_rn_get_params(struct ib_device *device, u32 port_num, 3147 enum rdma_netdev_t type, 3148 struct rdma_netdev_alloc_params *params) 3149{ 3150 if (type != RDMA_NETDEV_IPOIB) 3151 return -EOPNOTSUPP; 3152 3153 return mlx5_rdma_rn_get_params(to_mdev(device)->mdev, device, params); 3154} 3155 3156static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf, 3157 size_t count, loff_t *pos) 3158{ 3159 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3160 char lbuf[20]; 3161 int len; 3162 3163 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout); 3164 return simple_read_from_buffer(buf, count, pos, lbuf, len); 3165} 3166 3167static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf, 3168 size_t count, loff_t *pos) 3169{ 3170 struct mlx5_ib_delay_drop *delay_drop = filp->private_data; 3171 u32 timeout; 3172 u32 var; 3173 3174 if (kstrtouint_from_user(buf, count, 0, &var)) 3175 return -EFAULT; 3176 3177 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 3178 1000); 3179 if (timeout != var) 3180 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n", 3181 timeout); 3182 3183 delay_drop->timeout = timeout; 3184 3185 return count; 3186} 3187 3188static const struct file_operations fops_delay_drop_timeout = { 3189 .owner = THIS_MODULE, 3190 .open = simple_open, 3191 .write = delay_drop_timeout_write, 3192 .read = delay_drop_timeout_read, 3193}; 3194 3195static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev, 3196 struct mlx5_ib_multiport_info *mpi) 3197{ 3198 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3199 struct mlx5_ib_port *port = &ibdev->port[port_num]; 3200 int comps; 3201 int err; 3202 int i; 3203 3204 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3205 3206 mlx5_core_mp_event_replay(ibdev->mdev, 3207 MLX5_DRIVER_EVENT_AFFILIATION_REMOVED, 3208 NULL); 3209 mlx5_core_mp_event_replay(mpi->mdev, 3210 MLX5_DRIVER_EVENT_AFFILIATION_REMOVED, 3211 NULL); 3212 3213 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num); 3214 3215 spin_lock(&port->mp.mpi_lock); 3216 if (!mpi->ibdev) { 3217 spin_unlock(&port->mp.mpi_lock); 3218 return; 3219 } 3220 3221 mpi->ibdev = NULL; 3222 3223 spin_unlock(&port->mp.mpi_lock); 3224 if (mpi->mdev_events.notifier_call) 3225 mlx5_notifier_unregister(mpi->mdev, &mpi->mdev_events); 3226 mpi->mdev_events.notifier_call = NULL; 3227 mlx5_mdev_netdev_untrack(ibdev, port_num); 3228 spin_lock(&port->mp.mpi_lock); 3229 3230 comps = mpi->mdev_refcnt; 3231 if (comps) { 3232 mpi->unaffiliate = true; 3233 init_completion(&mpi->unref_comp); 3234 spin_unlock(&port->mp.mpi_lock); 3235 3236 for (i = 0; i < comps; i++) 3237 wait_for_completion(&mpi->unref_comp); 3238 3239 spin_lock(&port->mp.mpi_lock); 3240 mpi->unaffiliate = false; 3241 } 3242 3243 port->mp.mpi = NULL; 3244 3245 spin_unlock(&port->mp.mpi_lock); 3246 3247 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev); 3248 3249 mlx5_ib_dbg(ibdev, "unaffiliated port %u\n", port_num + 1); 3250 /* Log an error, still needed to cleanup the pointers and add 3251 * it back to the list. 3252 */ 3253 if (err) 3254 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n", 3255 port_num + 1); 3256 3257 ibdev->port[port_num].roce.last_port_state = IB_PORT_DOWN; 3258} 3259 3260static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev, 3261 struct mlx5_ib_multiport_info *mpi) 3262{ 3263 u32 port_num = mlx5_core_native_port_num(mpi->mdev) - 1; 3264 u64 key; 3265 int err; 3266 3267 lockdep_assert_held(&mlx5_ib_multiport_mutex); 3268 3269 spin_lock(&ibdev->port[port_num].mp.mpi_lock); 3270 if (ibdev->port[port_num].mp.mpi) { 3271 mlx5_ib_dbg(ibdev, "port %u already affiliated.\n", 3272 port_num + 1); 3273 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3274 return false; 3275 } 3276 3277 ibdev->port[port_num].mp.mpi = mpi; 3278 mpi->ibdev = ibdev; 3279 mpi->mdev_events.notifier_call = NULL; 3280 spin_unlock(&ibdev->port[port_num].mp.mpi_lock); 3281 3282 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev); 3283 if (err) 3284 goto unbind; 3285 3286 mlx5_mdev_netdev_track(ibdev, port_num); 3287 3288 mpi->mdev_events.notifier_call = mlx5_ib_event_slave_port; 3289 mlx5_notifier_register(mpi->mdev, &mpi->mdev_events); 3290 3291 mlx5_ib_init_cong_debugfs(ibdev, port_num); 3292 3293 key = mpi->mdev->priv.adev_idx; 3294 mlx5_core_mp_event_replay(mpi->mdev, 3295 MLX5_DRIVER_EVENT_AFFILIATION_DONE, 3296 &key); 3297 mlx5_core_mp_event_replay(ibdev->mdev, 3298 MLX5_DRIVER_EVENT_AFFILIATION_DONE, 3299 &key); 3300 3301 return true; 3302 3303unbind: 3304 mlx5_ib_unbind_slave_port(ibdev, mpi); 3305 return false; 3306} 3307 3308static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev) 3309{ 3310 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3311 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 3312 port_num + 1); 3313 struct mlx5_ib_multiport_info *mpi; 3314 int err; 3315 u32 i; 3316 3317 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 3318 return 0; 3319 3320 err = mlx5_query_nic_vport_system_image_guid(dev->mdev, 3321 &dev->sys_image_guid); 3322 if (err) 3323 return err; 3324 3325 err = mlx5_nic_vport_enable_roce(dev->mdev); 3326 if (err) 3327 return err; 3328 3329 mutex_lock(&mlx5_ib_multiport_mutex); 3330 for (i = 0; i < dev->num_ports; i++) { 3331 bool bound = false; 3332 3333 /* build a stub multiport info struct for the native port. */ 3334 if (i == port_num) { 3335 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 3336 if (!mpi) { 3337 mutex_unlock(&mlx5_ib_multiport_mutex); 3338 mlx5_nic_vport_disable_roce(dev->mdev); 3339 return -ENOMEM; 3340 } 3341 3342 mpi->is_master = true; 3343 mpi->mdev = dev->mdev; 3344 mpi->sys_image_guid = dev->sys_image_guid; 3345 dev->port[i].mp.mpi = mpi; 3346 mpi->ibdev = dev; 3347 mpi = NULL; 3348 continue; 3349 } 3350 3351 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list, 3352 list) { 3353 if (dev->sys_image_guid == mpi->sys_image_guid && 3354 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) { 3355 bound = mlx5_ib_bind_slave_port(dev, mpi); 3356 } 3357 3358 if (bound) { 3359 dev_dbg(mpi->mdev->device, 3360 "removing port from unaffiliated list.\n"); 3361 mlx5_ib_dbg(dev, "port %d bound\n", i + 1); 3362 list_del(&mpi->list); 3363 break; 3364 } 3365 } 3366 if (!bound) 3367 mlx5_ib_dbg(dev, "no free port found for port %d\n", 3368 i + 1); 3369 } 3370 3371 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list); 3372 mutex_unlock(&mlx5_ib_multiport_mutex); 3373 return err; 3374} 3375 3376static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev) 3377{ 3378 u32 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 3379 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 3380 port_num + 1); 3381 u32 i; 3382 3383 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET) 3384 return; 3385 3386 mutex_lock(&mlx5_ib_multiport_mutex); 3387 for (i = 0; i < dev->num_ports; i++) { 3388 if (dev->port[i].mp.mpi) { 3389 /* Destroy the native port stub */ 3390 if (i == port_num) { 3391 kfree(dev->port[i].mp.mpi); 3392 dev->port[i].mp.mpi = NULL; 3393 } else { 3394 mlx5_ib_dbg(dev, "unbinding port_num: %u\n", 3395 i + 1); 3396 list_add_tail(&dev->port[i].mp.mpi->list, 3397 &mlx5_ib_unaffiliated_port_list); 3398 mlx5_ib_unbind_slave_port(dev, 3399 dev->port[i].mp.mpi); 3400 } 3401 } 3402 } 3403 3404 mlx5_ib_dbg(dev, "removing from devlist\n"); 3405 list_del(&dev->ib_dev_list); 3406 mutex_unlock(&mlx5_ib_multiport_mutex); 3407 3408 mlx5_nic_vport_disable_roce(dev->mdev); 3409} 3410 3411static int mmap_obj_cleanup(struct ib_uobject *uobject, 3412 enum rdma_remove_reason why, 3413 struct uverbs_attr_bundle *attrs) 3414{ 3415 struct mlx5_user_mmap_entry *obj = uobject->object; 3416 3417 rdma_user_mmap_entry_remove(&obj->rdma_entry); 3418 return 0; 3419} 3420 3421static int mlx5_rdma_user_mmap_entry_insert(struct mlx5_ib_ucontext *c, 3422 struct mlx5_user_mmap_entry *entry, 3423 size_t length) 3424{ 3425 return rdma_user_mmap_entry_insert_range( 3426 &c->ibucontext, &entry->rdma_entry, length, 3427 (MLX5_IB_MMAP_OFFSET_START << 16), 3428 ((MLX5_IB_MMAP_OFFSET_END << 16) + (1UL << 16) - 1)); 3429} 3430 3431static struct mlx5_user_mmap_entry * 3432alloc_var_entry(struct mlx5_ib_ucontext *c) 3433{ 3434 struct mlx5_user_mmap_entry *entry; 3435 struct mlx5_var_table *var_table; 3436 u32 page_idx; 3437 int err; 3438 3439 var_table = &to_mdev(c->ibucontext.device)->var_table; 3440 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 3441 if (!entry) 3442 return ERR_PTR(-ENOMEM); 3443 3444 mutex_lock(&var_table->bitmap_lock); 3445 page_idx = find_first_zero_bit(var_table->bitmap, 3446 var_table->num_var_hw_entries); 3447 if (page_idx >= var_table->num_var_hw_entries) { 3448 err = -ENOSPC; 3449 mutex_unlock(&var_table->bitmap_lock); 3450 goto end; 3451 } 3452 3453 set_bit(page_idx, var_table->bitmap); 3454 mutex_unlock(&var_table->bitmap_lock); 3455 3456 entry->address = var_table->hw_start_addr + 3457 (page_idx * var_table->stride_size); 3458 entry->page_idx = page_idx; 3459 entry->mmap_flag = MLX5_IB_MMAP_TYPE_VAR; 3460 3461 err = mlx5_rdma_user_mmap_entry_insert(c, entry, 3462 var_table->stride_size); 3463 if (err) 3464 goto err_insert; 3465 3466 return entry; 3467 3468err_insert: 3469 mutex_lock(&var_table->bitmap_lock); 3470 clear_bit(page_idx, var_table->bitmap); 3471 mutex_unlock(&var_table->bitmap_lock); 3472end: 3473 kfree(entry); 3474 return ERR_PTR(err); 3475} 3476 3477static int UVERBS_HANDLER(MLX5_IB_METHOD_VAR_OBJ_ALLOC)( 3478 struct uverbs_attr_bundle *attrs) 3479{ 3480 struct ib_uobject *uobj = uverbs_attr_get_uobject( 3481 attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 3482 struct mlx5_ib_ucontext *c; 3483 struct mlx5_user_mmap_entry *entry; 3484 u64 mmap_offset; 3485 u32 length; 3486 int err; 3487 3488 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 3489 if (IS_ERR(c)) 3490 return PTR_ERR(c); 3491 3492 entry = alloc_var_entry(c); 3493 if (IS_ERR(entry)) 3494 return PTR_ERR(entry); 3495 3496 mmap_offset = mlx5_entry_to_mmap_offset(entry); 3497 length = entry->rdma_entry.npages * PAGE_SIZE; 3498 uobj->object = entry; 3499 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE); 3500 3501 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 3502 &mmap_offset, sizeof(mmap_offset)); 3503 if (err) 3504 return err; 3505 3506 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 3507 &entry->page_idx, sizeof(entry->page_idx)); 3508 if (err) 3509 return err; 3510 3511 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 3512 &length, sizeof(length)); 3513 return err; 3514} 3515 3516DECLARE_UVERBS_NAMED_METHOD( 3517 MLX5_IB_METHOD_VAR_OBJ_ALLOC, 3518 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_ALLOC_HANDLE, 3519 MLX5_IB_OBJECT_VAR, 3520 UVERBS_ACCESS_NEW, 3521 UA_MANDATORY), 3522 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_PAGE_ID, 3523 UVERBS_ATTR_TYPE(u32), 3524 UA_MANDATORY), 3525 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_LENGTH, 3526 UVERBS_ATTR_TYPE(u32), 3527 UA_MANDATORY), 3528 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_VAR_OBJ_ALLOC_MMAP_OFFSET, 3529 UVERBS_ATTR_TYPE(u64), 3530 UA_MANDATORY)); 3531 3532DECLARE_UVERBS_NAMED_METHOD_DESTROY( 3533 MLX5_IB_METHOD_VAR_OBJ_DESTROY, 3534 UVERBS_ATTR_IDR(MLX5_IB_ATTR_VAR_OBJ_DESTROY_HANDLE, 3535 MLX5_IB_OBJECT_VAR, 3536 UVERBS_ACCESS_DESTROY, 3537 UA_MANDATORY)); 3538 3539DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_VAR, 3540 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 3541 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_ALLOC), 3542 &UVERBS_METHOD(MLX5_IB_METHOD_VAR_OBJ_DESTROY)); 3543 3544static bool var_is_supported(struct ib_device *device) 3545{ 3546 struct mlx5_ib_dev *dev = to_mdev(device); 3547 3548 return (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 3549 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q); 3550} 3551 3552static struct mlx5_user_mmap_entry * 3553alloc_uar_entry(struct mlx5_ib_ucontext *c, 3554 enum mlx5_ib_uapi_uar_alloc_type alloc_type) 3555{ 3556 struct mlx5_user_mmap_entry *entry; 3557 struct mlx5_ib_dev *dev; 3558 u32 uar_index; 3559 int err; 3560 3561 entry = kzalloc(sizeof(*entry), GFP_KERNEL); 3562 if (!entry) 3563 return ERR_PTR(-ENOMEM); 3564 3565 dev = to_mdev(c->ibucontext.device); 3566 err = mlx5_cmd_uar_alloc(dev->mdev, &uar_index, c->devx_uid); 3567 if (err) 3568 goto end; 3569 3570 entry->page_idx = uar_index; 3571 entry->address = uar_index2paddress(dev, uar_index); 3572 if (alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 3573 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_WC; 3574 else 3575 entry->mmap_flag = MLX5_IB_MMAP_TYPE_UAR_NC; 3576 3577 err = mlx5_rdma_user_mmap_entry_insert(c, entry, PAGE_SIZE); 3578 if (err) 3579 goto err_insert; 3580 3581 return entry; 3582 3583err_insert: 3584 mlx5_cmd_uar_dealloc(dev->mdev, uar_index, c->devx_uid); 3585end: 3586 kfree(entry); 3587 return ERR_PTR(err); 3588} 3589 3590static int UVERBS_HANDLER(MLX5_IB_METHOD_UAR_OBJ_ALLOC)( 3591 struct uverbs_attr_bundle *attrs) 3592{ 3593 struct ib_uobject *uobj = uverbs_attr_get_uobject( 3594 attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 3595 enum mlx5_ib_uapi_uar_alloc_type alloc_type; 3596 struct mlx5_ib_ucontext *c; 3597 struct mlx5_user_mmap_entry *entry; 3598 u64 mmap_offset; 3599 u32 length; 3600 int err; 3601 3602 c = to_mucontext(ib_uverbs_get_ucontext(attrs)); 3603 if (IS_ERR(c)) 3604 return PTR_ERR(c); 3605 3606 err = uverbs_get_const(&alloc_type, attrs, 3607 MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE); 3608 if (err) 3609 return err; 3610 3611 if (alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF && 3612 alloc_type != MLX5_IB_UAPI_UAR_ALLOC_TYPE_NC) 3613 return -EOPNOTSUPP; 3614 3615 if (!to_mdev(c->ibucontext.device)->wc_support && 3616 alloc_type == MLX5_IB_UAPI_UAR_ALLOC_TYPE_BF) 3617 return -EOPNOTSUPP; 3618 3619 entry = alloc_uar_entry(c, alloc_type); 3620 if (IS_ERR(entry)) 3621 return PTR_ERR(entry); 3622 3623 mmap_offset = mlx5_entry_to_mmap_offset(entry); 3624 length = entry->rdma_entry.npages * PAGE_SIZE; 3625 uobj->object = entry; 3626 uverbs_finalize_uobj_create(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE); 3627 3628 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 3629 &mmap_offset, sizeof(mmap_offset)); 3630 if (err) 3631 return err; 3632 3633 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 3634 &entry->page_idx, sizeof(entry->page_idx)); 3635 if (err) 3636 return err; 3637 3638 err = uverbs_copy_to(attrs, MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 3639 &length, sizeof(length)); 3640 return err; 3641} 3642 3643DECLARE_UVERBS_NAMED_METHOD( 3644 MLX5_IB_METHOD_UAR_OBJ_ALLOC, 3645 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_ALLOC_HANDLE, 3646 MLX5_IB_OBJECT_UAR, 3647 UVERBS_ACCESS_NEW, 3648 UA_MANDATORY), 3649 UVERBS_ATTR_CONST_IN(MLX5_IB_ATTR_UAR_OBJ_ALLOC_TYPE, 3650 enum mlx5_ib_uapi_uar_alloc_type, 3651 UA_MANDATORY), 3652 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_PAGE_ID, 3653 UVERBS_ATTR_TYPE(u32), 3654 UA_MANDATORY), 3655 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_LENGTH, 3656 UVERBS_ATTR_TYPE(u32), 3657 UA_MANDATORY), 3658 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_UAR_OBJ_ALLOC_MMAP_OFFSET, 3659 UVERBS_ATTR_TYPE(u64), 3660 UA_MANDATORY)); 3661 3662DECLARE_UVERBS_NAMED_METHOD_DESTROY( 3663 MLX5_IB_METHOD_UAR_OBJ_DESTROY, 3664 UVERBS_ATTR_IDR(MLX5_IB_ATTR_UAR_OBJ_DESTROY_HANDLE, 3665 MLX5_IB_OBJECT_UAR, 3666 UVERBS_ACCESS_DESTROY, 3667 UA_MANDATORY)); 3668 3669DECLARE_UVERBS_NAMED_OBJECT(MLX5_IB_OBJECT_UAR, 3670 UVERBS_TYPE_ALLOC_IDR(mmap_obj_cleanup), 3671 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_ALLOC), 3672 &UVERBS_METHOD(MLX5_IB_METHOD_UAR_OBJ_DESTROY)); 3673 3674ADD_UVERBS_ATTRIBUTES_SIMPLE( 3675 mlx5_ib_query_context, 3676 UVERBS_OBJECT_DEVICE, 3677 UVERBS_METHOD_QUERY_CONTEXT, 3678 UVERBS_ATTR_PTR_OUT( 3679 MLX5_IB_ATTR_QUERY_CONTEXT_RESP_UCTX, 3680 UVERBS_ATTR_STRUCT(struct mlx5_ib_alloc_ucontext_resp, 3681 dump_fill_mkey), 3682 UA_MANDATORY)); 3683 3684static const struct uapi_definition mlx5_ib_defs[] = { 3685 UAPI_DEF_CHAIN(mlx5_ib_devx_defs), 3686 UAPI_DEF_CHAIN(mlx5_ib_flow_defs), 3687 UAPI_DEF_CHAIN(mlx5_ib_qos_defs), 3688 UAPI_DEF_CHAIN(mlx5_ib_std_types_defs), 3689 UAPI_DEF_CHAIN(mlx5_ib_dm_defs), 3690 3691 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DEVICE, &mlx5_ib_query_context), 3692 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_VAR, 3693 UAPI_DEF_IS_OBJ_SUPPORTED(var_is_supported)), 3694 UAPI_DEF_CHAIN_OBJ_TREE_NAMED(MLX5_IB_OBJECT_UAR), 3695 {} 3696}; 3697 3698static void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev) 3699{ 3700 mlx5_ib_cleanup_multiport_master(dev); 3701 WARN_ON(!xa_empty(&dev->odp_mkeys)); 3702 mutex_destroy(&dev->cap_mask_mutex); 3703 WARN_ON(!xa_empty(&dev->sig_mrs)); 3704 WARN_ON(!bitmap_empty(dev->dm.memic_alloc_pages, MLX5_MAX_MEMIC_PAGES)); 3705 mlx5r_macsec_dealloc_gids(dev); 3706} 3707 3708static int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev) 3709{ 3710 struct mlx5_core_dev *mdev = dev->mdev; 3711 int err, i; 3712 3713 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 3714 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 3715 dev->ib_dev.phys_port_cnt = dev->num_ports; 3716 dev->ib_dev.dev.parent = mdev->device; 3717 dev->ib_dev.lag_flags = RDMA_LAG_FLAGS_HASH_ALL_SLAVES; 3718 3719 for (i = 0; i < dev->num_ports; i++) { 3720 spin_lock_init(&dev->port[i].mp.mpi_lock); 3721 rwlock_init(&dev->port[i].roce.netdev_lock); 3722 dev->port[i].roce.dev = dev; 3723 dev->port[i].roce.native_port_num = i + 1; 3724 dev->port[i].roce.last_port_state = IB_PORT_DOWN; 3725 } 3726 3727 err = mlx5r_cmd_query_special_mkeys(dev); 3728 if (err) 3729 return err; 3730 3731 err = mlx5r_macsec_init_gids_and_devlist(dev); 3732 if (err) 3733 return err; 3734 3735 err = mlx5_ib_init_multiport_master(dev); 3736 if (err) 3737 goto err; 3738 3739 err = set_has_smi_cap(dev); 3740 if (err) 3741 goto err_mp; 3742 3743 err = mlx5_query_max_pkeys(&dev->ib_dev, &dev->pkey_table_len); 3744 if (err) 3745 goto err_mp; 3746 3747 if (mlx5_use_mad_ifc(dev)) 3748 get_ext_port_caps(dev); 3749 3750 dev->ib_dev.num_comp_vectors = mlx5_comp_vectors_max(mdev); 3751 3752 mutex_init(&dev->cap_mask_mutex); 3753 INIT_LIST_HEAD(&dev->qp_list); 3754 spin_lock_init(&dev->reset_flow_resource_lock); 3755 xa_init(&dev->odp_mkeys); 3756 xa_init(&dev->sig_mrs); 3757 atomic_set(&dev->mkey_var, 0); 3758 3759 spin_lock_init(&dev->dm.lock); 3760 dev->dm.dev = mdev; 3761 return 0; 3762err: 3763 mlx5r_macsec_dealloc_gids(dev); 3764err_mp: 3765 mlx5_ib_cleanup_multiport_master(dev); 3766 return err; 3767} 3768 3769static int mlx5_ib_enable_driver(struct ib_device *dev) 3770{ 3771 struct mlx5_ib_dev *mdev = to_mdev(dev); 3772 int ret; 3773 3774 ret = mlx5_ib_test_wc(mdev); 3775 mlx5_ib_dbg(mdev, "Write-Combining %s", 3776 mdev->wc_support ? "supported" : "not supported"); 3777 3778 return ret; 3779} 3780 3781static const struct ib_device_ops mlx5_ib_dev_ops = { 3782 .owner = THIS_MODULE, 3783 .driver_id = RDMA_DRIVER_MLX5, 3784 .uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION, 3785 3786 .add_gid = mlx5_ib_add_gid, 3787 .alloc_mr = mlx5_ib_alloc_mr, 3788 .alloc_mr_integrity = mlx5_ib_alloc_mr_integrity, 3789 .alloc_pd = mlx5_ib_alloc_pd, 3790 .alloc_ucontext = mlx5_ib_alloc_ucontext, 3791 .attach_mcast = mlx5_ib_mcg_attach, 3792 .check_mr_status = mlx5_ib_check_mr_status, 3793 .create_ah = mlx5_ib_create_ah, 3794 .create_cq = mlx5_ib_create_cq, 3795 .create_qp = mlx5_ib_create_qp, 3796 .create_srq = mlx5_ib_create_srq, 3797 .create_user_ah = mlx5_ib_create_ah, 3798 .dealloc_pd = mlx5_ib_dealloc_pd, 3799 .dealloc_ucontext = mlx5_ib_dealloc_ucontext, 3800 .del_gid = mlx5_ib_del_gid, 3801 .dereg_mr = mlx5_ib_dereg_mr, 3802 .destroy_ah = mlx5_ib_destroy_ah, 3803 .destroy_cq = mlx5_ib_destroy_cq, 3804 .destroy_qp = mlx5_ib_destroy_qp, 3805 .destroy_srq = mlx5_ib_destroy_srq, 3806 .detach_mcast = mlx5_ib_mcg_detach, 3807 .disassociate_ucontext = mlx5_ib_disassociate_ucontext, 3808 .drain_rq = mlx5_ib_drain_rq, 3809 .drain_sq = mlx5_ib_drain_sq, 3810 .device_group = &mlx5_attr_group, 3811 .enable_driver = mlx5_ib_enable_driver, 3812 .get_dev_fw_str = get_dev_fw_str, 3813 .get_dma_mr = mlx5_ib_get_dma_mr, 3814 .get_link_layer = mlx5_ib_port_link_layer, 3815 .map_mr_sg = mlx5_ib_map_mr_sg, 3816 .map_mr_sg_pi = mlx5_ib_map_mr_sg_pi, 3817 .mmap = mlx5_ib_mmap, 3818 .mmap_free = mlx5_ib_mmap_free, 3819 .modify_cq = mlx5_ib_modify_cq, 3820 .modify_device = mlx5_ib_modify_device, 3821 .modify_port = mlx5_ib_modify_port, 3822 .modify_qp = mlx5_ib_modify_qp, 3823 .modify_srq = mlx5_ib_modify_srq, 3824 .poll_cq = mlx5_ib_poll_cq, 3825 .post_recv = mlx5_ib_post_recv_nodrain, 3826 .post_send = mlx5_ib_post_send_nodrain, 3827 .post_srq_recv = mlx5_ib_post_srq_recv, 3828 .process_mad = mlx5_ib_process_mad, 3829 .query_ah = mlx5_ib_query_ah, 3830 .query_device = mlx5_ib_query_device, 3831 .query_gid = mlx5_ib_query_gid, 3832 .query_pkey = mlx5_ib_query_pkey, 3833 .query_qp = mlx5_ib_query_qp, 3834 .query_srq = mlx5_ib_query_srq, 3835 .query_ucontext = mlx5_ib_query_ucontext, 3836 .reg_user_mr = mlx5_ib_reg_user_mr, 3837 .reg_user_mr_dmabuf = mlx5_ib_reg_user_mr_dmabuf, 3838 .req_notify_cq = mlx5_ib_arm_cq, 3839 .rereg_user_mr = mlx5_ib_rereg_user_mr, 3840 .resize_cq = mlx5_ib_resize_cq, 3841 3842 INIT_RDMA_OBJ_SIZE(ib_ah, mlx5_ib_ah, ibah), 3843 INIT_RDMA_OBJ_SIZE(ib_counters, mlx5_ib_mcounters, ibcntrs), 3844 INIT_RDMA_OBJ_SIZE(ib_cq, mlx5_ib_cq, ibcq), 3845 INIT_RDMA_OBJ_SIZE(ib_pd, mlx5_ib_pd, ibpd), 3846 INIT_RDMA_OBJ_SIZE(ib_qp, mlx5_ib_qp, ibqp), 3847 INIT_RDMA_OBJ_SIZE(ib_srq, mlx5_ib_srq, ibsrq), 3848 INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx5_ib_ucontext, ibucontext), 3849}; 3850 3851static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops = { 3852 .rdma_netdev_get_params = mlx5_ib_rn_get_params, 3853}; 3854 3855static const struct ib_device_ops mlx5_ib_dev_sriov_ops = { 3856 .get_vf_config = mlx5_ib_get_vf_config, 3857 .get_vf_guid = mlx5_ib_get_vf_guid, 3858 .get_vf_stats = mlx5_ib_get_vf_stats, 3859 .set_vf_guid = mlx5_ib_set_vf_guid, 3860 .set_vf_link_state = mlx5_ib_set_vf_link_state, 3861}; 3862 3863static const struct ib_device_ops mlx5_ib_dev_mw_ops = { 3864 .alloc_mw = mlx5_ib_alloc_mw, 3865 .dealloc_mw = mlx5_ib_dealloc_mw, 3866 3867 INIT_RDMA_OBJ_SIZE(ib_mw, mlx5_ib_mw, ibmw), 3868}; 3869 3870static const struct ib_device_ops mlx5_ib_dev_xrc_ops = { 3871 .alloc_xrcd = mlx5_ib_alloc_xrcd, 3872 .dealloc_xrcd = mlx5_ib_dealloc_xrcd, 3873 3874 INIT_RDMA_OBJ_SIZE(ib_xrcd, mlx5_ib_xrcd, ibxrcd), 3875}; 3876 3877static int mlx5_ib_init_var_table(struct mlx5_ib_dev *dev) 3878{ 3879 struct mlx5_core_dev *mdev = dev->mdev; 3880 struct mlx5_var_table *var_table = &dev->var_table; 3881 u8 log_doorbell_bar_size; 3882 u8 log_doorbell_stride; 3883 u64 bar_size; 3884 3885 log_doorbell_bar_size = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 3886 log_doorbell_bar_size); 3887 log_doorbell_stride = MLX5_CAP_DEV_VDPA_EMULATION(mdev, 3888 log_doorbell_stride); 3889 var_table->hw_start_addr = dev->mdev->bar_addr + 3890 MLX5_CAP64_DEV_VDPA_EMULATION(mdev, 3891 doorbell_bar_offset); 3892 bar_size = (1ULL << log_doorbell_bar_size) * 4096; 3893 var_table->stride_size = 1ULL << log_doorbell_stride; 3894 var_table->num_var_hw_entries = div_u64(bar_size, 3895 var_table->stride_size); 3896 mutex_init(&var_table->bitmap_lock); 3897 var_table->bitmap = bitmap_zalloc(var_table->num_var_hw_entries, 3898 GFP_KERNEL); 3899 return (var_table->bitmap) ? 0 : -ENOMEM; 3900} 3901 3902static void mlx5_ib_stage_caps_cleanup(struct mlx5_ib_dev *dev) 3903{ 3904 bitmap_free(dev->var_table.bitmap); 3905} 3906 3907static int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev) 3908{ 3909 struct mlx5_core_dev *mdev = dev->mdev; 3910 int err; 3911 3912 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) && 3913 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB)) 3914 ib_set_device_ops(&dev->ib_dev, 3915 &mlx5_ib_dev_ipoib_enhanced_ops); 3916 3917 if (mlx5_core_is_pf(mdev)) 3918 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_sriov_ops); 3919 3920 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence)); 3921 3922 if (MLX5_CAP_GEN(mdev, imaicl)) 3923 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_mw_ops); 3924 3925 if (MLX5_CAP_GEN(mdev, xrc)) 3926 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_xrc_ops); 3927 3928 if (MLX5_CAP_DEV_MEM(mdev, memic) || 3929 MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 3930 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM) 3931 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_dm_ops); 3932 3933 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_ops); 3934 3935 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)) 3936 dev->ib_dev.driver_def = mlx5_ib_defs; 3937 3938 err = init_node_data(dev); 3939 if (err) 3940 return err; 3941 3942 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) && 3943 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) || 3944 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc))) 3945 mutex_init(&dev->lb.mutex); 3946 3947 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) & 3948 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q) { 3949 err = mlx5_ib_init_var_table(dev); 3950 if (err) 3951 return err; 3952 } 3953 3954 dev->ib_dev.use_cq_dim = true; 3955 3956 return 0; 3957} 3958 3959static const struct ib_device_ops mlx5_ib_dev_port_ops = { 3960 .get_port_immutable = mlx5_port_immutable, 3961 .query_port = mlx5_ib_query_port, 3962}; 3963 3964static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev) 3965{ 3966 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_ops); 3967 return 0; 3968} 3969 3970static const struct ib_device_ops mlx5_ib_dev_port_rep_ops = { 3971 .get_port_immutable = mlx5_port_rep_immutable, 3972 .query_port = mlx5_ib_rep_query_port, 3973 .query_pkey = mlx5_ib_rep_query_pkey, 3974}; 3975 3976static int mlx5_ib_stage_raw_eth_non_default_cb(struct mlx5_ib_dev *dev) 3977{ 3978 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_port_rep_ops); 3979 return 0; 3980} 3981 3982static const struct ib_device_ops mlx5_ib_dev_common_roce_ops = { 3983 .create_rwq_ind_table = mlx5_ib_create_rwq_ind_table, 3984 .create_wq = mlx5_ib_create_wq, 3985 .destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table, 3986 .destroy_wq = mlx5_ib_destroy_wq, 3987 .get_netdev = mlx5_ib_get_netdev, 3988 .modify_wq = mlx5_ib_modify_wq, 3989 3990 INIT_RDMA_OBJ_SIZE(ib_rwq_ind_table, mlx5_ib_rwq_ind_table, 3991 ib_rwq_ind_tbl), 3992}; 3993 3994static int mlx5_ib_roce_init(struct mlx5_ib_dev *dev) 3995{ 3996 struct mlx5_core_dev *mdev = dev->mdev; 3997 enum rdma_link_layer ll; 3998 int port_type_cap; 3999 u32 port_num = 0; 4000 int err; 4001 4002 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4003 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4004 4005 if (ll == IB_LINK_LAYER_ETHERNET) { 4006 ib_set_device_ops(&dev->ib_dev, &mlx5_ib_dev_common_roce_ops); 4007 4008 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4009 4010 /* Register only for native ports */ 4011 mlx5_mdev_netdev_track(dev, port_num); 4012 4013 err = mlx5_enable_eth(dev); 4014 if (err) 4015 goto cleanup; 4016 } 4017 4018 return 0; 4019cleanup: 4020 mlx5_mdev_netdev_untrack(dev, port_num); 4021 return err; 4022} 4023 4024static void mlx5_ib_roce_cleanup(struct mlx5_ib_dev *dev) 4025{ 4026 struct mlx5_core_dev *mdev = dev->mdev; 4027 enum rdma_link_layer ll; 4028 int port_type_cap; 4029 u32 port_num; 4030 4031 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4032 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4033 4034 if (ll == IB_LINK_LAYER_ETHERNET) { 4035 mlx5_disable_eth(dev); 4036 4037 port_num = mlx5_core_native_port_num(dev->mdev) - 1; 4038 mlx5_mdev_netdev_untrack(dev, port_num); 4039 } 4040} 4041 4042static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev) 4043{ 4044 mlx5_ib_init_cong_debugfs(dev, 4045 mlx5_core_native_port_num(dev->mdev) - 1); 4046 return 0; 4047} 4048 4049static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev) 4050{ 4051 mlx5_ib_cleanup_cong_debugfs(dev, 4052 mlx5_core_native_port_num(dev->mdev) - 1); 4053} 4054 4055static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev) 4056{ 4057 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev); 4058 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar); 4059} 4060 4061static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev) 4062{ 4063 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar); 4064} 4065 4066static int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev) 4067{ 4068 int err; 4069 4070 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false); 4071 if (err) 4072 return err; 4073 4074 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true); 4075 if (err) 4076 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4077 4078 return err; 4079} 4080 4081static void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev) 4082{ 4083 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg); 4084 mlx5_free_bfreg(dev->mdev, &dev->bfreg); 4085} 4086 4087static int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev) 4088{ 4089 const char *name; 4090 4091 if (!mlx5_lag_is_active(dev->mdev)) 4092 name = "mlx5_%d"; 4093 else 4094 name = "mlx5_bond_%d"; 4095 return ib_register_device(&dev->ib_dev, name, &dev->mdev->pdev->dev); 4096} 4097 4098static void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev) 4099{ 4100 mlx5_mkey_cache_cleanup(dev); 4101 mlx5r_umr_resource_cleanup(dev); 4102} 4103 4104static void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev) 4105{ 4106 ib_unregister_device(&dev->ib_dev); 4107} 4108 4109static int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev) 4110{ 4111 int ret; 4112 4113 ret = mlx5r_umr_resource_init(dev); 4114 if (ret) 4115 return ret; 4116 4117 ret = mlx5_mkey_cache_init(dev); 4118 if (ret) 4119 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 4120 return ret; 4121} 4122 4123static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev) 4124{ 4125 struct dentry *root; 4126 4127 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4128 return 0; 4129 4130 mutex_init(&dev->delay_drop.lock); 4131 dev->delay_drop.dev = dev; 4132 dev->delay_drop.activate = false; 4133 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000; 4134 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler); 4135 atomic_set(&dev->delay_drop.rqs_cnt, 0); 4136 atomic_set(&dev->delay_drop.events_cnt, 0); 4137 4138 if (!mlx5_debugfs_root) 4139 return 0; 4140 4141 root = debugfs_create_dir("delay_drop", mlx5_debugfs_get_dev_root(dev->mdev)); 4142 dev->delay_drop.dir_debugfs = root; 4143 4144 debugfs_create_atomic_t("num_timeout_events", 0400, root, 4145 &dev->delay_drop.events_cnt); 4146 debugfs_create_atomic_t("num_rqs", 0400, root, 4147 &dev->delay_drop.rqs_cnt); 4148 debugfs_create_file("timeout", 0600, root, &dev->delay_drop, 4149 &fops_delay_drop_timeout); 4150 return 0; 4151} 4152 4153static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev) 4154{ 4155 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP)) 4156 return; 4157 4158 cancel_work_sync(&dev->delay_drop.delay_drop_work); 4159 if (!dev->delay_drop.dir_debugfs) 4160 return; 4161 4162 debugfs_remove_recursive(dev->delay_drop.dir_debugfs); 4163 dev->delay_drop.dir_debugfs = NULL; 4164} 4165 4166static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev *dev) 4167{ 4168 dev->mdev_events.notifier_call = mlx5_ib_event; 4169 mlx5_notifier_register(dev->mdev, &dev->mdev_events); 4170 4171 mlx5r_macsec_event_register(dev); 4172 4173 return 0; 4174} 4175 4176static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev *dev) 4177{ 4178 mlx5r_macsec_event_unregister(dev); 4179 mlx5_notifier_unregister(dev->mdev, &dev->mdev_events); 4180} 4181 4182void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 4183 const struct mlx5_ib_profile *profile, 4184 int stage) 4185{ 4186 dev->ib_active = false; 4187 4188 /* Number of stages to cleanup */ 4189 while (stage) { 4190 stage--; 4191 if (profile->stage[stage].cleanup) 4192 profile->stage[stage].cleanup(dev); 4193 } 4194 4195 kfree(dev->port); 4196 ib_dealloc_device(&dev->ib_dev); 4197} 4198 4199int __mlx5_ib_add(struct mlx5_ib_dev *dev, 4200 const struct mlx5_ib_profile *profile) 4201{ 4202 int err; 4203 int i; 4204 4205 dev->profile = profile; 4206 4207 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) { 4208 if (profile->stage[i].init) { 4209 err = profile->stage[i].init(dev); 4210 if (err) 4211 goto err_out; 4212 } 4213 } 4214 4215 dev->ib_active = true; 4216 return 0; 4217 4218err_out: 4219 /* Clean up stages which were initialized */ 4220 while (i) { 4221 i--; 4222 if (profile->stage[i].cleanup) 4223 profile->stage[i].cleanup(dev); 4224 } 4225 return -ENOMEM; 4226} 4227 4228static const struct mlx5_ib_profile pf_profile = { 4229 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4230 mlx5_ib_stage_init_init, 4231 mlx5_ib_stage_init_cleanup), 4232 STAGE_CREATE(MLX5_IB_STAGE_FS, 4233 mlx5_ib_fs_init, 4234 mlx5_ib_fs_cleanup), 4235 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4236 mlx5_ib_stage_caps_init, 4237 mlx5_ib_stage_caps_cleanup), 4238 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4239 mlx5_ib_stage_non_default_cb, 4240 NULL), 4241 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 4242 mlx5_ib_roce_init, 4243 mlx5_ib_roce_cleanup), 4244 STAGE_CREATE(MLX5_IB_STAGE_QP, 4245 mlx5_init_qp_table, 4246 mlx5_cleanup_qp_table), 4247 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4248 mlx5_init_srq_table, 4249 mlx5_cleanup_srq_table), 4250 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4251 mlx5_ib_dev_res_init, 4252 mlx5_ib_dev_res_cleanup), 4253 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 4254 mlx5_ib_stage_dev_notifier_init, 4255 mlx5_ib_stage_dev_notifier_cleanup), 4256 STAGE_CREATE(MLX5_IB_STAGE_ODP, 4257 mlx5_ib_odp_init_one, 4258 mlx5_ib_odp_cleanup_one), 4259 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 4260 mlx5_ib_counters_init, 4261 mlx5_ib_counters_cleanup), 4262 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 4263 mlx5_ib_stage_cong_debugfs_init, 4264 mlx5_ib_stage_cong_debugfs_cleanup), 4265 STAGE_CREATE(MLX5_IB_STAGE_UAR, 4266 mlx5_ib_stage_uar_init, 4267 mlx5_ib_stage_uar_cleanup), 4268 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4269 mlx5_ib_stage_bfrag_init, 4270 mlx5_ib_stage_bfrag_cleanup), 4271 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 4272 NULL, 4273 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 4274 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 4275 mlx5_ib_devx_init, 4276 mlx5_ib_devx_cleanup), 4277 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4278 mlx5_ib_stage_ib_reg_init, 4279 mlx5_ib_stage_ib_reg_cleanup), 4280 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 4281 mlx5_ib_stage_post_ib_reg_umr_init, 4282 NULL), 4283 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 4284 mlx5_ib_stage_delay_drop_init, 4285 mlx5_ib_stage_delay_drop_cleanup), 4286 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 4287 mlx5_ib_restrack_init, 4288 NULL), 4289}; 4290 4291const struct mlx5_ib_profile raw_eth_profile = { 4292 STAGE_CREATE(MLX5_IB_STAGE_INIT, 4293 mlx5_ib_stage_init_init, 4294 mlx5_ib_stage_init_cleanup), 4295 STAGE_CREATE(MLX5_IB_STAGE_FS, 4296 mlx5_ib_fs_init, 4297 mlx5_ib_fs_cleanup), 4298 STAGE_CREATE(MLX5_IB_STAGE_CAPS, 4299 mlx5_ib_stage_caps_init, 4300 mlx5_ib_stage_caps_cleanup), 4301 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB, 4302 mlx5_ib_stage_raw_eth_non_default_cb, 4303 NULL), 4304 STAGE_CREATE(MLX5_IB_STAGE_ROCE, 4305 mlx5_ib_roce_init, 4306 mlx5_ib_roce_cleanup), 4307 STAGE_CREATE(MLX5_IB_STAGE_QP, 4308 mlx5_init_qp_table, 4309 mlx5_cleanup_qp_table), 4310 STAGE_CREATE(MLX5_IB_STAGE_SRQ, 4311 mlx5_init_srq_table, 4312 mlx5_cleanup_srq_table), 4313 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES, 4314 mlx5_ib_dev_res_init, 4315 mlx5_ib_dev_res_cleanup), 4316 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER, 4317 mlx5_ib_stage_dev_notifier_init, 4318 mlx5_ib_stage_dev_notifier_cleanup), 4319 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS, 4320 mlx5_ib_counters_init, 4321 mlx5_ib_counters_cleanup), 4322 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS, 4323 mlx5_ib_stage_cong_debugfs_init, 4324 mlx5_ib_stage_cong_debugfs_cleanup), 4325 STAGE_CREATE(MLX5_IB_STAGE_UAR, 4326 mlx5_ib_stage_uar_init, 4327 mlx5_ib_stage_uar_cleanup), 4328 STAGE_CREATE(MLX5_IB_STAGE_BFREG, 4329 mlx5_ib_stage_bfrag_init, 4330 mlx5_ib_stage_bfrag_cleanup), 4331 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR, 4332 NULL, 4333 mlx5_ib_stage_pre_ib_reg_umr_cleanup), 4334 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID, 4335 mlx5_ib_devx_init, 4336 mlx5_ib_devx_cleanup), 4337 STAGE_CREATE(MLX5_IB_STAGE_IB_REG, 4338 mlx5_ib_stage_ib_reg_init, 4339 mlx5_ib_stage_ib_reg_cleanup), 4340 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR, 4341 mlx5_ib_stage_post_ib_reg_umr_init, 4342 NULL), 4343 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP, 4344 mlx5_ib_stage_delay_drop_init, 4345 mlx5_ib_stage_delay_drop_cleanup), 4346 STAGE_CREATE(MLX5_IB_STAGE_RESTRACK, 4347 mlx5_ib_restrack_init, 4348 NULL), 4349}; 4350 4351static int mlx5r_mp_probe(struct auxiliary_device *adev, 4352 const struct auxiliary_device_id *id) 4353{ 4354 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 4355 struct mlx5_core_dev *mdev = idev->mdev; 4356 struct mlx5_ib_multiport_info *mpi; 4357 struct mlx5_ib_dev *dev; 4358 bool bound = false; 4359 int err; 4360 4361 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL); 4362 if (!mpi) 4363 return -ENOMEM; 4364 4365 mpi->mdev = mdev; 4366 err = mlx5_query_nic_vport_system_image_guid(mdev, 4367 &mpi->sys_image_guid); 4368 if (err) { 4369 kfree(mpi); 4370 return err; 4371 } 4372 4373 mutex_lock(&mlx5_ib_multiport_mutex); 4374 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) { 4375 if (dev->sys_image_guid == mpi->sys_image_guid) 4376 bound = mlx5_ib_bind_slave_port(dev, mpi); 4377 4378 if (bound) { 4379 rdma_roce_rescan_device(&dev->ib_dev); 4380 mpi->ibdev->ib_active = true; 4381 break; 4382 } 4383 } 4384 4385 if (!bound) { 4386 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list); 4387 dev_dbg(mdev->device, 4388 "no suitable IB device found to bind to, added to unaffiliated list.\n"); 4389 } 4390 mutex_unlock(&mlx5_ib_multiport_mutex); 4391 4392 auxiliary_set_drvdata(adev, mpi); 4393 return 0; 4394} 4395 4396static void mlx5r_mp_remove(struct auxiliary_device *adev) 4397{ 4398 struct mlx5_ib_multiport_info *mpi; 4399 4400 mpi = auxiliary_get_drvdata(adev); 4401 mutex_lock(&mlx5_ib_multiport_mutex); 4402 if (mpi->ibdev) 4403 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi); 4404 else 4405 list_del(&mpi->list); 4406 mutex_unlock(&mlx5_ib_multiport_mutex); 4407 kfree(mpi); 4408} 4409 4410static int mlx5r_probe(struct auxiliary_device *adev, 4411 const struct auxiliary_device_id *id) 4412{ 4413 struct mlx5_adev *idev = container_of(adev, struct mlx5_adev, adev); 4414 struct mlx5_core_dev *mdev = idev->mdev; 4415 const struct mlx5_ib_profile *profile; 4416 int port_type_cap, num_ports, ret; 4417 enum rdma_link_layer ll; 4418 struct mlx5_ib_dev *dev; 4419 4420 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 4421 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 4422 4423 num_ports = max(MLX5_CAP_GEN(mdev, num_ports), 4424 MLX5_CAP_GEN(mdev, num_vhca_ports)); 4425 dev = ib_alloc_device(mlx5_ib_dev, ib_dev); 4426 if (!dev) 4427 return -ENOMEM; 4428 dev->port = kcalloc(num_ports, sizeof(*dev->port), 4429 GFP_KERNEL); 4430 if (!dev->port) { 4431 ib_dealloc_device(&dev->ib_dev); 4432 return -ENOMEM; 4433 } 4434 4435 dev->mdev = mdev; 4436 dev->num_ports = num_ports; 4437 4438 if (ll == IB_LINK_LAYER_ETHERNET && !mlx5_get_roce_state(mdev)) 4439 profile = &raw_eth_profile; 4440 else 4441 profile = &pf_profile; 4442 4443 ret = __mlx5_ib_add(dev, profile); 4444 if (ret) { 4445 kfree(dev->port); 4446 ib_dealloc_device(&dev->ib_dev); 4447 return ret; 4448 } 4449 4450 auxiliary_set_drvdata(adev, dev); 4451 return 0; 4452} 4453 4454static void mlx5r_remove(struct auxiliary_device *adev) 4455{ 4456 struct mlx5_ib_dev *dev; 4457 4458 dev = auxiliary_get_drvdata(adev); 4459 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX); 4460} 4461 4462static const struct auxiliary_device_id mlx5r_mp_id_table[] = { 4463 { .name = MLX5_ADEV_NAME ".multiport", }, 4464 {}, 4465}; 4466 4467static const struct auxiliary_device_id mlx5r_id_table[] = { 4468 { .name = MLX5_ADEV_NAME ".rdma", }, 4469 {}, 4470}; 4471 4472MODULE_DEVICE_TABLE(auxiliary, mlx5r_mp_id_table); 4473MODULE_DEVICE_TABLE(auxiliary, mlx5r_id_table); 4474 4475static struct auxiliary_driver mlx5r_mp_driver = { 4476 .name = "multiport", 4477 .probe = mlx5r_mp_probe, 4478 .remove = mlx5r_mp_remove, 4479 .id_table = mlx5r_mp_id_table, 4480}; 4481 4482static struct auxiliary_driver mlx5r_driver = { 4483 .name = "rdma", 4484 .probe = mlx5r_probe, 4485 .remove = mlx5r_remove, 4486 .id_table = mlx5r_id_table, 4487}; 4488 4489static int __init mlx5_ib_init(void) 4490{ 4491 int ret; 4492 4493 xlt_emergency_page = (void *)__get_free_page(GFP_KERNEL); 4494 if (!xlt_emergency_page) 4495 return -ENOMEM; 4496 4497 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0); 4498 if (!mlx5_ib_event_wq) { 4499 free_page((unsigned long)xlt_emergency_page); 4500 return -ENOMEM; 4501 } 4502 4503 ret = mlx5_ib_qp_event_init(); 4504 if (ret) 4505 goto qp_event_err; 4506 4507 mlx5_ib_odp_init(); 4508 ret = mlx5r_rep_init(); 4509 if (ret) 4510 goto rep_err; 4511 ret = auxiliary_driver_register(&mlx5r_mp_driver); 4512 if (ret) 4513 goto mp_err; 4514 ret = auxiliary_driver_register(&mlx5r_driver); 4515 if (ret) 4516 goto drv_err; 4517 return 0; 4518 4519drv_err: 4520 auxiliary_driver_unregister(&mlx5r_mp_driver); 4521mp_err: 4522 mlx5r_rep_cleanup(); 4523rep_err: 4524 mlx5_ib_qp_event_cleanup(); 4525qp_event_err: 4526 destroy_workqueue(mlx5_ib_event_wq); 4527 free_page((unsigned long)xlt_emergency_page); 4528 return ret; 4529} 4530 4531static void __exit mlx5_ib_cleanup(void) 4532{ 4533 auxiliary_driver_unregister(&mlx5r_driver); 4534 auxiliary_driver_unregister(&mlx5r_mp_driver); 4535 mlx5r_rep_cleanup(); 4536 4537 mlx5_ib_qp_event_cleanup(); 4538 destroy_workqueue(mlx5_ib_event_wq); 4539 free_page((unsigned long)xlt_emergency_page); 4540} 4541 4542module_init(mlx5_ib_init); 4543module_exit(mlx5_ib_cleanup); 4544