1/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ 2/* Copyright (c) 2023 Imagination Technologies Ltd. */ 3 4#ifndef PVR_ROGUE_FWIF_COMMON_H 5#define PVR_ROGUE_FWIF_COMMON_H 6 7#include <linux/build_bug.h> 8 9/* 10 * This macro represents a mask of LSBs that must be zero on data structure 11 * sizes and offsets to ensure they are 8-byte granular on types shared between 12 * the FW and host driver. 13 */ 14#define PVR_FW_ALIGNMENT_LSB 7U 15 16/* Macro to test structure size alignment. */ 17#define PVR_FW_STRUCT_SIZE_ASSERT(_a) \ 18 static_assert((sizeof(_a) & PVR_FW_ALIGNMENT_LSB) == 0U, \ 19 "Size of " #_a " is not properly aligned") 20 21/* The master definition for data masters known to the firmware. */ 22 23#define PVR_FWIF_DM_GP (0) 24/* Either TDM or 2D DM is present. */ 25/* When the 'tla' feature is present in the hw (as per @pvr_device_features). */ 26#define PVR_FWIF_DM_2D (1) 27/* 28 * When the 'fastrender_dm' feature is present in the hw (as per 29 * @pvr_device_features). 30 */ 31#define PVR_FWIF_DM_TDM (1) 32 33#define PVR_FWIF_DM_GEOM (2) 34#define PVR_FWIF_DM_FRAG (3) 35#define PVR_FWIF_DM_CDM (4) 36#define PVR_FWIF_DM_RAY (5) 37#define PVR_FWIF_DM_GEOM2 (6) 38#define PVR_FWIF_DM_GEOM3 (7) 39#define PVR_FWIF_DM_GEOM4 (8) 40 41#define PVR_FWIF_DM_LAST PVR_FWIF_DM_GEOM4 42 43/* Maximum number of DM in use: GP, 2D/TDM, GEOM, 3D, CDM, RAY, GEOM2, GEOM3, GEOM4 */ 44#define PVR_FWIF_DM_MAX (PVR_FWIF_DM_LAST + 1U) 45 46/* GPU Utilisation states */ 47#define PVR_FWIF_GPU_UTIL_STATE_IDLE 0U 48#define PVR_FWIF_GPU_UTIL_STATE_ACTIVE 1U 49#define PVR_FWIF_GPU_UTIL_STATE_BLOCKED 2U 50#define PVR_FWIF_GPU_UTIL_STATE_NUM 3U 51#define PVR_FWIF_GPU_UTIL_STATE_MASK 0x3ULL 52 53/* 54 * Maximum amount of register writes that can be done by the register 55 * programmer (FW or META DMA). This is not a HW limitation, it is only 56 * a protection against malformed inputs to the register programmer. 57 */ 58#define PVR_MAX_NUM_REGISTER_PROGRAMMER_WRITES 128U 59 60#endif /* PVR_ROGUE_FWIF_COMMON_H */ 61