1/* 2 * Copyright �� 2013 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24#include <drm/drm_managed.h> 25#include <linux/pm_runtime.h> 26 27#include "gt/intel_engine_regs.h" 28#include "gt/intel_gt_regs.h" 29 30#include "i915_drv.h" 31#include "i915_iosf_mbi.h" 32#include "i915_reg.h" 33#include "i915_trace.h" 34#include "i915_vgpu.h" 35 36#define FORCEWAKE_ACK_TIMEOUT_MS 50 37#define GT_FIFO_TIMEOUT_MS 10 38 39#define __raw_posting_read(...) ((void)__raw_uncore_read32(__VA_ARGS__)) 40 41static void 42fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains) 43{ 44 uncore->fw_get_funcs->force_wake_get(uncore, fw_domains); 45} 46 47void 48intel_uncore_mmio_debug_init_early(struct drm_i915_private *i915) 49{ 50 spin_lock_init(&i915->mmio_debug.lock); 51 i915->mmio_debug.unclaimed_mmio_check = 1; 52 53 i915->uncore.debug = &i915->mmio_debug; 54} 55 56static void mmio_debug_suspend(struct intel_uncore *uncore) 57{ 58 if (!uncore->debug) 59 return; 60 61 spin_lock(&uncore->debug->lock); 62 63 /* Save and disable mmio debugging for the user bypass */ 64 if (!uncore->debug->suspend_count++) { 65 uncore->debug->saved_mmio_check = uncore->debug->unclaimed_mmio_check; 66 uncore->debug->unclaimed_mmio_check = 0; 67 } 68 69 spin_unlock(&uncore->debug->lock); 70} 71 72static bool check_for_unclaimed_mmio(struct intel_uncore *uncore); 73 74static void mmio_debug_resume(struct intel_uncore *uncore) 75{ 76 if (!uncore->debug) 77 return; 78 79 spin_lock(&uncore->debug->lock); 80 81 if (!--uncore->debug->suspend_count) 82 uncore->debug->unclaimed_mmio_check = uncore->debug->saved_mmio_check; 83 84 if (check_for_unclaimed_mmio(uncore)) 85 drm_info(&uncore->i915->drm, 86 "Invalid mmio detected during user access\n"); 87 88 spin_unlock(&uncore->debug->lock); 89} 90 91static const char * const forcewake_domain_names[] = { 92 "render", 93 "gt", 94 "media", 95 "vdbox0", 96 "vdbox1", 97 "vdbox2", 98 "vdbox3", 99 "vdbox4", 100 "vdbox5", 101 "vdbox6", 102 "vdbox7", 103 "vebox0", 104 "vebox1", 105 "vebox2", 106 "vebox3", 107 "gsc", 108}; 109 110const char * 111intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id) 112{ 113 BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT); 114 115 if (id >= 0 && id < FW_DOMAIN_ID_COUNT) 116 return forcewake_domain_names[id]; 117 118 WARN_ON(id); 119 120 return "unknown"; 121} 122 123#define fw_ack(d) readl((d)->reg_ack) 124#define fw_set(d, val) writel(_MASKED_BIT_ENABLE((val)), (d)->reg_set) 125#define fw_clear(d, val) writel(_MASKED_BIT_DISABLE((val)), (d)->reg_set) 126 127static inline void 128fw_domain_reset(const struct intel_uncore_forcewake_domain *d) 129{ 130 /* 131 * We don't really know if the powerwell for the forcewake domain we are 132 * trying to reset here does exist at this point (engines could be fused 133 * off in ICL+), so no waiting for acks 134 */ 135 /* WaRsClearFWBitsAtReset */ 136 if (GRAPHICS_VER(d->uncore->i915) >= 12) 137 fw_clear(d, 0xefff); 138 else 139 fw_clear(d, 0xffff); 140} 141 142static inline void 143fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d) 144{ 145 GEM_BUG_ON(d->uncore->fw_domains_timer & d->mask); 146 d->uncore->fw_domains_timer |= d->mask; 147 d->wake_count++; 148 hrtimer_start_range_ns(&d->timer, 149 NSEC_PER_MSEC, 150 NSEC_PER_MSEC, 151 HRTIMER_MODE_REL); 152} 153 154static inline int 155__wait_for_ack(const struct intel_uncore_forcewake_domain *d, 156 const u32 ack, 157 const u32 value) 158{ 159 return wait_for_atomic((fw_ack(d) & ack) == value, 160 FORCEWAKE_ACK_TIMEOUT_MS); 161} 162 163static inline int 164wait_ack_clear(const struct intel_uncore_forcewake_domain *d, 165 const u32 ack) 166{ 167 return __wait_for_ack(d, ack, 0); 168} 169 170static inline int 171wait_ack_set(const struct intel_uncore_forcewake_domain *d, 172 const u32 ack) 173{ 174 return __wait_for_ack(d, ack, ack); 175} 176 177static inline void 178fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d) 179{ 180 if (!wait_ack_clear(d, FORCEWAKE_KERNEL)) 181 return; 182 183 if (fw_ack(d) == ~0) 184 drm_err(&d->uncore->i915->drm, 185 "%s: MMIO unreliable (forcewake register returns 0xFFFFFFFF)!\n", 186 intel_uncore_forcewake_domain_to_str(d->id)); 187 else 188 drm_err(&d->uncore->i915->drm, 189 "%s: timed out waiting for forcewake ack to clear.\n", 190 intel_uncore_forcewake_domain_to_str(d->id)); 191 192 add_taint_for_CI(d->uncore->i915, TAINT_WARN); /* CI now unreliable */ 193} 194 195enum ack_type { 196 ACK_CLEAR = 0, 197 ACK_SET 198}; 199 200static int 201fw_domain_wait_ack_with_fallback(const struct intel_uncore_forcewake_domain *d, 202 const enum ack_type type) 203{ 204 const u32 ack_bit = FORCEWAKE_KERNEL; 205 const u32 value = type == ACK_SET ? ack_bit : 0; 206 unsigned int pass; 207 bool ack_detected; 208 209 /* 210 * There is a possibility of driver's wake request colliding 211 * with hardware's own wake requests and that can cause 212 * hardware to not deliver the driver's ack message. 213 * 214 * Use a fallback bit toggle to kick the gpu state machine 215 * in the hope that the original ack will be delivered along with 216 * the fallback ack. 217 * 218 * This workaround is described in HSDES #1604254524 and it's known as: 219 * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl 220 * although the name is a bit misleading. 221 */ 222 223 pass = 1; 224 do { 225 wait_ack_clear(d, FORCEWAKE_KERNEL_FALLBACK); 226 227 fw_set(d, FORCEWAKE_KERNEL_FALLBACK); 228 /* Give gt some time to relax before the polling frenzy */ 229 udelay(10 * pass); 230 wait_ack_set(d, FORCEWAKE_KERNEL_FALLBACK); 231 232 ack_detected = (fw_ack(d) & ack_bit) == value; 233 234 fw_clear(d, FORCEWAKE_KERNEL_FALLBACK); 235 } while (!ack_detected && pass++ < 10); 236 237 drm_dbg(&d->uncore->i915->drm, 238 "%s had to use fallback to %s ack, 0x%x (passes %u)\n", 239 intel_uncore_forcewake_domain_to_str(d->id), 240 type == ACK_SET ? "set" : "clear", 241 fw_ack(d), 242 pass); 243 244 return ack_detected ? 0 : -ETIMEDOUT; 245} 246 247static inline void 248fw_domain_wait_ack_clear_fallback(const struct intel_uncore_forcewake_domain *d) 249{ 250 if (likely(!wait_ack_clear(d, FORCEWAKE_KERNEL))) 251 return; 252 253 if (fw_domain_wait_ack_with_fallback(d, ACK_CLEAR)) 254 fw_domain_wait_ack_clear(d); 255} 256 257static inline void 258fw_domain_get(const struct intel_uncore_forcewake_domain *d) 259{ 260 fw_set(d, FORCEWAKE_KERNEL); 261} 262 263static inline void 264fw_domain_wait_ack_set(const struct intel_uncore_forcewake_domain *d) 265{ 266 if (wait_ack_set(d, FORCEWAKE_KERNEL)) { 267 drm_err(&d->uncore->i915->drm, 268 "%s: timed out waiting for forcewake ack request.\n", 269 intel_uncore_forcewake_domain_to_str(d->id)); 270 add_taint_for_CI(d->uncore->i915, TAINT_WARN); /* CI now unreliable */ 271 } 272} 273 274static inline void 275fw_domain_wait_ack_set_fallback(const struct intel_uncore_forcewake_domain *d) 276{ 277 if (likely(!wait_ack_set(d, FORCEWAKE_KERNEL))) 278 return; 279 280 if (fw_domain_wait_ack_with_fallback(d, ACK_SET)) 281 fw_domain_wait_ack_set(d); 282} 283 284static inline void 285fw_domain_put(const struct intel_uncore_forcewake_domain *d) 286{ 287 fw_clear(d, FORCEWAKE_KERNEL); 288} 289 290static void 291fw_domains_get_normal(struct intel_uncore *uncore, enum forcewake_domains fw_domains) 292{ 293 struct intel_uncore_forcewake_domain *d; 294 unsigned int tmp; 295 296 GEM_BUG_ON(fw_domains & ~uncore->fw_domains); 297 298 for_each_fw_domain_masked(d, fw_domains, uncore, tmp) { 299 fw_domain_wait_ack_clear(d); 300 fw_domain_get(d); 301 } 302 303 for_each_fw_domain_masked(d, fw_domains, uncore, tmp) 304 fw_domain_wait_ack_set(d); 305 306 uncore->fw_domains_active |= fw_domains; 307} 308 309static void 310fw_domains_get_with_fallback(struct intel_uncore *uncore, 311 enum forcewake_domains fw_domains) 312{ 313 struct intel_uncore_forcewake_domain *d; 314 unsigned int tmp; 315 316 GEM_BUG_ON(fw_domains & ~uncore->fw_domains); 317 318 for_each_fw_domain_masked(d, fw_domains, uncore, tmp) { 319 fw_domain_wait_ack_clear_fallback(d); 320 fw_domain_get(d); 321 } 322 323 for_each_fw_domain_masked(d, fw_domains, uncore, tmp) 324 fw_domain_wait_ack_set_fallback(d); 325 326 uncore->fw_domains_active |= fw_domains; 327} 328 329static void 330fw_domains_put(struct intel_uncore *uncore, enum forcewake_domains fw_domains) 331{ 332 struct intel_uncore_forcewake_domain *d; 333 unsigned int tmp; 334 335 GEM_BUG_ON(fw_domains & ~uncore->fw_domains); 336 337 for_each_fw_domain_masked(d, fw_domains, uncore, tmp) 338 fw_domain_put(d); 339 340 uncore->fw_domains_active &= ~fw_domains; 341} 342 343static void 344fw_domains_reset(struct intel_uncore *uncore, 345 enum forcewake_domains fw_domains) 346{ 347 struct intel_uncore_forcewake_domain *d; 348 unsigned int tmp; 349 350 if (!fw_domains) 351 return; 352 353 GEM_BUG_ON(fw_domains & ~uncore->fw_domains); 354 355 for_each_fw_domain_masked(d, fw_domains, uncore, tmp) 356 fw_domain_reset(d); 357} 358 359static inline u32 gt_thread_status(struct intel_uncore *uncore) 360{ 361 u32 val; 362 363 val = __raw_uncore_read32(uncore, GEN6_GT_THREAD_STATUS_REG); 364 val &= GEN6_GT_THREAD_STATUS_CORE_MASK; 365 366 return val; 367} 368 369static void __gen6_gt_wait_for_thread_c0(struct intel_uncore *uncore) 370{ 371 /* 372 * w/a for a sporadic read returning 0 by waiting for the GT 373 * thread to wake up. 374 */ 375 drm_WARN_ONCE(&uncore->i915->drm, 376 wait_for_atomic_us(gt_thread_status(uncore) == 0, 5000), 377 "GT thread status wait timed out\n"); 378} 379 380static void fw_domains_get_with_thread_status(struct intel_uncore *uncore, 381 enum forcewake_domains fw_domains) 382{ 383 fw_domains_get_normal(uncore, fw_domains); 384 385 /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */ 386 __gen6_gt_wait_for_thread_c0(uncore); 387} 388 389static inline u32 fifo_free_entries(struct intel_uncore *uncore) 390{ 391 u32 count = __raw_uncore_read32(uncore, GTFIFOCTL); 392 393 return count & GT_FIFO_FREE_ENTRIES_MASK; 394} 395 396static void __gen6_gt_wait_for_fifo(struct intel_uncore *uncore) 397{ 398 u32 n; 399 400 /* On VLV, FIFO will be shared by both SW and HW. 401 * So, we need to read the FREE_ENTRIES everytime */ 402 if (IS_VALLEYVIEW(uncore->i915)) 403 n = fifo_free_entries(uncore); 404 else 405 n = uncore->fifo_count; 406 407 if (n <= GT_FIFO_NUM_RESERVED_ENTRIES) { 408 if (wait_for_atomic((n = fifo_free_entries(uncore)) > 409 GT_FIFO_NUM_RESERVED_ENTRIES, 410 GT_FIFO_TIMEOUT_MS)) { 411 drm_dbg(&uncore->i915->drm, 412 "GT_FIFO timeout, entries: %u\n", n); 413 return; 414 } 415 } 416 417 uncore->fifo_count = n - 1; 418} 419 420static enum hrtimer_restart 421intel_uncore_fw_release_timer(struct hrtimer *timer) 422{ 423 struct intel_uncore_forcewake_domain *domain = 424 container_of(timer, struct intel_uncore_forcewake_domain, timer); 425 struct intel_uncore *uncore = domain->uncore; 426 unsigned long irqflags; 427 428 assert_rpm_device_not_suspended(uncore->rpm); 429 430 if (xchg(&domain->active, false)) 431 return HRTIMER_RESTART; 432 433 spin_lock_irqsave(&uncore->lock, irqflags); 434 435 uncore->fw_domains_timer &= ~domain->mask; 436 437 GEM_BUG_ON(!domain->wake_count); 438 if (--domain->wake_count == 0) 439 fw_domains_put(uncore, domain->mask); 440 441 spin_unlock_irqrestore(&uncore->lock, irqflags); 442 443 return HRTIMER_NORESTART; 444} 445 446/* Note callers must have acquired the PUNIT->PMIC bus, before calling this. */ 447static unsigned int 448intel_uncore_forcewake_reset(struct intel_uncore *uncore) 449{ 450 unsigned long irqflags; 451 struct intel_uncore_forcewake_domain *domain; 452 int retry_count = 100; 453 enum forcewake_domains fw, active_domains; 454 455 iosf_mbi_assert_punit_acquired(); 456 457 /* Hold uncore.lock across reset to prevent any register access 458 * with forcewake not set correctly. Wait until all pending 459 * timers are run before holding. 460 */ 461 while (1) { 462 unsigned int tmp; 463 464 active_domains = 0; 465 466 for_each_fw_domain(domain, uncore, tmp) { 467 smp_store_mb(domain->active, false); 468 if (hrtimer_cancel(&domain->timer) == 0) 469 continue; 470 471 intel_uncore_fw_release_timer(&domain->timer); 472 } 473 474 spin_lock_irqsave(&uncore->lock, irqflags); 475 476 for_each_fw_domain(domain, uncore, tmp) { 477 if (hrtimer_active(&domain->timer)) 478 active_domains |= domain->mask; 479 } 480 481 if (active_domains == 0) 482 break; 483 484 if (--retry_count == 0) { 485 drm_err(&uncore->i915->drm, "Timed out waiting for forcewake timers to finish\n"); 486 break; 487 } 488 489 spin_unlock_irqrestore(&uncore->lock, irqflags); 490 cond_resched(); 491 } 492 493 drm_WARN_ON(&uncore->i915->drm, active_domains); 494 495 fw = uncore->fw_domains_active; 496 if (fw) 497 fw_domains_put(uncore, fw); 498 499 fw_domains_reset(uncore, uncore->fw_domains); 500 assert_forcewakes_inactive(uncore); 501 502 spin_unlock_irqrestore(&uncore->lock, irqflags); 503 504 return fw; /* track the lost user forcewake domains */ 505} 506 507static bool 508fpga_check_for_unclaimed_mmio(struct intel_uncore *uncore) 509{ 510 u32 dbg; 511 512 dbg = __raw_uncore_read32(uncore, FPGA_DBG); 513 if (likely(!(dbg & FPGA_DBG_RM_NOCLAIM))) 514 return false; 515 516 /* 517 * Bugs in PCI programming (or failing hardware) can occasionally cause 518 * us to lose access to the MMIO BAR. When this happens, register 519 * reads will come back with 0xFFFFFFFF for every register and things 520 * go bad very quickly. Let's try to detect that special case and at 521 * least try to print a more informative message about what has 522 * happened. 523 * 524 * During normal operation the FPGA_DBG register has several unused 525 * bits that will always read back as 0's so we can use them as canaries 526 * to recognize when MMIO accesses are just busted. 527 */ 528 if (unlikely(dbg == ~0)) 529 drm_err(&uncore->i915->drm, 530 "Lost access to MMIO BAR; all registers now read back as 0xFFFFFFFF!\n"); 531 532 __raw_uncore_write32(uncore, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); 533 534 return true; 535} 536 537static bool 538vlv_check_for_unclaimed_mmio(struct intel_uncore *uncore) 539{ 540 u32 cer; 541 542 cer = __raw_uncore_read32(uncore, CLAIM_ER); 543 if (likely(!(cer & (CLAIM_ER_OVERFLOW | CLAIM_ER_CTR_MASK)))) 544 return false; 545 546 __raw_uncore_write32(uncore, CLAIM_ER, CLAIM_ER_CLR); 547 548 return true; 549} 550 551static bool 552gen6_check_for_fifo_debug(struct intel_uncore *uncore) 553{ 554 u32 fifodbg; 555 556 fifodbg = __raw_uncore_read32(uncore, GTFIFODBG); 557 558 if (unlikely(fifodbg)) { 559 drm_dbg(&uncore->i915->drm, "GTFIFODBG = 0x08%x\n", fifodbg); 560 __raw_uncore_write32(uncore, GTFIFODBG, fifodbg); 561 } 562 563 return fifodbg; 564} 565 566static bool 567check_for_unclaimed_mmio(struct intel_uncore *uncore) 568{ 569 bool ret = false; 570 571 lockdep_assert_held(&uncore->debug->lock); 572 573 if (uncore->debug->suspend_count) 574 return false; 575 576 if (intel_uncore_has_fpga_dbg_unclaimed(uncore)) 577 ret |= fpga_check_for_unclaimed_mmio(uncore); 578 579 if (intel_uncore_has_dbg_unclaimed(uncore)) 580 ret |= vlv_check_for_unclaimed_mmio(uncore); 581 582 if (intel_uncore_has_fifo(uncore)) 583 ret |= gen6_check_for_fifo_debug(uncore); 584 585 return ret; 586} 587 588static void forcewake_early_sanitize(struct intel_uncore *uncore, 589 unsigned int restore_forcewake) 590{ 591 GEM_BUG_ON(!intel_uncore_has_forcewake(uncore)); 592 593 /* WaDisableShadowRegForCpd:chv */ 594 if (IS_CHERRYVIEW(uncore->i915)) { 595 __raw_uncore_write32(uncore, GTFIFOCTL, 596 __raw_uncore_read32(uncore, GTFIFOCTL) | 597 GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL | 598 GT_FIFO_CTL_RC6_POLICY_STALL); 599 } 600 601 iosf_mbi_punit_acquire(); 602 intel_uncore_forcewake_reset(uncore); 603 if (restore_forcewake) { 604 spin_lock_irq(&uncore->lock); 605 fw_domains_get(uncore, restore_forcewake); 606 607 if (intel_uncore_has_fifo(uncore)) 608 uncore->fifo_count = fifo_free_entries(uncore); 609 spin_unlock_irq(&uncore->lock); 610 } 611 iosf_mbi_punit_release(); 612} 613 614void intel_uncore_suspend(struct intel_uncore *uncore) 615{ 616 if (!intel_uncore_has_forcewake(uncore)) 617 return; 618 619 iosf_mbi_punit_acquire(); 620 iosf_mbi_unregister_pmic_bus_access_notifier_unlocked( 621 &uncore->pmic_bus_access_nb); 622 uncore->fw_domains_saved = intel_uncore_forcewake_reset(uncore); 623 iosf_mbi_punit_release(); 624} 625 626void intel_uncore_resume_early(struct intel_uncore *uncore) 627{ 628 unsigned int restore_forcewake; 629 630 if (intel_uncore_unclaimed_mmio(uncore)) 631 drm_dbg(&uncore->i915->drm, "unclaimed mmio detected on resume, clearing\n"); 632 633 if (!intel_uncore_has_forcewake(uncore)) 634 return; 635 636 restore_forcewake = fetch_and_zero(&uncore->fw_domains_saved); 637 forcewake_early_sanitize(uncore, restore_forcewake); 638 639 iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb); 640} 641 642void intel_uncore_runtime_resume(struct intel_uncore *uncore) 643{ 644 if (!intel_uncore_has_forcewake(uncore)) 645 return; 646 647 iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb); 648} 649 650static void __intel_uncore_forcewake_get(struct intel_uncore *uncore, 651 enum forcewake_domains fw_domains) 652{ 653 struct intel_uncore_forcewake_domain *domain; 654 unsigned int tmp; 655 656 fw_domains &= uncore->fw_domains; 657 658 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) { 659 if (domain->wake_count++) { 660 fw_domains &= ~domain->mask; 661 domain->active = true; 662 } 663 } 664 665 if (fw_domains) 666 fw_domains_get(uncore, fw_domains); 667} 668 669/** 670 * intel_uncore_forcewake_get - grab forcewake domain references 671 * @uncore: the intel_uncore structure 672 * @fw_domains: forcewake domains to get reference on 673 * 674 * This function can be used get GT's forcewake domain references. 675 * Normal register access will handle the forcewake domains automatically. 676 * However if some sequence requires the GT to not power down a particular 677 * forcewake domains this function should be called at the beginning of the 678 * sequence. And subsequently the reference should be dropped by symmetric 679 * call to intel_unforce_forcewake_put(). Usually caller wants all the domains 680 * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL. 681 */ 682void intel_uncore_forcewake_get(struct intel_uncore *uncore, 683 enum forcewake_domains fw_domains) 684{ 685 unsigned long irqflags; 686 687 if (!uncore->fw_get_funcs) 688 return; 689 690 assert_rpm_wakelock_held(uncore->rpm); 691 692 spin_lock_irqsave(&uncore->lock, irqflags); 693 __intel_uncore_forcewake_get(uncore, fw_domains); 694 spin_unlock_irqrestore(&uncore->lock, irqflags); 695} 696 697/** 698 * intel_uncore_forcewake_user_get - claim forcewake on behalf of userspace 699 * @uncore: the intel_uncore structure 700 * 701 * This function is a wrapper around intel_uncore_forcewake_get() to acquire 702 * the GT powerwell and in the process disable our debugging for the 703 * duration of userspace's bypass. 704 */ 705void intel_uncore_forcewake_user_get(struct intel_uncore *uncore) 706{ 707 spin_lock_irq(&uncore->lock); 708 if (!uncore->user_forcewake_count++) { 709 intel_uncore_forcewake_get__locked(uncore, FORCEWAKE_ALL); 710 mmio_debug_suspend(uncore); 711 } 712 spin_unlock_irq(&uncore->lock); 713} 714 715/** 716 * intel_uncore_forcewake_user_put - release forcewake on behalf of userspace 717 * @uncore: the intel_uncore structure 718 * 719 * This function complements intel_uncore_forcewake_user_get() and releases 720 * the GT powerwell taken on behalf of the userspace bypass. 721 */ 722void intel_uncore_forcewake_user_put(struct intel_uncore *uncore) 723{ 724 spin_lock_irq(&uncore->lock); 725 if (!--uncore->user_forcewake_count) { 726 mmio_debug_resume(uncore); 727 intel_uncore_forcewake_put__locked(uncore, FORCEWAKE_ALL); 728 } 729 spin_unlock_irq(&uncore->lock); 730} 731 732/** 733 * intel_uncore_forcewake_get__locked - grab forcewake domain references 734 * @uncore: the intel_uncore structure 735 * @fw_domains: forcewake domains to get reference on 736 * 737 * See intel_uncore_forcewake_get(). This variant places the onus 738 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock. 739 */ 740void intel_uncore_forcewake_get__locked(struct intel_uncore *uncore, 741 enum forcewake_domains fw_domains) 742{ 743 lockdep_assert_held(&uncore->lock); 744 745 if (!uncore->fw_get_funcs) 746 return; 747 748 __intel_uncore_forcewake_get(uncore, fw_domains); 749} 750 751static void __intel_uncore_forcewake_put(struct intel_uncore *uncore, 752 enum forcewake_domains fw_domains, 753 bool delayed) 754{ 755 struct intel_uncore_forcewake_domain *domain; 756 unsigned int tmp; 757 758 fw_domains &= uncore->fw_domains; 759 760 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) { 761 GEM_BUG_ON(!domain->wake_count); 762 763 if (--domain->wake_count) { 764 domain->active = true; 765 continue; 766 } 767 768 if (delayed && 769 !(domain->uncore->fw_domains_timer & domain->mask)) 770 fw_domain_arm_timer(domain); 771 else 772 fw_domains_put(uncore, domain->mask); 773 } 774} 775 776/** 777 * intel_uncore_forcewake_put - release a forcewake domain reference 778 * @uncore: the intel_uncore structure 779 * @fw_domains: forcewake domains to put references 780 * 781 * This function drops the device-level forcewakes for specified 782 * domains obtained by intel_uncore_forcewake_get(). 783 */ 784void intel_uncore_forcewake_put(struct intel_uncore *uncore, 785 enum forcewake_domains fw_domains) 786{ 787 unsigned long irqflags; 788 789 if (!uncore->fw_get_funcs) 790 return; 791 792 spin_lock_irqsave(&uncore->lock, irqflags); 793 __intel_uncore_forcewake_put(uncore, fw_domains, false); 794 spin_unlock_irqrestore(&uncore->lock, irqflags); 795} 796 797void intel_uncore_forcewake_put_delayed(struct intel_uncore *uncore, 798 enum forcewake_domains fw_domains) 799{ 800 unsigned long irqflags; 801 802 if (!uncore->fw_get_funcs) 803 return; 804 805 spin_lock_irqsave(&uncore->lock, irqflags); 806 __intel_uncore_forcewake_put(uncore, fw_domains, true); 807 spin_unlock_irqrestore(&uncore->lock, irqflags); 808} 809 810/** 811 * intel_uncore_forcewake_flush - flush the delayed release 812 * @uncore: the intel_uncore structure 813 * @fw_domains: forcewake domains to flush 814 */ 815void intel_uncore_forcewake_flush(struct intel_uncore *uncore, 816 enum forcewake_domains fw_domains) 817{ 818 struct intel_uncore_forcewake_domain *domain; 819 unsigned int tmp; 820 821 if (!uncore->fw_get_funcs) 822 return; 823 824 fw_domains &= uncore->fw_domains; 825 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) { 826 WRITE_ONCE(domain->active, false); 827 if (hrtimer_cancel(&domain->timer)) 828 intel_uncore_fw_release_timer(&domain->timer); 829 } 830} 831 832/** 833 * intel_uncore_forcewake_put__locked - release forcewake domain references 834 * @uncore: the intel_uncore structure 835 * @fw_domains: forcewake domains to put references 836 * 837 * See intel_uncore_forcewake_put(). This variant places the onus 838 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock. 839 */ 840void intel_uncore_forcewake_put__locked(struct intel_uncore *uncore, 841 enum forcewake_domains fw_domains) 842{ 843 lockdep_assert_held(&uncore->lock); 844 845 if (!uncore->fw_get_funcs) 846 return; 847 848 __intel_uncore_forcewake_put(uncore, fw_domains, false); 849} 850 851void assert_forcewakes_inactive(struct intel_uncore *uncore) 852{ 853 if (!uncore->fw_get_funcs) 854 return; 855 856 drm_WARN(&uncore->i915->drm, uncore->fw_domains_active, 857 "Expected all fw_domains to be inactive, but %08x are still on\n", 858 uncore->fw_domains_active); 859} 860 861void assert_forcewakes_active(struct intel_uncore *uncore, 862 enum forcewake_domains fw_domains) 863{ 864 struct intel_uncore_forcewake_domain *domain; 865 unsigned int tmp; 866 867 if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) 868 return; 869 870 if (!uncore->fw_get_funcs) 871 return; 872 873 spin_lock_irq(&uncore->lock); 874 875 assert_rpm_wakelock_held(uncore->rpm); 876 877 fw_domains &= uncore->fw_domains; 878 drm_WARN(&uncore->i915->drm, fw_domains & ~uncore->fw_domains_active, 879 "Expected %08x fw_domains to be active, but %08x are off\n", 880 fw_domains, fw_domains & ~uncore->fw_domains_active); 881 882 /* 883 * Check that the caller has an explicit wakeref and we don't mistake 884 * it for the auto wakeref. 885 */ 886 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) { 887 unsigned int actual = READ_ONCE(domain->wake_count); 888 unsigned int expect = 1; 889 890 if (uncore->fw_domains_timer & domain->mask) 891 expect++; /* pending automatic release */ 892 893 if (drm_WARN(&uncore->i915->drm, actual < expect, 894 "Expected domain %d to be held awake by caller, count=%d\n", 895 domain->id, actual)) 896 break; 897 } 898 899 spin_unlock_irq(&uncore->lock); 900} 901 902/* 903 * We give fast paths for the really cool registers. The second range includes 904 * media domains (and the GSC starting from Xe_LPM+) 905 */ 906#define NEEDS_FORCE_WAKE(reg) ({ \ 907 u32 __reg = (reg); \ 908 __reg < 0x40000 || __reg >= 0x116000; \ 909}) 910 911static int fw_range_cmp(u32 offset, const struct intel_forcewake_range *entry) 912{ 913 if (offset < entry->start) 914 return -1; 915 else if (offset > entry->end) 916 return 1; 917 else 918 return 0; 919} 920 921/* Copied and "macroized" from lib/bsearch.c */ 922#define BSEARCH(key, base, num, cmp) ({ \ 923 unsigned int start__ = 0, end__ = (num); \ 924 typeof(base) result__ = NULL; \ 925 while (start__ < end__) { \ 926 unsigned int mid__ = start__ + (end__ - start__) / 2; \ 927 int ret__ = (cmp)((key), (base) + mid__); \ 928 if (ret__ < 0) { \ 929 end__ = mid__; \ 930 } else if (ret__ > 0) { \ 931 start__ = mid__ + 1; \ 932 } else { \ 933 result__ = (base) + mid__; \ 934 break; \ 935 } \ 936 } \ 937 result__; \ 938}) 939 940static enum forcewake_domains 941find_fw_domain(struct intel_uncore *uncore, u32 offset) 942{ 943 const struct intel_forcewake_range *entry; 944 945 if (IS_GSI_REG(offset)) 946 offset += uncore->gsi_offset; 947 948 entry = BSEARCH(offset, 949 uncore->fw_domains_table, 950 uncore->fw_domains_table_entries, 951 fw_range_cmp); 952 953 if (!entry) 954 return 0; 955 956 /* 957 * The list of FW domains depends on the SKU in gen11+ so we 958 * can't determine it statically. We use FORCEWAKE_ALL and 959 * translate it here to the list of available domains. 960 */ 961 if (entry->domains == FORCEWAKE_ALL) 962 return uncore->fw_domains; 963 964 drm_WARN(&uncore->i915->drm, entry->domains & ~uncore->fw_domains, 965 "Uninitialized forcewake domain(s) 0x%x accessed at 0x%x\n", 966 entry->domains & ~uncore->fw_domains, offset); 967 968 return entry->domains; 969} 970 971/* 972 * Shadowed register tables describe special register ranges that i915 is 973 * allowed to write to without acquiring forcewake. If these registers' power 974 * wells are down, the hardware will save values written by i915 to a shadow 975 * copy and automatically transfer them into the real register the next time 976 * the power well is woken up. Shadowing only applies to writes; forcewake 977 * must still be acquired when reading from registers in these ranges. 978 * 979 * The documentation for shadowed registers is somewhat spotty on older 980 * platforms. However missing registers from these lists is non-fatal; it just 981 * means we'll wake up the hardware for some register accesses where we didn't 982 * really need to. 983 * 984 * The ranges listed in these tables must be sorted by offset. 985 * 986 * When adding new tables here, please also add them to 987 * intel_shadow_table_check() in selftests/intel_uncore.c so that they will be 988 * scanned for obvious mistakes or typos by the selftests. 989 */ 990 991static const struct i915_range gen8_shadowed_regs[] = { 992 { .start = 0x2030, .end = 0x2030 }, 993 { .start = 0xA008, .end = 0xA00C }, 994 { .start = 0x12030, .end = 0x12030 }, 995 { .start = 0x1a030, .end = 0x1a030 }, 996 { .start = 0x22030, .end = 0x22030 }, 997}; 998 999static const struct i915_range gen11_shadowed_regs[] = { 1000 { .start = 0x2030, .end = 0x2030 }, 1001 { .start = 0x2550, .end = 0x2550 }, 1002 { .start = 0xA008, .end = 0xA00C }, 1003 { .start = 0x22030, .end = 0x22030 }, 1004 { .start = 0x22230, .end = 0x22230 }, 1005 { .start = 0x22510, .end = 0x22550 }, 1006 { .start = 0x1C0030, .end = 0x1C0030 }, 1007 { .start = 0x1C0230, .end = 0x1C0230 }, 1008 { .start = 0x1C0510, .end = 0x1C0550 }, 1009 { .start = 0x1C4030, .end = 0x1C4030 }, 1010 { .start = 0x1C4230, .end = 0x1C4230 }, 1011 { .start = 0x1C4510, .end = 0x1C4550 }, 1012 { .start = 0x1C8030, .end = 0x1C8030 }, 1013 { .start = 0x1C8230, .end = 0x1C8230 }, 1014 { .start = 0x1C8510, .end = 0x1C8550 }, 1015 { .start = 0x1D0030, .end = 0x1D0030 }, 1016 { .start = 0x1D0230, .end = 0x1D0230 }, 1017 { .start = 0x1D0510, .end = 0x1D0550 }, 1018 { .start = 0x1D4030, .end = 0x1D4030 }, 1019 { .start = 0x1D4230, .end = 0x1D4230 }, 1020 { .start = 0x1D4510, .end = 0x1D4550 }, 1021 { .start = 0x1D8030, .end = 0x1D8030 }, 1022 { .start = 0x1D8230, .end = 0x1D8230 }, 1023 { .start = 0x1D8510, .end = 0x1D8550 }, 1024}; 1025 1026static const struct i915_range gen12_shadowed_regs[] = { 1027 { .start = 0x2030, .end = 0x2030 }, 1028 { .start = 0x2510, .end = 0x2550 }, 1029 { .start = 0xA008, .end = 0xA00C }, 1030 { .start = 0xA188, .end = 0xA188 }, 1031 { .start = 0xA278, .end = 0xA278 }, 1032 { .start = 0xA540, .end = 0xA56C }, 1033 { .start = 0xC4C8, .end = 0xC4C8 }, 1034 { .start = 0xC4D4, .end = 0xC4D4 }, 1035 { .start = 0xC600, .end = 0xC600 }, 1036 { .start = 0x22030, .end = 0x22030 }, 1037 { .start = 0x22510, .end = 0x22550 }, 1038 { .start = 0x1C0030, .end = 0x1C0030 }, 1039 { .start = 0x1C0510, .end = 0x1C0550 }, 1040 { .start = 0x1C4030, .end = 0x1C4030 }, 1041 { .start = 0x1C4510, .end = 0x1C4550 }, 1042 { .start = 0x1C8030, .end = 0x1C8030 }, 1043 { .start = 0x1C8510, .end = 0x1C8550 }, 1044 { .start = 0x1D0030, .end = 0x1D0030 }, 1045 { .start = 0x1D0510, .end = 0x1D0550 }, 1046 { .start = 0x1D4030, .end = 0x1D4030 }, 1047 { .start = 0x1D4510, .end = 0x1D4550 }, 1048 { .start = 0x1D8030, .end = 0x1D8030 }, 1049 { .start = 0x1D8510, .end = 0x1D8550 }, 1050 1051 /* 1052 * The rest of these ranges are specific to Xe_HP and beyond, but 1053 * are reserved/unused ranges on earlier gen12 platforms, so they can 1054 * be safely added to the gen12 table. 1055 */ 1056 { .start = 0x1E0030, .end = 0x1E0030 }, 1057 { .start = 0x1E0510, .end = 0x1E0550 }, 1058 { .start = 0x1E4030, .end = 0x1E4030 }, 1059 { .start = 0x1E4510, .end = 0x1E4550 }, 1060 { .start = 0x1E8030, .end = 0x1E8030 }, 1061 { .start = 0x1E8510, .end = 0x1E8550 }, 1062 { .start = 0x1F0030, .end = 0x1F0030 }, 1063 { .start = 0x1F0510, .end = 0x1F0550 }, 1064 { .start = 0x1F4030, .end = 0x1F4030 }, 1065 { .start = 0x1F4510, .end = 0x1F4550 }, 1066 { .start = 0x1F8030, .end = 0x1F8030 }, 1067 { .start = 0x1F8510, .end = 0x1F8550 }, 1068}; 1069 1070static const struct i915_range dg2_shadowed_regs[] = { 1071 { .start = 0x2030, .end = 0x2030 }, 1072 { .start = 0x2510, .end = 0x2550 }, 1073 { .start = 0xA008, .end = 0xA00C }, 1074 { .start = 0xA188, .end = 0xA188 }, 1075 { .start = 0xA278, .end = 0xA278 }, 1076 { .start = 0xA540, .end = 0xA56C }, 1077 { .start = 0xC4C8, .end = 0xC4C8 }, 1078 { .start = 0xC4E0, .end = 0xC4E0 }, 1079 { .start = 0xC600, .end = 0xC600 }, 1080 { .start = 0xC658, .end = 0xC658 }, 1081 { .start = 0x22030, .end = 0x22030 }, 1082 { .start = 0x22510, .end = 0x22550 }, 1083 { .start = 0x1C0030, .end = 0x1C0030 }, 1084 { .start = 0x1C0510, .end = 0x1C0550 }, 1085 { .start = 0x1C4030, .end = 0x1C4030 }, 1086 { .start = 0x1C4510, .end = 0x1C4550 }, 1087 { .start = 0x1C8030, .end = 0x1C8030 }, 1088 { .start = 0x1C8510, .end = 0x1C8550 }, 1089 { .start = 0x1D0030, .end = 0x1D0030 }, 1090 { .start = 0x1D0510, .end = 0x1D0550 }, 1091 { .start = 0x1D4030, .end = 0x1D4030 }, 1092 { .start = 0x1D4510, .end = 0x1D4550 }, 1093 { .start = 0x1D8030, .end = 0x1D8030 }, 1094 { .start = 0x1D8510, .end = 0x1D8550 }, 1095 { .start = 0x1E0030, .end = 0x1E0030 }, 1096 { .start = 0x1E0510, .end = 0x1E0550 }, 1097 { .start = 0x1E4030, .end = 0x1E4030 }, 1098 { .start = 0x1E4510, .end = 0x1E4550 }, 1099 { .start = 0x1E8030, .end = 0x1E8030 }, 1100 { .start = 0x1E8510, .end = 0x1E8550 }, 1101 { .start = 0x1F0030, .end = 0x1F0030 }, 1102 { .start = 0x1F0510, .end = 0x1F0550 }, 1103 { .start = 0x1F4030, .end = 0x1F4030 }, 1104 { .start = 0x1F4510, .end = 0x1F4550 }, 1105 { .start = 0x1F8030, .end = 0x1F8030 }, 1106 { .start = 0x1F8510, .end = 0x1F8550 }, 1107}; 1108 1109static const struct i915_range mtl_shadowed_regs[] = { 1110 { .start = 0x2030, .end = 0x2030 }, 1111 { .start = 0x2510, .end = 0x2550 }, 1112 { .start = 0xA008, .end = 0xA00C }, 1113 { .start = 0xA188, .end = 0xA188 }, 1114 { .start = 0xA278, .end = 0xA278 }, 1115 { .start = 0xA540, .end = 0xA56C }, 1116 { .start = 0xC050, .end = 0xC050 }, 1117 { .start = 0xC340, .end = 0xC340 }, 1118 { .start = 0xC4C8, .end = 0xC4C8 }, 1119 { .start = 0xC4E0, .end = 0xC4E0 }, 1120 { .start = 0xC600, .end = 0xC600 }, 1121 { .start = 0xC658, .end = 0xC658 }, 1122 { .start = 0xCFD4, .end = 0xCFDC }, 1123 { .start = 0x22030, .end = 0x22030 }, 1124 { .start = 0x22510, .end = 0x22550 }, 1125}; 1126 1127static const struct i915_range xelpmp_shadowed_regs[] = { 1128 { .start = 0x1C0030, .end = 0x1C0030 }, 1129 { .start = 0x1C0510, .end = 0x1C0550 }, 1130 { .start = 0x1C8030, .end = 0x1C8030 }, 1131 { .start = 0x1C8510, .end = 0x1C8550 }, 1132 { .start = 0x1D0030, .end = 0x1D0030 }, 1133 { .start = 0x1D0510, .end = 0x1D0550 }, 1134 { .start = 0x38A008, .end = 0x38A00C }, 1135 { .start = 0x38A188, .end = 0x38A188 }, 1136 { .start = 0x38A278, .end = 0x38A278 }, 1137 { .start = 0x38A540, .end = 0x38A56C }, 1138 { .start = 0x38A618, .end = 0x38A618 }, 1139 { .start = 0x38C050, .end = 0x38C050 }, 1140 { .start = 0x38C340, .end = 0x38C340 }, 1141 { .start = 0x38C4C8, .end = 0x38C4C8 }, 1142 { .start = 0x38C4E0, .end = 0x38C4E4 }, 1143 { .start = 0x38C600, .end = 0x38C600 }, 1144 { .start = 0x38C658, .end = 0x38C658 }, 1145 { .start = 0x38CFD4, .end = 0x38CFDC }, 1146}; 1147 1148static int mmio_range_cmp(u32 key, const struct i915_range *range) 1149{ 1150 if (key < range->start) 1151 return -1; 1152 else if (key > range->end) 1153 return 1; 1154 else 1155 return 0; 1156} 1157 1158static bool is_shadowed(struct intel_uncore *uncore, u32 offset) 1159{ 1160 if (drm_WARN_ON(&uncore->i915->drm, !uncore->shadowed_reg_table)) 1161 return false; 1162 1163 if (IS_GSI_REG(offset)) 1164 offset += uncore->gsi_offset; 1165 1166 return BSEARCH(offset, 1167 uncore->shadowed_reg_table, 1168 uncore->shadowed_reg_table_entries, 1169 mmio_range_cmp); 1170} 1171 1172static enum forcewake_domains 1173gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) 1174{ 1175 return FORCEWAKE_RENDER; 1176} 1177 1178#define __fwtable_reg_read_fw_domains(uncore, offset) \ 1179({ \ 1180 enum forcewake_domains __fwd = 0; \ 1181 if (NEEDS_FORCE_WAKE((offset))) \ 1182 __fwd = find_fw_domain(uncore, offset); \ 1183 __fwd; \ 1184}) 1185 1186#define __fwtable_reg_write_fw_domains(uncore, offset) \ 1187({ \ 1188 enum forcewake_domains __fwd = 0; \ 1189 const u32 __offset = (offset); \ 1190 if (NEEDS_FORCE_WAKE((__offset)) && !is_shadowed(uncore, __offset)) \ 1191 __fwd = find_fw_domain(uncore, __offset); \ 1192 __fwd; \ 1193}) 1194 1195#define GEN_FW_RANGE(s, e, d) \ 1196 { .start = (s), .end = (e), .domains = (d) } 1197 1198/* 1199 * All platforms' forcewake tables below must be sorted by offset ranges. 1200 * Furthermore, new forcewake tables added should be "watertight" and have 1201 * no gaps between ranges. 1202 * 1203 * When there are multiple consecutive ranges listed in the bspec with 1204 * the same forcewake domain, it is customary to combine them into a single 1205 * row in the tables below to keep the tables small and lookups fast. 1206 * Likewise, reserved/unused ranges may be combined with the preceding and/or 1207 * following ranges since the driver will never be making MMIO accesses in 1208 * those ranges. 1209 * 1210 * For example, if the bspec were to list: 1211 * 1212 * ... 1213 * 0x1000 - 0x1fff: GT 1214 * 0x2000 - 0x2cff: GT 1215 * 0x2d00 - 0x2fff: unused/reserved 1216 * 0x3000 - 0xffff: GT 1217 * ... 1218 * 1219 * these could all be represented by a single line in the code: 1220 * 1221 * GEN_FW_RANGE(0x1000, 0xffff, FORCEWAKE_GT) 1222 * 1223 * When adding new forcewake tables here, please also add them to 1224 * intel_uncore_mock_selftests in selftests/intel_uncore.c so that they will be 1225 * scanned for obvious mistakes or typos by the selftests. 1226 */ 1227 1228static const struct intel_forcewake_range __gen6_fw_ranges[] = { 1229 GEN_FW_RANGE(0x0, 0x3ffff, FORCEWAKE_RENDER), 1230}; 1231 1232static const struct intel_forcewake_range __vlv_fw_ranges[] = { 1233 GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER), 1234 GEN_FW_RANGE(0x5000, 0x7fff, FORCEWAKE_RENDER), 1235 GEN_FW_RANGE(0xb000, 0x11fff, FORCEWAKE_RENDER), 1236 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA), 1237 GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_MEDIA), 1238 GEN_FW_RANGE(0x2e000, 0x2ffff, FORCEWAKE_RENDER), 1239 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA), 1240}; 1241 1242static const struct intel_forcewake_range __chv_fw_ranges[] = { 1243 GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER), 1244 GEN_FW_RANGE(0x4000, 0x4fff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), 1245 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), 1246 GEN_FW_RANGE(0x8000, 0x82ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), 1247 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), 1248 GEN_FW_RANGE(0x8500, 0x85ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), 1249 GEN_FW_RANGE(0x8800, 0x88ff, FORCEWAKE_MEDIA), 1250 GEN_FW_RANGE(0x9000, 0xafff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), 1251 GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER), 1252 GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA), 1253 GEN_FW_RANGE(0xe000, 0xe7ff, FORCEWAKE_RENDER), 1254 GEN_FW_RANGE(0xf000, 0xffff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), 1255 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA), 1256 GEN_FW_RANGE(0x1a000, 0x1bfff, FORCEWAKE_MEDIA), 1257 GEN_FW_RANGE(0x1e800, 0x1e9ff, FORCEWAKE_MEDIA), 1258 GEN_FW_RANGE(0x30000, 0x37fff, FORCEWAKE_MEDIA), 1259}; 1260 1261static const struct intel_forcewake_range __gen9_fw_ranges[] = { 1262 GEN_FW_RANGE(0x0, 0xaff, FORCEWAKE_GT), 1263 GEN_FW_RANGE(0xb00, 0x1fff, 0), /* uncore range */ 1264 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), 1265 GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT), 1266 GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER), 1267 GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT), 1268 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), 1269 GEN_FW_RANGE(0x8000, 0x812f, FORCEWAKE_GT), 1270 GEN_FW_RANGE(0x8130, 0x813f, FORCEWAKE_MEDIA), 1271 GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), 1272 GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_GT), 1273 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), 1274 GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_GT), 1275 GEN_FW_RANGE(0x8800, 0x89ff, FORCEWAKE_MEDIA), 1276 GEN_FW_RANGE(0x8a00, 0x8bff, FORCEWAKE_GT), 1277 GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER), 1278 GEN_FW_RANGE(0x8d00, 0x93ff, FORCEWAKE_GT), 1279 GEN_FW_RANGE(0x9400, 0x97ff, FORCEWAKE_RENDER | FORCEWAKE_MEDIA), 1280 GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_GT), 1281 GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER), 1282 GEN_FW_RANGE(0xb480, 0xcfff, FORCEWAKE_GT), 1283 GEN_FW_RANGE(0xd000, 0xd7ff, FORCEWAKE_MEDIA), 1284 GEN_FW_RANGE(0xd800, 0xdfff, FORCEWAKE_GT), 1285 GEN_FW_RANGE(0xe000, 0xe8ff, FORCEWAKE_RENDER), 1286 GEN_FW_RANGE(0xe900, 0x11fff, FORCEWAKE_GT), 1287 GEN_FW_RANGE(0x12000, 0x13fff, FORCEWAKE_MEDIA), 1288 GEN_FW_RANGE(0x14000, 0x19fff, FORCEWAKE_GT), 1289 GEN_FW_RANGE(0x1a000, 0x1e9ff, FORCEWAKE_MEDIA), 1290 GEN_FW_RANGE(0x1ea00, 0x243ff, FORCEWAKE_GT), 1291 GEN_FW_RANGE(0x24400, 0x247ff, FORCEWAKE_RENDER), 1292 GEN_FW_RANGE(0x24800, 0x2ffff, FORCEWAKE_GT), 1293 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA), 1294}; 1295 1296static const struct intel_forcewake_range __gen11_fw_ranges[] = { 1297 GEN_FW_RANGE(0x0, 0x1fff, 0), /* uncore range */ 1298 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), 1299 GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT), 1300 GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER), 1301 GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT), 1302 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), 1303 GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT), 1304 GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), 1305 GEN_FW_RANGE(0x8160, 0x82ff, FORCEWAKE_GT), 1306 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), 1307 GEN_FW_RANGE(0x8500, 0x87ff, FORCEWAKE_GT), 1308 GEN_FW_RANGE(0x8800, 0x8bff, 0), 1309 GEN_FW_RANGE(0x8c00, 0x8cff, FORCEWAKE_RENDER), 1310 GEN_FW_RANGE(0x8d00, 0x94cf, FORCEWAKE_GT), 1311 GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER), 1312 GEN_FW_RANGE(0x9560, 0x95ff, 0), 1313 GEN_FW_RANGE(0x9600, 0xafff, FORCEWAKE_GT), 1314 GEN_FW_RANGE(0xb000, 0xb47f, FORCEWAKE_RENDER), 1315 GEN_FW_RANGE(0xb480, 0xdeff, FORCEWAKE_GT), 1316 GEN_FW_RANGE(0xdf00, 0xe8ff, FORCEWAKE_RENDER), 1317 GEN_FW_RANGE(0xe900, 0x16dff, FORCEWAKE_GT), 1318 GEN_FW_RANGE(0x16e00, 0x19fff, FORCEWAKE_RENDER), 1319 GEN_FW_RANGE(0x1a000, 0x23fff, FORCEWAKE_GT), 1320 GEN_FW_RANGE(0x24000, 0x2407f, 0), 1321 GEN_FW_RANGE(0x24080, 0x2417f, FORCEWAKE_GT), 1322 GEN_FW_RANGE(0x24180, 0x242ff, FORCEWAKE_RENDER), 1323 GEN_FW_RANGE(0x24300, 0x243ff, FORCEWAKE_GT), 1324 GEN_FW_RANGE(0x24400, 0x24fff, FORCEWAKE_RENDER), 1325 GEN_FW_RANGE(0x25000, 0x3ffff, FORCEWAKE_GT), 1326 GEN_FW_RANGE(0x40000, 0x1bffff, 0), 1327 GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), 1328 GEN_FW_RANGE(0x1c4000, 0x1c7fff, 0), 1329 GEN_FW_RANGE(0x1c8000, 0x1cffff, FORCEWAKE_MEDIA_VEBOX0), 1330 GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), 1331 GEN_FW_RANGE(0x1d4000, 0x1dbfff, 0) 1332}; 1333 1334static const struct intel_forcewake_range __gen12_fw_ranges[] = { 1335 GEN_FW_RANGE(0x0, 0x1fff, 0), /* 1336 0x0 - 0xaff: reserved 1337 0xb00 - 0x1fff: always on */ 1338 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), 1339 GEN_FW_RANGE(0x2700, 0x27ff, FORCEWAKE_GT), 1340 GEN_FW_RANGE(0x2800, 0x2aff, FORCEWAKE_RENDER), 1341 GEN_FW_RANGE(0x2b00, 0x2fff, FORCEWAKE_GT), 1342 GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER), 1343 GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT), /* 1344 0x4000 - 0x48ff: gt 1345 0x4900 - 0x51ff: reserved */ 1346 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), /* 1347 0x5200 - 0x53ff: render 1348 0x5400 - 0x54ff: reserved 1349 0x5500 - 0x7fff: render */ 1350 GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT), 1351 GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), 1352 GEN_FW_RANGE(0x8160, 0x81ff, 0), /* 1353 0x8160 - 0x817f: reserved 1354 0x8180 - 0x81ff: always on */ 1355 GEN_FW_RANGE(0x8200, 0x82ff, FORCEWAKE_GT), 1356 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), 1357 GEN_FW_RANGE(0x8500, 0x94cf, FORCEWAKE_GT), /* 1358 0x8500 - 0x87ff: gt 1359 0x8800 - 0x8fff: reserved 1360 0x9000 - 0x947f: gt 1361 0x9480 - 0x94cf: reserved */ 1362 GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER), 1363 GEN_FW_RANGE(0x9560, 0x97ff, 0), /* 1364 0x9560 - 0x95ff: always on 1365 0x9600 - 0x97ff: reserved */ 1366 GEN_FW_RANGE(0x9800, 0xafff, FORCEWAKE_GT), 1367 GEN_FW_RANGE(0xb000, 0xb3ff, FORCEWAKE_RENDER), 1368 GEN_FW_RANGE(0xb400, 0xcfff, FORCEWAKE_GT), /* 1369 0xb400 - 0xbf7f: gt 1370 0xb480 - 0xbfff: reserved 1371 0xc000 - 0xcfff: gt */ 1372 GEN_FW_RANGE(0xd000, 0xd7ff, 0), 1373 GEN_FW_RANGE(0xd800, 0xd8ff, FORCEWAKE_RENDER), 1374 GEN_FW_RANGE(0xd900, 0xdbff, FORCEWAKE_GT), 1375 GEN_FW_RANGE(0xdc00, 0xefff, FORCEWAKE_RENDER), /* 1376 0xdc00 - 0xddff: render 1377 0xde00 - 0xde7f: reserved 1378 0xde80 - 0xe8ff: render 1379 0xe900 - 0xefff: reserved */ 1380 GEN_FW_RANGE(0xf000, 0x147ff, FORCEWAKE_GT), /* 1381 0xf000 - 0xffff: gt 1382 0x10000 - 0x147ff: reserved */ 1383 GEN_FW_RANGE(0x14800, 0x1ffff, FORCEWAKE_RENDER), /* 1384 0x14800 - 0x14fff: render 1385 0x15000 - 0x16dff: reserved 1386 0x16e00 - 0x1bfff: render 1387 0x1c000 - 0x1ffff: reserved */ 1388 GEN_FW_RANGE(0x20000, 0x20fff, FORCEWAKE_MEDIA_VDBOX0), 1389 GEN_FW_RANGE(0x21000, 0x21fff, FORCEWAKE_MEDIA_VDBOX2), 1390 GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT), 1391 GEN_FW_RANGE(0x24000, 0x2417f, 0), /* 1392 0x24000 - 0x2407f: always on 1393 0x24080 - 0x2417f: reserved */ 1394 GEN_FW_RANGE(0x24180, 0x249ff, FORCEWAKE_GT), /* 1395 0x24180 - 0x241ff: gt 1396 0x24200 - 0x249ff: reserved */ 1397 GEN_FW_RANGE(0x24a00, 0x251ff, FORCEWAKE_RENDER), /* 1398 0x24a00 - 0x24a7f: render 1399 0x24a80 - 0x251ff: reserved */ 1400 GEN_FW_RANGE(0x25200, 0x255ff, FORCEWAKE_GT), /* 1401 0x25200 - 0x252ff: gt 1402 0x25300 - 0x255ff: reserved */ 1403 GEN_FW_RANGE(0x25600, 0x2567f, FORCEWAKE_MEDIA_VDBOX0), 1404 GEN_FW_RANGE(0x25680, 0x259ff, FORCEWAKE_MEDIA_VDBOX2), /* 1405 0x25680 - 0x256ff: VD2 1406 0x25700 - 0x259ff: reserved */ 1407 GEN_FW_RANGE(0x25a00, 0x25a7f, FORCEWAKE_MEDIA_VDBOX0), 1408 GEN_FW_RANGE(0x25a80, 0x2ffff, FORCEWAKE_MEDIA_VDBOX2), /* 1409 0x25a80 - 0x25aff: VD2 1410 0x25b00 - 0x2ffff: reserved */ 1411 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_GT), 1412 GEN_FW_RANGE(0x40000, 0x1bffff, 0), 1413 GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /* 1414 0x1c0000 - 0x1c2bff: VD0 1415 0x1c2c00 - 0x1c2cff: reserved 1416 0x1c2d00 - 0x1c2dff: VD0 1417 0x1c2e00 - 0x1c3eff: reserved 1418 0x1c3f00 - 0x1c3fff: VD0 */ 1419 GEN_FW_RANGE(0x1c4000, 0x1c7fff, 0), 1420 GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), /* 1421 0x1c8000 - 0x1ca0ff: VE0 1422 0x1ca100 - 0x1cbeff: reserved 1423 0x1cbf00 - 0x1cbfff: VE0 */ 1424 GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX0), /* 1425 0x1cc000 - 0x1ccfff: VD0 1426 0x1cd000 - 0x1cffff: reserved */ 1427 GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), /* 1428 0x1d0000 - 0x1d2bff: VD2 1429 0x1d2c00 - 0x1d2cff: reserved 1430 0x1d2d00 - 0x1d2dff: VD2 1431 0x1d2e00 - 0x1d3eff: reserved 1432 0x1d3f00 - 0x1d3fff: VD2 */ 1433}; 1434 1435static const struct intel_forcewake_range __dg2_fw_ranges[] = { 1436 GEN_FW_RANGE(0x0, 0x1fff, 0), /* 1437 0x0 - 0xaff: reserved 1438 0xb00 - 0x1fff: always on */ 1439 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), 1440 GEN_FW_RANGE(0x2700, 0x4aff, FORCEWAKE_GT), 1441 GEN_FW_RANGE(0x4b00, 0x51ff, 0), /* 1442 0x4b00 - 0x4fff: reserved 1443 0x5000 - 0x51ff: always on */ 1444 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), 1445 GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT), 1446 GEN_FW_RANGE(0x8140, 0x815f, FORCEWAKE_RENDER), 1447 GEN_FW_RANGE(0x8160, 0x81ff, 0), /* 1448 0x8160 - 0x817f: reserved 1449 0x8180 - 0x81ff: always on */ 1450 GEN_FW_RANGE(0x8200, 0x82ff, FORCEWAKE_GT), 1451 GEN_FW_RANGE(0x8300, 0x84ff, FORCEWAKE_RENDER), 1452 GEN_FW_RANGE(0x8500, 0x8cff, FORCEWAKE_GT), /* 1453 0x8500 - 0x87ff: gt 1454 0x8800 - 0x8c7f: reserved 1455 0x8c80 - 0x8cff: gt (DG2 only) */ 1456 GEN_FW_RANGE(0x8d00, 0x8fff, FORCEWAKE_RENDER), /* 1457 0x8d00 - 0x8dff: render (DG2 only) 1458 0x8e00 - 0x8fff: reserved */ 1459 GEN_FW_RANGE(0x9000, 0x94cf, FORCEWAKE_GT), /* 1460 0x9000 - 0x947f: gt 1461 0x9480 - 0x94cf: reserved */ 1462 GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER), 1463 GEN_FW_RANGE(0x9560, 0x967f, 0), /* 1464 0x9560 - 0x95ff: always on 1465 0x9600 - 0x967f: reserved */ 1466 GEN_FW_RANGE(0x9680, 0x97ff, FORCEWAKE_RENDER), /* 1467 0x9680 - 0x96ff: render 1468 0x9700 - 0x97ff: reserved */ 1469 GEN_FW_RANGE(0x9800, 0xcfff, FORCEWAKE_GT), /* 1470 0x9800 - 0xb4ff: gt 1471 0xb500 - 0xbfff: reserved 1472 0xc000 - 0xcfff: gt */ 1473 GEN_FW_RANGE(0xd000, 0xd7ff, 0), 1474 GEN_FW_RANGE(0xd800, 0xd87f, FORCEWAKE_RENDER), 1475 GEN_FW_RANGE(0xd880, 0xdbff, FORCEWAKE_GT), 1476 GEN_FW_RANGE(0xdc00, 0xdcff, FORCEWAKE_RENDER), 1477 GEN_FW_RANGE(0xdd00, 0xde7f, FORCEWAKE_GT), /* 1478 0xdd00 - 0xddff: gt 1479 0xde00 - 0xde7f: reserved */ 1480 GEN_FW_RANGE(0xde80, 0xe8ff, FORCEWAKE_RENDER), /* 1481 0xde80 - 0xdfff: render 1482 0xe000 - 0xe0ff: reserved 1483 0xe100 - 0xe8ff: render */ 1484 GEN_FW_RANGE(0xe900, 0xffff, FORCEWAKE_GT), /* 1485 0xe900 - 0xe9ff: gt 1486 0xea00 - 0xefff: reserved 1487 0xf000 - 0xffff: gt */ 1488 GEN_FW_RANGE(0x10000, 0x12fff, 0), /* 1489 0x10000 - 0x11fff: reserved 1490 0x12000 - 0x127ff: always on 1491 0x12800 - 0x12fff: reserved */ 1492 GEN_FW_RANGE(0x13000, 0x131ff, FORCEWAKE_MEDIA_VDBOX0), 1493 GEN_FW_RANGE(0x13200, 0x147ff, FORCEWAKE_MEDIA_VDBOX2), /* 1494 0x13200 - 0x133ff: VD2 (DG2 only) 1495 0x13400 - 0x147ff: reserved */ 1496 GEN_FW_RANGE(0x14800, 0x14fff, FORCEWAKE_RENDER), 1497 GEN_FW_RANGE(0x15000, 0x16dff, FORCEWAKE_GT), /* 1498 0x15000 - 0x15fff: gt (DG2 only) 1499 0x16000 - 0x16dff: reserved */ 1500 GEN_FW_RANGE(0x16e00, 0x21fff, FORCEWAKE_RENDER), /* 1501 0x16e00 - 0x1ffff: render 1502 0x20000 - 0x21fff: reserved */ 1503 GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT), 1504 GEN_FW_RANGE(0x24000, 0x2417f, 0), /* 1505 0x24000 - 0x2407f: always on 1506 0x24080 - 0x2417f: reserved */ 1507 GEN_FW_RANGE(0x24180, 0x249ff, FORCEWAKE_GT), /* 1508 0x24180 - 0x241ff: gt 1509 0x24200 - 0x249ff: reserved */ 1510 GEN_FW_RANGE(0x24a00, 0x251ff, FORCEWAKE_RENDER), /* 1511 0x24a00 - 0x24a7f: render 1512 0x24a80 - 0x251ff: reserved */ 1513 GEN_FW_RANGE(0x25200, 0x25fff, FORCEWAKE_GT), /* 1514 0x25200 - 0x252ff: gt 1515 0x25300 - 0x25fff: reserved */ 1516 GEN_FW_RANGE(0x26000, 0x2ffff, FORCEWAKE_RENDER), /* 1517 0x26000 - 0x27fff: render 1518 0x28000 - 0x29fff: reserved 1519 0x2a000 - 0x2ffff: undocumented */ 1520 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_GT), 1521 GEN_FW_RANGE(0x40000, 0x1bffff, 0), 1522 GEN_FW_RANGE(0x1c0000, 0x1c3fff, FORCEWAKE_MEDIA_VDBOX0), /* 1523 0x1c0000 - 0x1c2bff: VD0 1524 0x1c2c00 - 0x1c2cff: reserved 1525 0x1c2d00 - 0x1c2dff: VD0 1526 0x1c2e00 - 0x1c3eff: VD0 1527 0x1c3f00 - 0x1c3fff: VD0 */ 1528 GEN_FW_RANGE(0x1c4000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX1), /* 1529 0x1c4000 - 0x1c6bff: VD1 1530 0x1c6c00 - 0x1c6cff: reserved 1531 0x1c6d00 - 0x1c6dff: VD1 1532 0x1c6e00 - 0x1c7fff: reserved */ 1533 GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), /* 1534 0x1c8000 - 0x1ca0ff: VE0 1535 0x1ca100 - 0x1cbfff: reserved */ 1536 GEN_FW_RANGE(0x1cc000, 0x1ccfff, FORCEWAKE_MEDIA_VDBOX0), 1537 GEN_FW_RANGE(0x1cd000, 0x1cdfff, FORCEWAKE_MEDIA_VDBOX2), 1538 GEN_FW_RANGE(0x1ce000, 0x1cefff, FORCEWAKE_MEDIA_VDBOX4), 1539 GEN_FW_RANGE(0x1cf000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX6), 1540 GEN_FW_RANGE(0x1d0000, 0x1d3fff, FORCEWAKE_MEDIA_VDBOX2), /* 1541 0x1d0000 - 0x1d2bff: VD2 1542 0x1d2c00 - 0x1d2cff: reserved 1543 0x1d2d00 - 0x1d2dff: VD2 1544 0x1d2e00 - 0x1d3dff: VD2 1545 0x1d3e00 - 0x1d3eff: reserved 1546 0x1d3f00 - 0x1d3fff: VD2 */ 1547 GEN_FW_RANGE(0x1d4000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX3), /* 1548 0x1d4000 - 0x1d6bff: VD3 1549 0x1d6c00 - 0x1d6cff: reserved 1550 0x1d6d00 - 0x1d6dff: VD3 1551 0x1d6e00 - 0x1d7fff: reserved */ 1552 GEN_FW_RANGE(0x1d8000, 0x1dffff, FORCEWAKE_MEDIA_VEBOX1), /* 1553 0x1d8000 - 0x1da0ff: VE1 1554 0x1da100 - 0x1dffff: reserved */ 1555 GEN_FW_RANGE(0x1e0000, 0x1e3fff, FORCEWAKE_MEDIA_VDBOX4), /* 1556 0x1e0000 - 0x1e2bff: VD4 1557 0x1e2c00 - 0x1e2cff: reserved 1558 0x1e2d00 - 0x1e2dff: VD4 1559 0x1e2e00 - 0x1e3eff: reserved 1560 0x1e3f00 - 0x1e3fff: VD4 */ 1561 GEN_FW_RANGE(0x1e4000, 0x1e7fff, FORCEWAKE_MEDIA_VDBOX5), /* 1562 0x1e4000 - 0x1e6bff: VD5 1563 0x1e6c00 - 0x1e6cff: reserved 1564 0x1e6d00 - 0x1e6dff: VD5 1565 0x1e6e00 - 0x1e7fff: reserved */ 1566 GEN_FW_RANGE(0x1e8000, 0x1effff, FORCEWAKE_MEDIA_VEBOX2), /* 1567 0x1e8000 - 0x1ea0ff: VE2 1568 0x1ea100 - 0x1effff: reserved */ 1569 GEN_FW_RANGE(0x1f0000, 0x1f3fff, FORCEWAKE_MEDIA_VDBOX6), /* 1570 0x1f0000 - 0x1f2bff: VD6 1571 0x1f2c00 - 0x1f2cff: reserved 1572 0x1f2d00 - 0x1f2dff: VD6 1573 0x1f2e00 - 0x1f3eff: reserved 1574 0x1f3f00 - 0x1f3fff: VD6 */ 1575 GEN_FW_RANGE(0x1f4000, 0x1f7fff, FORCEWAKE_MEDIA_VDBOX7), /* 1576 0x1f4000 - 0x1f6bff: VD7 1577 0x1f6c00 - 0x1f6cff: reserved 1578 0x1f6d00 - 0x1f6dff: VD7 1579 0x1f6e00 - 0x1f7fff: reserved */ 1580 GEN_FW_RANGE(0x1f8000, 0x1fa0ff, FORCEWAKE_MEDIA_VEBOX3), 1581}; 1582 1583static const struct intel_forcewake_range __mtl_fw_ranges[] = { 1584 GEN_FW_RANGE(0x0, 0xaff, 0), 1585 GEN_FW_RANGE(0xb00, 0xbff, FORCEWAKE_GT), 1586 GEN_FW_RANGE(0xc00, 0xfff, 0), 1587 GEN_FW_RANGE(0x1000, 0x1fff, FORCEWAKE_GT), 1588 GEN_FW_RANGE(0x2000, 0x26ff, FORCEWAKE_RENDER), 1589 GEN_FW_RANGE(0x2700, 0x2fff, FORCEWAKE_GT), 1590 GEN_FW_RANGE(0x3000, 0x3fff, FORCEWAKE_RENDER), 1591 GEN_FW_RANGE(0x4000, 0x51ff, FORCEWAKE_GT), /* 1592 0x4000 - 0x48ff: render 1593 0x4900 - 0x51ff: reserved */ 1594 GEN_FW_RANGE(0x5200, 0x7fff, FORCEWAKE_RENDER), /* 1595 0x5200 - 0x53ff: render 1596 0x5400 - 0x54ff: reserved 1597 0x5500 - 0x7fff: render */ 1598 GEN_FW_RANGE(0x8000, 0x813f, FORCEWAKE_GT), 1599 GEN_FW_RANGE(0x8140, 0x817f, FORCEWAKE_RENDER), /* 1600 0x8140 - 0x815f: render 1601 0x8160 - 0x817f: reserved */ 1602 GEN_FW_RANGE(0x8180, 0x81ff, 0), 1603 GEN_FW_RANGE(0x8200, 0x94cf, FORCEWAKE_GT), /* 1604 0x8200 - 0x87ff: gt 1605 0x8800 - 0x8dff: reserved 1606 0x8e00 - 0x8f7f: gt 1607 0x8f80 - 0x8fff: reserved 1608 0x9000 - 0x947f: gt 1609 0x9480 - 0x94cf: reserved */ 1610 GEN_FW_RANGE(0x94d0, 0x955f, FORCEWAKE_RENDER), 1611 GEN_FW_RANGE(0x9560, 0x967f, 0), /* 1612 0x9560 - 0x95ff: always on 1613 0x9600 - 0x967f: reserved */ 1614 GEN_FW_RANGE(0x9680, 0x97ff, FORCEWAKE_RENDER), /* 1615 0x9680 - 0x96ff: render 1616 0x9700 - 0x97ff: reserved */ 1617 GEN_FW_RANGE(0x9800, 0xcfff, FORCEWAKE_GT), /* 1618 0x9800 - 0xb4ff: gt 1619 0xb500 - 0xbfff: reserved 1620 0xc000 - 0xcfff: gt */ 1621 GEN_FW_RANGE(0xd000, 0xd7ff, 0), /* 1622 0xd000 - 0xd3ff: always on 1623 0xd400 - 0xd7ff: reserved */ 1624 GEN_FW_RANGE(0xd800, 0xd87f, FORCEWAKE_RENDER), 1625 GEN_FW_RANGE(0xd880, 0xdbff, FORCEWAKE_GT), 1626 GEN_FW_RANGE(0xdc00, 0xdcff, FORCEWAKE_RENDER), 1627 GEN_FW_RANGE(0xdd00, 0xde7f, FORCEWAKE_GT), /* 1628 0xdd00 - 0xddff: gt 1629 0xde00 - 0xde7f: reserved */ 1630 GEN_FW_RANGE(0xde80, 0xe8ff, FORCEWAKE_RENDER), /* 1631 0xde80 - 0xdfff: render 1632 0xe000 - 0xe0ff: reserved 1633 0xe100 - 0xe8ff: render */ 1634 GEN_FW_RANGE(0xe900, 0xe9ff, FORCEWAKE_GT), 1635 GEN_FW_RANGE(0xea00, 0x147ff, 0), /* 1636 0xea00 - 0x11fff: reserved 1637 0x12000 - 0x127ff: always on 1638 0x12800 - 0x147ff: reserved */ 1639 GEN_FW_RANGE(0x14800, 0x19fff, FORCEWAKE_GT), /* 1640 0x14800 - 0x153ff: gt 1641 0x15400 - 0x19fff: reserved */ 1642 GEN_FW_RANGE(0x1a000, 0x21fff, FORCEWAKE_RENDER), /* 1643 0x1a000 - 0x1bfff: render 1644 0x1c000 - 0x21fff: reserved */ 1645 GEN_FW_RANGE(0x22000, 0x23fff, FORCEWAKE_GT), 1646 GEN_FW_RANGE(0x24000, 0x2ffff, 0), /* 1647 0x24000 - 0x2407f: always on 1648 0x24080 - 0x2ffff: reserved */ 1649 GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_GT), 1650 GEN_FW_RANGE(0x40000, 0x1901ef, 0), 1651 GEN_FW_RANGE(0x1901f0, 0x1901f3, FORCEWAKE_GT) 1652 /* FIXME: WA to wake GT while triggering H2G */ 1653}; 1654 1655/* 1656 * Note that the register ranges here are the final offsets after 1657 * translation of the GSI block to the 0x380000 offset. 1658 * 1659 * NOTE: There are a couple MCR ranges near the bottom of this table 1660 * that need to power up either VD0 or VD2 depending on which replicated 1661 * instance of the register we're trying to access. Our forcewake logic 1662 * at the moment doesn't have a good way to take steering into consideration, 1663 * and the driver doesn't even access any registers in those ranges today, 1664 * so for now we just mark those ranges as FORCEWAKE_ALL. That will ensure 1665 * proper operation if we do start using the ranges in the future, and we 1666 * can determine at that time whether it's worth adding extra complexity to 1667 * the forcewake handling to take steering into consideration. 1668 */ 1669static const struct intel_forcewake_range __xelpmp_fw_ranges[] = { 1670 GEN_FW_RANGE(0x0, 0x115fff, 0), /* render GT range */ 1671 GEN_FW_RANGE(0x116000, 0x11ffff, FORCEWAKE_GSC), /* 1672 0x116000 - 0x117fff: gsc 1673 0x118000 - 0x119fff: reserved 1674 0x11a000 - 0x11efff: gsc 1675 0x11f000 - 0x11ffff: reserved */ 1676 GEN_FW_RANGE(0x120000, 0x1bffff, 0), /* non-GT range */ 1677 GEN_FW_RANGE(0x1c0000, 0x1c7fff, FORCEWAKE_MEDIA_VDBOX0), /* 1678 0x1c0000 - 0x1c3dff: VD0 1679 0x1c3e00 - 0x1c3eff: reserved 1680 0x1c3f00 - 0x1c3fff: VD0 1681 0x1c4000 - 0x1c7fff: reserved */ 1682 GEN_FW_RANGE(0x1c8000, 0x1cbfff, FORCEWAKE_MEDIA_VEBOX0), /* 1683 0x1c8000 - 0x1ca0ff: VE0 1684 0x1ca100 - 0x1cbfff: reserved */ 1685 GEN_FW_RANGE(0x1cc000, 0x1cffff, FORCEWAKE_MEDIA_VDBOX0), /* 1686 0x1cc000 - 0x1cdfff: VD0 1687 0x1ce000 - 0x1cffff: reserved */ 1688 GEN_FW_RANGE(0x1d0000, 0x1d7fff, FORCEWAKE_MEDIA_VDBOX2), /* 1689 0x1d0000 - 0x1d3dff: VD2 1690 0x1d3e00 - 0x1d3eff: reserved 1691 0x1d4000 - 0x1d7fff: VD2 */ 1692 GEN_FW_RANGE(0x1d8000, 0x1da0ff, FORCEWAKE_MEDIA_VEBOX1), 1693 GEN_FW_RANGE(0x1da100, 0x380aff, 0), /* 1694 0x1da100 - 0x23ffff: reserved 1695 0x240000 - 0x37ffff: non-GT range 1696 0x380000 - 0x380aff: reserved */ 1697 GEN_FW_RANGE(0x380b00, 0x380bff, FORCEWAKE_GT), 1698 GEN_FW_RANGE(0x380c00, 0x380fff, 0), 1699 GEN_FW_RANGE(0x381000, 0x38817f, FORCEWAKE_GT), /* 1700 0x381000 - 0x381fff: gt 1701 0x382000 - 0x383fff: reserved 1702 0x384000 - 0x384aff: gt 1703 0x384b00 - 0x3851ff: reserved 1704 0x385200 - 0x3871ff: gt 1705 0x387200 - 0x387fff: reserved 1706 0x388000 - 0x38813f: gt 1707 0x388140 - 0x38817f: reserved */ 1708 GEN_FW_RANGE(0x388180, 0x3882ff, 0), /* 1709 0x388180 - 0x3881ff: always on 1710 0x388200 - 0x3882ff: reserved */ 1711 GEN_FW_RANGE(0x388300, 0x38955f, FORCEWAKE_GT), /* 1712 0x388300 - 0x38887f: gt 1713 0x388880 - 0x388fff: reserved 1714 0x389000 - 0x38947f: gt 1715 0x389480 - 0x38955f: reserved */ 1716 GEN_FW_RANGE(0x389560, 0x389fff, 0), /* 1717 0x389560 - 0x3895ff: always on 1718 0x389600 - 0x389fff: reserved */ 1719 GEN_FW_RANGE(0x38a000, 0x38cfff, FORCEWAKE_GT), /* 1720 0x38a000 - 0x38afff: gt 1721 0x38b000 - 0x38bfff: reserved 1722 0x38c000 - 0x38cfff: gt */ 1723 GEN_FW_RANGE(0x38d000, 0x38d11f, 0), 1724 GEN_FW_RANGE(0x38d120, 0x391fff, FORCEWAKE_GT), /* 1725 0x38d120 - 0x38dfff: gt 1726 0x38e000 - 0x38efff: reserved 1727 0x38f000 - 0x38ffff: gt 1728 0x389000 - 0x391fff: reserved */ 1729 GEN_FW_RANGE(0x392000, 0x392fff, 0), /* 1730 0x392000 - 0x3927ff: always on 1731 0x392800 - 0x292fff: reserved */ 1732 GEN_FW_RANGE(0x393000, 0x3931ff, FORCEWAKE_GT), 1733 GEN_FW_RANGE(0x393200, 0x39323f, FORCEWAKE_ALL), /* instance-based, see note above */ 1734 GEN_FW_RANGE(0x393240, 0x3933ff, FORCEWAKE_GT), 1735 GEN_FW_RANGE(0x393400, 0x3934ff, FORCEWAKE_ALL), /* instance-based, see note above */ 1736 GEN_FW_RANGE(0x393500, 0x393c7f, 0), /* 1737 0x393500 - 0x393bff: reserved 1738 0x393c00 - 0x393c7f: always on */ 1739 GEN_FW_RANGE(0x393c80, 0x393dff, FORCEWAKE_GT), 1740}; 1741 1742static void 1743ilk_dummy_write(struct intel_uncore *uncore) 1744{ 1745 /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up 1746 * the chip from rc6 before touching it for real. MI_MODE is masked, 1747 * hence harmless to write 0 into. */ 1748 __raw_uncore_write32(uncore, RING_MI_MODE(RENDER_RING_BASE), 0); 1749} 1750 1751static void 1752__unclaimed_reg_debug(struct intel_uncore *uncore, 1753 const i915_reg_t reg, 1754 const bool read) 1755{ 1756 if (drm_WARN(&uncore->i915->drm, 1757 check_for_unclaimed_mmio(uncore), 1758 "Unclaimed %s register 0x%x\n", 1759 read ? "read from" : "write to", 1760 i915_mmio_reg_offset(reg))) 1761 /* Only report the first N failures */ 1762 uncore->i915->params.mmio_debug--; 1763} 1764 1765static void 1766__unclaimed_previous_reg_debug(struct intel_uncore *uncore, 1767 const i915_reg_t reg, 1768 const bool read) 1769{ 1770 if (check_for_unclaimed_mmio(uncore)) 1771 drm_dbg(&uncore->i915->drm, 1772 "Unclaimed access detected before %s register 0x%x\n", 1773 read ? "read from" : "write to", 1774 i915_mmio_reg_offset(reg)); 1775} 1776 1777static inline bool __must_check 1778unclaimed_reg_debug_header(struct intel_uncore *uncore, 1779 const i915_reg_t reg, const bool read) 1780{ 1781 if (likely(!uncore->i915->params.mmio_debug) || !uncore->debug) 1782 return false; 1783 1784 /* interrupts are disabled and re-enabled around uncore->lock usage */ 1785 lockdep_assert_held(&uncore->lock); 1786 1787 spin_lock(&uncore->debug->lock); 1788 __unclaimed_previous_reg_debug(uncore, reg, read); 1789 1790 return true; 1791} 1792 1793static inline void 1794unclaimed_reg_debug_footer(struct intel_uncore *uncore, 1795 const i915_reg_t reg, const bool read) 1796{ 1797 /* interrupts are disabled and re-enabled around uncore->lock usage */ 1798 lockdep_assert_held(&uncore->lock); 1799 1800 __unclaimed_reg_debug(uncore, reg, read); 1801 spin_unlock(&uncore->debug->lock); 1802} 1803 1804#define __vgpu_read(x) \ 1805static u##x \ 1806vgpu_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \ 1807 u##x val = __raw_uncore_read##x(uncore, reg); \ 1808 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ 1809 return val; \ 1810} 1811__vgpu_read(8) 1812__vgpu_read(16) 1813__vgpu_read(32) 1814__vgpu_read(64) 1815 1816#define GEN2_READ_HEADER(x) \ 1817 u##x val = 0; \ 1818 assert_rpm_wakelock_held(uncore->rpm); 1819 1820#define GEN2_READ_FOOTER \ 1821 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ 1822 return val 1823 1824#define __gen2_read(x) \ 1825static u##x \ 1826gen2_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \ 1827 GEN2_READ_HEADER(x); \ 1828 val = __raw_uncore_read##x(uncore, reg); \ 1829 GEN2_READ_FOOTER; \ 1830} 1831 1832#define __gen5_read(x) \ 1833static u##x \ 1834gen5_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) { \ 1835 GEN2_READ_HEADER(x); \ 1836 ilk_dummy_write(uncore); \ 1837 val = __raw_uncore_read##x(uncore, reg); \ 1838 GEN2_READ_FOOTER; \ 1839} 1840 1841__gen5_read(8) 1842__gen5_read(16) 1843__gen5_read(32) 1844__gen5_read(64) 1845__gen2_read(8) 1846__gen2_read(16) 1847__gen2_read(32) 1848__gen2_read(64) 1849 1850#undef __gen5_read 1851#undef __gen2_read 1852 1853#undef GEN2_READ_FOOTER 1854#undef GEN2_READ_HEADER 1855 1856#define GEN6_READ_HEADER(x) \ 1857 u32 offset = i915_mmio_reg_offset(reg); \ 1858 unsigned long irqflags; \ 1859 bool unclaimed_reg_debug; \ 1860 u##x val = 0; \ 1861 assert_rpm_wakelock_held(uncore->rpm); \ 1862 spin_lock_irqsave(&uncore->lock, irqflags); \ 1863 unclaimed_reg_debug = unclaimed_reg_debug_header(uncore, reg, true) 1864 1865#define GEN6_READ_FOOTER \ 1866 if (unclaimed_reg_debug) \ 1867 unclaimed_reg_debug_footer(uncore, reg, true); \ 1868 spin_unlock_irqrestore(&uncore->lock, irqflags); \ 1869 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ 1870 return val 1871 1872static noinline void ___force_wake_auto(struct intel_uncore *uncore, 1873 enum forcewake_domains fw_domains) 1874{ 1875 struct intel_uncore_forcewake_domain *domain; 1876 unsigned int tmp; 1877 1878 GEM_BUG_ON(fw_domains & ~uncore->fw_domains); 1879 1880 for_each_fw_domain_masked(domain, fw_domains, uncore, tmp) 1881 fw_domain_arm_timer(domain); 1882 1883 fw_domains_get(uncore, fw_domains); 1884} 1885 1886static inline void __force_wake_auto(struct intel_uncore *uncore, 1887 enum forcewake_domains fw_domains) 1888{ 1889 GEM_BUG_ON(!fw_domains); 1890 1891 /* Turn on all requested but inactive supported forcewake domains. */ 1892 fw_domains &= uncore->fw_domains; 1893 fw_domains &= ~uncore->fw_domains_active; 1894 1895 if (fw_domains) 1896 ___force_wake_auto(uncore, fw_domains); 1897} 1898 1899#define __gen_fwtable_read(x) \ 1900static u##x \ 1901fwtable_read##x(struct intel_uncore *uncore, i915_reg_t reg, bool trace) \ 1902{ \ 1903 enum forcewake_domains fw_engine; \ 1904 GEN6_READ_HEADER(x); \ 1905 fw_engine = __fwtable_reg_read_fw_domains(uncore, offset); \ 1906 if (fw_engine) \ 1907 __force_wake_auto(uncore, fw_engine); \ 1908 val = __raw_uncore_read##x(uncore, reg); \ 1909 GEN6_READ_FOOTER; \ 1910} 1911 1912static enum forcewake_domains 1913fwtable_reg_read_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) { 1914 return __fwtable_reg_read_fw_domains(uncore, i915_mmio_reg_offset(reg)); 1915} 1916 1917__gen_fwtable_read(8) 1918__gen_fwtable_read(16) 1919__gen_fwtable_read(32) 1920__gen_fwtable_read(64) 1921 1922#undef __gen_fwtable_read 1923#undef GEN6_READ_FOOTER 1924#undef GEN6_READ_HEADER 1925 1926#define GEN2_WRITE_HEADER \ 1927 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ 1928 assert_rpm_wakelock_held(uncore->rpm); \ 1929 1930#define GEN2_WRITE_FOOTER 1931 1932#define __gen2_write(x) \ 1933static void \ 1934gen2_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ 1935 GEN2_WRITE_HEADER; \ 1936 __raw_uncore_write##x(uncore, reg, val); \ 1937 GEN2_WRITE_FOOTER; \ 1938} 1939 1940#define __gen5_write(x) \ 1941static void \ 1942gen5_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ 1943 GEN2_WRITE_HEADER; \ 1944 ilk_dummy_write(uncore); \ 1945 __raw_uncore_write##x(uncore, reg, val); \ 1946 GEN2_WRITE_FOOTER; \ 1947} 1948 1949__gen5_write(8) 1950__gen5_write(16) 1951__gen5_write(32) 1952__gen2_write(8) 1953__gen2_write(16) 1954__gen2_write(32) 1955 1956#undef __gen5_write 1957#undef __gen2_write 1958 1959#undef GEN2_WRITE_FOOTER 1960#undef GEN2_WRITE_HEADER 1961 1962#define GEN6_WRITE_HEADER \ 1963 u32 offset = i915_mmio_reg_offset(reg); \ 1964 unsigned long irqflags; \ 1965 bool unclaimed_reg_debug; \ 1966 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ 1967 assert_rpm_wakelock_held(uncore->rpm); \ 1968 spin_lock_irqsave(&uncore->lock, irqflags); \ 1969 unclaimed_reg_debug = unclaimed_reg_debug_header(uncore, reg, false) 1970 1971#define GEN6_WRITE_FOOTER \ 1972 if (unclaimed_reg_debug) \ 1973 unclaimed_reg_debug_footer(uncore, reg, false); \ 1974 spin_unlock_irqrestore(&uncore->lock, irqflags) 1975 1976#define __gen6_write(x) \ 1977static void \ 1978gen6_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ 1979 GEN6_WRITE_HEADER; \ 1980 if (NEEDS_FORCE_WAKE(offset)) \ 1981 __gen6_gt_wait_for_fifo(uncore); \ 1982 __raw_uncore_write##x(uncore, reg, val); \ 1983 GEN6_WRITE_FOOTER; \ 1984} 1985__gen6_write(8) 1986__gen6_write(16) 1987__gen6_write(32) 1988 1989#define __gen_fwtable_write(x) \ 1990static void \ 1991fwtable_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ 1992 enum forcewake_domains fw_engine; \ 1993 GEN6_WRITE_HEADER; \ 1994 fw_engine = __fwtable_reg_write_fw_domains(uncore, offset); \ 1995 if (fw_engine) \ 1996 __force_wake_auto(uncore, fw_engine); \ 1997 __raw_uncore_write##x(uncore, reg, val); \ 1998 GEN6_WRITE_FOOTER; \ 1999} 2000 2001static enum forcewake_domains 2002fwtable_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg) 2003{ 2004 return __fwtable_reg_write_fw_domains(uncore, i915_mmio_reg_offset(reg)); 2005} 2006 2007__gen_fwtable_write(8) 2008__gen_fwtable_write(16) 2009__gen_fwtable_write(32) 2010 2011#undef __gen_fwtable_write 2012#undef GEN6_WRITE_FOOTER 2013#undef GEN6_WRITE_HEADER 2014 2015#define __vgpu_write(x) \ 2016static void \ 2017vgpu_write##x(struct intel_uncore *uncore, i915_reg_t reg, u##x val, bool trace) { \ 2018 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ 2019 __raw_uncore_write##x(uncore, reg, val); \ 2020} 2021__vgpu_write(8) 2022__vgpu_write(16) 2023__vgpu_write(32) 2024 2025#define ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, x) \ 2026do { \ 2027 (uncore)->funcs.mmio_writeb = x##_write8; \ 2028 (uncore)->funcs.mmio_writew = x##_write16; \ 2029 (uncore)->funcs.mmio_writel = x##_write32; \ 2030} while (0) 2031 2032#define ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x) \ 2033do { \ 2034 (uncore)->funcs.mmio_readb = x##_read8; \ 2035 (uncore)->funcs.mmio_readw = x##_read16; \ 2036 (uncore)->funcs.mmio_readl = x##_read32; \ 2037 (uncore)->funcs.mmio_readq = x##_read64; \ 2038} while (0) 2039 2040#define ASSIGN_WRITE_MMIO_VFUNCS(uncore, x) \ 2041do { \ 2042 ASSIGN_RAW_WRITE_MMIO_VFUNCS((uncore), x); \ 2043 (uncore)->funcs.write_fw_domains = x##_reg_write_fw_domains; \ 2044} while (0) 2045 2046#define ASSIGN_READ_MMIO_VFUNCS(uncore, x) \ 2047do { \ 2048 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x); \ 2049 (uncore)->funcs.read_fw_domains = x##_reg_read_fw_domains; \ 2050} while (0) 2051 2052static int __fw_domain_init(struct intel_uncore *uncore, 2053 enum forcewake_domain_id domain_id, 2054 i915_reg_t reg_set, 2055 i915_reg_t reg_ack) 2056{ 2057 struct intel_uncore_forcewake_domain *d; 2058 2059 GEM_BUG_ON(domain_id >= FW_DOMAIN_ID_COUNT); 2060 GEM_BUG_ON(uncore->fw_domain[domain_id]); 2061 2062 if (i915_inject_probe_failure(uncore->i915)) 2063 return -ENOMEM; 2064 2065 d = kzalloc(sizeof(*d), GFP_KERNEL); 2066 if (!d) 2067 return -ENOMEM; 2068 2069 drm_WARN_ON(&uncore->i915->drm, !i915_mmio_reg_valid(reg_set)); 2070 drm_WARN_ON(&uncore->i915->drm, !i915_mmio_reg_valid(reg_ack)); 2071 2072 d->uncore = uncore; 2073 d->wake_count = 0; 2074 d->reg_set = uncore->regs + i915_mmio_reg_offset(reg_set) + uncore->gsi_offset; 2075 d->reg_ack = uncore->regs + i915_mmio_reg_offset(reg_ack) + uncore->gsi_offset; 2076 2077 d->id = domain_id; 2078 2079 BUILD_BUG_ON(FORCEWAKE_RENDER != (1 << FW_DOMAIN_ID_RENDER)); 2080 BUILD_BUG_ON(FORCEWAKE_GT != (1 << FW_DOMAIN_ID_GT)); 2081 BUILD_BUG_ON(FORCEWAKE_MEDIA != (1 << FW_DOMAIN_ID_MEDIA)); 2082 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX0)); 2083 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX1)); 2084 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX2 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX2)); 2085 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX3 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX3)); 2086 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX4 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX4)); 2087 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX5 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX5)); 2088 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX6 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX6)); 2089 BUILD_BUG_ON(FORCEWAKE_MEDIA_VDBOX7 != (1 << FW_DOMAIN_ID_MEDIA_VDBOX7)); 2090 BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX0 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX0)); 2091 BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX1 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX1)); 2092 BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX2 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX2)); 2093 BUILD_BUG_ON(FORCEWAKE_MEDIA_VEBOX3 != (1 << FW_DOMAIN_ID_MEDIA_VEBOX3)); 2094 BUILD_BUG_ON(FORCEWAKE_GSC != (1 << FW_DOMAIN_ID_GSC)); 2095 2096 d->mask = BIT(domain_id); 2097 2098 hrtimer_init(&d->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 2099 d->timer.function = intel_uncore_fw_release_timer; 2100 2101 uncore->fw_domains |= BIT(domain_id); 2102 2103 fw_domain_reset(d); 2104 2105 uncore->fw_domain[domain_id] = d; 2106 2107 return 0; 2108} 2109 2110static void fw_domain_fini(struct intel_uncore *uncore, 2111 enum forcewake_domain_id domain_id) 2112{ 2113 struct intel_uncore_forcewake_domain *d; 2114 2115 GEM_BUG_ON(domain_id >= FW_DOMAIN_ID_COUNT); 2116 2117 d = fetch_and_zero(&uncore->fw_domain[domain_id]); 2118 if (!d) 2119 return; 2120 2121 uncore->fw_domains &= ~BIT(domain_id); 2122 drm_WARN_ON(&uncore->i915->drm, d->wake_count); 2123 drm_WARN_ON(&uncore->i915->drm, hrtimer_cancel(&d->timer)); 2124 kfree(d); 2125} 2126 2127static void intel_uncore_fw_domains_fini(struct intel_uncore *uncore) 2128{ 2129 struct intel_uncore_forcewake_domain *d; 2130 int tmp; 2131 2132 for_each_fw_domain(d, uncore, tmp) 2133 fw_domain_fini(uncore, d->id); 2134} 2135 2136static const struct intel_uncore_fw_get uncore_get_fallback = { 2137 .force_wake_get = fw_domains_get_with_fallback 2138}; 2139 2140static const struct intel_uncore_fw_get uncore_get_normal = { 2141 .force_wake_get = fw_domains_get_normal, 2142}; 2143 2144static const struct intel_uncore_fw_get uncore_get_thread_status = { 2145 .force_wake_get = fw_domains_get_with_thread_status 2146}; 2147 2148static int intel_uncore_fw_domains_init(struct intel_uncore *uncore) 2149{ 2150 struct drm_i915_private *i915 = uncore->i915; 2151 int ret = 0; 2152 2153 GEM_BUG_ON(!intel_uncore_has_forcewake(uncore)); 2154 2155#define fw_domain_init(uncore__, id__, set__, ack__) \ 2156 (ret ?: (ret = __fw_domain_init((uncore__), (id__), (set__), (ack__)))) 2157 2158 if (GRAPHICS_VER(i915) >= 11) { 2159 intel_engine_mask_t emask; 2160 int i; 2161 2162 /* we'll prune the domains of missing engines later */ 2163 emask = uncore->gt->info.engine_mask; 2164 2165 uncore->fw_get_funcs = &uncore_get_fallback; 2166 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) 2167 fw_domain_init(uncore, FW_DOMAIN_ID_GT, 2168 FORCEWAKE_GT_GEN9, 2169 FORCEWAKE_ACK_GT_MTL); 2170 else 2171 fw_domain_init(uncore, FW_DOMAIN_ID_GT, 2172 FORCEWAKE_GT_GEN9, 2173 FORCEWAKE_ACK_GT_GEN9); 2174 2175 if (RCS_MASK(uncore->gt) || CCS_MASK(uncore->gt)) 2176 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, 2177 FORCEWAKE_RENDER_GEN9, 2178 FORCEWAKE_ACK_RENDER_GEN9); 2179 2180 for (i = 0; i < I915_MAX_VCS; i++) { 2181 if (!__HAS_ENGINE(emask, _VCS(i))) 2182 continue; 2183 2184 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VDBOX0 + i, 2185 FORCEWAKE_MEDIA_VDBOX_GEN11(i), 2186 FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(i)); 2187 } 2188 for (i = 0; i < I915_MAX_VECS; i++) { 2189 if (!__HAS_ENGINE(emask, _VECS(i))) 2190 continue; 2191 2192 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA_VEBOX0 + i, 2193 FORCEWAKE_MEDIA_VEBOX_GEN11(i), 2194 FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i)); 2195 } 2196 2197 if (uncore->gt->type == GT_MEDIA) 2198 fw_domain_init(uncore, FW_DOMAIN_ID_GSC, 2199 FORCEWAKE_REQ_GSC, FORCEWAKE_ACK_GSC); 2200 } else if (IS_GRAPHICS_VER(i915, 9, 10)) { 2201 uncore->fw_get_funcs = &uncore_get_fallback; 2202 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, 2203 FORCEWAKE_RENDER_GEN9, 2204 FORCEWAKE_ACK_RENDER_GEN9); 2205 fw_domain_init(uncore, FW_DOMAIN_ID_GT, 2206 FORCEWAKE_GT_GEN9, 2207 FORCEWAKE_ACK_GT_GEN9); 2208 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA, 2209 FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9); 2210 } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { 2211 uncore->fw_get_funcs = &uncore_get_normal; 2212 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, 2213 FORCEWAKE_VLV, FORCEWAKE_ACK_VLV); 2214 fw_domain_init(uncore, FW_DOMAIN_ID_MEDIA, 2215 FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV); 2216 } else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { 2217 uncore->fw_get_funcs = &uncore_get_thread_status; 2218 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, 2219 FORCEWAKE_MT, FORCEWAKE_ACK_HSW); 2220 } else if (IS_IVYBRIDGE(i915)) { 2221 u32 ecobus; 2222 2223 /* IVB configs may use multi-threaded forcewake */ 2224 2225 /* A small trick here - if the bios hasn't configured 2226 * MT forcewake, and if the device is in RC6, then 2227 * force_wake_mt_get will not wake the device and the 2228 * ECOBUS read will return zero. Which will be 2229 * (correctly) interpreted by the test below as MT 2230 * forcewake being disabled. 2231 */ 2232 uncore->fw_get_funcs = &uncore_get_thread_status; 2233 2234 /* We need to init first for ECOBUS access and then 2235 * determine later if we want to reinit, in case of MT access is 2236 * not working. In this stage we don't know which flavour this 2237 * ivb is, so it is better to reset also the gen6 fw registers 2238 * before the ecobus check. 2239 */ 2240 2241 __raw_uncore_write32(uncore, FORCEWAKE, 0); 2242 __raw_posting_read(uncore, ECOBUS); 2243 2244 ret = __fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, 2245 FORCEWAKE_MT, FORCEWAKE_MT_ACK); 2246 if (ret) 2247 goto out; 2248 2249 spin_lock_irq(&uncore->lock); 2250 fw_domains_get_with_thread_status(uncore, FORCEWAKE_RENDER); 2251 ecobus = __raw_uncore_read32(uncore, ECOBUS); 2252 fw_domains_put(uncore, FORCEWAKE_RENDER); 2253 spin_unlock_irq(&uncore->lock); 2254 2255 if (!(ecobus & FORCEWAKE_MT_ENABLE)) { 2256 drm_info(&i915->drm, "No MT forcewake available on Ivybridge, this can result in issues\n"); 2257 drm_info(&i915->drm, "when using vblank-synced partial screen updates.\n"); 2258 fw_domain_fini(uncore, FW_DOMAIN_ID_RENDER); 2259 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, 2260 FORCEWAKE, FORCEWAKE_ACK); 2261 } 2262 } else if (GRAPHICS_VER(i915) == 6) { 2263 uncore->fw_get_funcs = &uncore_get_thread_status; 2264 fw_domain_init(uncore, FW_DOMAIN_ID_RENDER, 2265 FORCEWAKE, FORCEWAKE_ACK); 2266 } 2267 2268#undef fw_domain_init 2269 2270 /* All future platforms are expected to require complex power gating */ 2271 drm_WARN_ON(&i915->drm, !ret && uncore->fw_domains == 0); 2272 2273out: 2274 if (ret) 2275 intel_uncore_fw_domains_fini(uncore); 2276 2277 return ret; 2278} 2279 2280#define ASSIGN_FW_DOMAINS_TABLE(uncore, d) \ 2281{ \ 2282 (uncore)->fw_domains_table = \ 2283 (struct intel_forcewake_range *)(d); \ 2284 (uncore)->fw_domains_table_entries = ARRAY_SIZE((d)); \ 2285} 2286 2287#define ASSIGN_SHADOW_TABLE(uncore, d) \ 2288{ \ 2289 (uncore)->shadowed_reg_table = d; \ 2290 (uncore)->shadowed_reg_table_entries = ARRAY_SIZE((d)); \ 2291} 2292 2293static int i915_pmic_bus_access_notifier(struct notifier_block *nb, 2294 unsigned long action, void *data) 2295{ 2296 struct intel_uncore *uncore = container_of(nb, 2297 struct intel_uncore, pmic_bus_access_nb); 2298 2299 switch (action) { 2300 case MBI_PMIC_BUS_ACCESS_BEGIN: 2301 /* 2302 * forcewake all now to make sure that we don't need to do a 2303 * forcewake later which on systems where this notifier gets 2304 * called requires the punit to access to the shared pmic i2c 2305 * bus, which will be busy after this notification, leading to: 2306 * "render: timed out waiting for forcewake ack request." 2307 * errors. 2308 * 2309 * The notifier is unregistered during intel_runtime_suspend(), 2310 * so it's ok to access the HW here without holding a RPM 2311 * wake reference -> disable wakeref asserts for the time of 2312 * the access. 2313 */ 2314 disable_rpm_wakeref_asserts(uncore->rpm); 2315 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); 2316 enable_rpm_wakeref_asserts(uncore->rpm); 2317 break; 2318 case MBI_PMIC_BUS_ACCESS_END: 2319 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL); 2320 break; 2321 } 2322 2323 return NOTIFY_OK; 2324} 2325 2326static void uncore_unmap_mmio(struct drm_device *drm, void *regs) 2327{ 2328 iounmap((void __iomem *)regs); 2329} 2330 2331int intel_uncore_setup_mmio(struct intel_uncore *uncore, phys_addr_t phys_addr) 2332{ 2333 struct drm_i915_private *i915 = uncore->i915; 2334 int mmio_size; 2335 2336 /* 2337 * Before gen4, the registers and the GTT are behind different BARs. 2338 * However, from gen4 onwards, the registers and the GTT are shared 2339 * in the same BAR, so we want to restrict this ioremap from 2340 * clobbering the GTT which we want ioremap_wc instead. Fortunately, 2341 * the register BAR remains the same size for all the earlier 2342 * generations up to Ironlake. 2343 * For dgfx chips register range is expanded to 4MB, and this larger 2344 * range is also used for integrated gpus beginning with Meteor Lake. 2345 */ 2346 if (IS_DGFX(i915) || GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) 2347 mmio_size = 4 * 1024 * 1024; 2348 else if (GRAPHICS_VER(i915) >= 5) 2349 mmio_size = 2 * 1024 * 1024; 2350 else 2351 mmio_size = 512 * 1024; 2352 2353 uncore->regs = ioremap(phys_addr, mmio_size); 2354 if (uncore->regs == NULL) { 2355 drm_err(&i915->drm, "failed to map registers\n"); 2356 return -EIO; 2357 } 2358 2359 return drmm_add_action_or_reset(&i915->drm, uncore_unmap_mmio, 2360 (void __force *)uncore->regs); 2361} 2362 2363void intel_uncore_init_early(struct intel_uncore *uncore, 2364 struct intel_gt *gt) 2365{ 2366 spin_lock_init(&uncore->lock); 2367 uncore->i915 = gt->i915; 2368 uncore->gt = gt; 2369 uncore->rpm = >->i915->runtime_pm; 2370} 2371 2372static void uncore_raw_init(struct intel_uncore *uncore) 2373{ 2374 GEM_BUG_ON(intel_uncore_has_forcewake(uncore)); 2375 2376 if (intel_vgpu_active(uncore->i915)) { 2377 ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, vgpu); 2378 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, vgpu); 2379 } else if (GRAPHICS_VER(uncore->i915) == 5) { 2380 ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen5); 2381 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen5); 2382 } else { 2383 ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen2); 2384 ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen2); 2385 } 2386} 2387 2388static int uncore_media_forcewake_init(struct intel_uncore *uncore) 2389{ 2390 struct drm_i915_private *i915 = uncore->i915; 2391 2392 if (MEDIA_VER(i915) >= 13) { 2393 ASSIGN_FW_DOMAINS_TABLE(uncore, __xelpmp_fw_ranges); 2394 ASSIGN_SHADOW_TABLE(uncore, xelpmp_shadowed_regs); 2395 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); 2396 } else { 2397 MISSING_CASE(MEDIA_VER(i915)); 2398 return -ENODEV; 2399 } 2400 2401 return 0; 2402} 2403 2404static int uncore_forcewake_init(struct intel_uncore *uncore) 2405{ 2406 struct drm_i915_private *i915 = uncore->i915; 2407 int ret; 2408 2409 GEM_BUG_ON(!intel_uncore_has_forcewake(uncore)); 2410 2411 ret = intel_uncore_fw_domains_init(uncore); 2412 if (ret) 2413 return ret; 2414 forcewake_early_sanitize(uncore, 0); 2415 2416 ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable); 2417 2418 if (uncore->gt->type == GT_MEDIA) 2419 return uncore_media_forcewake_init(uncore); 2420 2421 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) { 2422 ASSIGN_FW_DOMAINS_TABLE(uncore, __mtl_fw_ranges); 2423 ASSIGN_SHADOW_TABLE(uncore, mtl_shadowed_regs); 2424 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); 2425 } else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) { 2426 ASSIGN_FW_DOMAINS_TABLE(uncore, __dg2_fw_ranges); 2427 ASSIGN_SHADOW_TABLE(uncore, dg2_shadowed_regs); 2428 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); 2429 } else if (GRAPHICS_VER(i915) >= 12) { 2430 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen12_fw_ranges); 2431 ASSIGN_SHADOW_TABLE(uncore, gen12_shadowed_regs); 2432 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); 2433 } else if (GRAPHICS_VER(i915) == 11) { 2434 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen11_fw_ranges); 2435 ASSIGN_SHADOW_TABLE(uncore, gen11_shadowed_regs); 2436 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); 2437 } else if (IS_GRAPHICS_VER(i915, 9, 10)) { 2438 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen9_fw_ranges); 2439 ASSIGN_SHADOW_TABLE(uncore, gen8_shadowed_regs); 2440 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); 2441 } else if (IS_CHERRYVIEW(i915)) { 2442 ASSIGN_FW_DOMAINS_TABLE(uncore, __chv_fw_ranges); 2443 ASSIGN_SHADOW_TABLE(uncore, gen8_shadowed_regs); 2444 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); 2445 } else if (GRAPHICS_VER(i915) == 8) { 2446 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen6_fw_ranges); 2447 ASSIGN_SHADOW_TABLE(uncore, gen8_shadowed_regs); 2448 ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable); 2449 } else if (IS_VALLEYVIEW(i915)) { 2450 ASSIGN_FW_DOMAINS_TABLE(uncore, __vlv_fw_ranges); 2451 ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6); 2452 } else if (IS_GRAPHICS_VER(i915, 6, 7)) { 2453 ASSIGN_FW_DOMAINS_TABLE(uncore, __gen6_fw_ranges); 2454 ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6); 2455 } 2456 2457 uncore->pmic_bus_access_nb.notifier_call = i915_pmic_bus_access_notifier; 2458 iosf_mbi_register_pmic_bus_access_notifier(&uncore->pmic_bus_access_nb); 2459 2460 return 0; 2461} 2462 2463static int sanity_check_mmio_access(struct intel_uncore *uncore) 2464{ 2465 struct drm_i915_private *i915 = uncore->i915; 2466 2467 if (GRAPHICS_VER(i915) < 8) 2468 return 0; 2469 2470 /* 2471 * Sanitycheck that MMIO access to the device is working properly. If 2472 * the CPU is unable to communcate with a PCI device, BAR reads will 2473 * return 0xFFFFFFFF. Let's make sure the device isn't in this state 2474 * before we start trying to access registers. 2475 * 2476 * We use the primary GT's forcewake register as our guinea pig since 2477 * it's been around since HSW and it's a masked register so the upper 2478 * 16 bits can never read back as 1's if device access is operating 2479 * properly. 2480 * 2481 * If MMIO isn't working, we'll wait up to 2 seconds to see if it 2482 * recovers, then give up. 2483 */ 2484#define COND (__raw_uncore_read32(uncore, FORCEWAKE_MT) != ~0) 2485 if (wait_for(COND, 2000) == -ETIMEDOUT) { 2486 drm_err(&i915->drm, "Device is non-operational; MMIO access returns 0xFFFFFFFF!\n"); 2487 return -EIO; 2488 } 2489 2490 return 0; 2491} 2492 2493int intel_uncore_init_mmio(struct intel_uncore *uncore) 2494{ 2495 struct drm_i915_private *i915 = uncore->i915; 2496 int ret; 2497 2498 ret = sanity_check_mmio_access(uncore); 2499 if (ret) 2500 return ret; 2501 2502 /* 2503 * The boot firmware initializes local memory and assesses its health. 2504 * If memory training fails, the punit will have been instructed to 2505 * keep the GT powered down; we won't be able to communicate with it 2506 * and we should not continue with driver initialization. 2507 */ 2508 if (IS_DGFX(i915) && 2509 !(__raw_uncore_read32(uncore, GU_CNTL) & LMEM_INIT)) { 2510 drm_err(&i915->drm, "LMEM not initialized by firmware\n"); 2511 return -ENODEV; 2512 } 2513 2514 if (GRAPHICS_VER(i915) > 5 && !intel_vgpu_active(i915)) 2515 uncore->flags |= UNCORE_HAS_FORCEWAKE; 2516 2517 if (!intel_uncore_has_forcewake(uncore)) { 2518 uncore_raw_init(uncore); 2519 } else { 2520 ret = uncore_forcewake_init(uncore); 2521 if (ret) 2522 return ret; 2523 } 2524 2525 /* make sure fw funcs are set if and only if we have fw*/ 2526 GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->fw_get_funcs); 2527 GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.read_fw_domains); 2528 GEM_BUG_ON(intel_uncore_has_forcewake(uncore) != !!uncore->funcs.write_fw_domains); 2529 2530 if (HAS_FPGA_DBG_UNCLAIMED(i915)) 2531 uncore->flags |= UNCORE_HAS_FPGA_DBG_UNCLAIMED; 2532 2533 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) 2534 uncore->flags |= UNCORE_HAS_DBG_UNCLAIMED; 2535 2536 if (IS_GRAPHICS_VER(i915, 6, 7)) 2537 uncore->flags |= UNCORE_HAS_FIFO; 2538 2539 /* clear out unclaimed reg detection bit */ 2540 if (intel_uncore_unclaimed_mmio(uncore)) 2541 drm_dbg(&i915->drm, "unclaimed mmio detected on uncore init, clearing\n"); 2542 2543 return 0; 2544} 2545 2546/* 2547 * We might have detected that some engines are fused off after we initialized 2548 * the forcewake domains. Prune them, to make sure they only reference existing 2549 * engines. 2550 */ 2551void intel_uncore_prune_engine_fw_domains(struct intel_uncore *uncore, 2552 struct intel_gt *gt) 2553{ 2554 enum forcewake_domains fw_domains = uncore->fw_domains; 2555 enum forcewake_domain_id domain_id; 2556 int i; 2557 2558 if (!intel_uncore_has_forcewake(uncore) || GRAPHICS_VER(uncore->i915) < 11) 2559 return; 2560 2561 for (i = 0; i < I915_MAX_VCS; i++) { 2562 domain_id = FW_DOMAIN_ID_MEDIA_VDBOX0 + i; 2563 2564 if (HAS_ENGINE(gt, _VCS(i))) 2565 continue; 2566 2567 /* 2568 * Starting with XeHP, the power well for an even-numbered 2569 * VDBOX is also used for shared units within the 2570 * media slice such as SFC. So even if the engine 2571 * itself is fused off, we still need to initialize 2572 * the forcewake domain if any of the other engines 2573 * in the same media slice are present. 2574 */ 2575 if (GRAPHICS_VER_FULL(uncore->i915) >= IP_VER(12, 55) && i % 2 == 0) { 2576 if ((i + 1 < I915_MAX_VCS) && HAS_ENGINE(gt, _VCS(i + 1))) 2577 continue; 2578 2579 if (HAS_ENGINE(gt, _VECS(i / 2))) 2580 continue; 2581 } 2582 2583 if (fw_domains & BIT(domain_id)) 2584 fw_domain_fini(uncore, domain_id); 2585 } 2586 2587 for (i = 0; i < I915_MAX_VECS; i++) { 2588 domain_id = FW_DOMAIN_ID_MEDIA_VEBOX0 + i; 2589 2590 if (HAS_ENGINE(gt, _VECS(i))) 2591 continue; 2592 2593 if (fw_domains & BIT(domain_id)) 2594 fw_domain_fini(uncore, domain_id); 2595 } 2596 2597 if ((fw_domains & BIT(FW_DOMAIN_ID_GSC)) && !HAS_ENGINE(gt, GSC0)) 2598 fw_domain_fini(uncore, FW_DOMAIN_ID_GSC); 2599} 2600 2601/* 2602 * The driver-initiated FLR is the highest level of reset that we can trigger 2603 * from within the driver. It is different from the PCI FLR in that it doesn't 2604 * fully reset the SGUnit and doesn't modify the PCI config space and therefore 2605 * it doesn't require a re-enumeration of the PCI BARs. However, the 2606 * driver-initiated FLR does still cause a reset of both GT and display and a 2607 * memory wipe of local and stolen memory, so recovery would require a full HW 2608 * re-init and saving/restoring (or re-populating) the wiped memory. Since we 2609 * perform the FLR as the very last action before releasing access to the HW 2610 * during the driver release flow, we don't attempt recovery at all, because 2611 * if/when a new instance of i915 is bound to the device it will do a full 2612 * re-init anyway. 2613 */ 2614static void driver_initiated_flr(struct intel_uncore *uncore) 2615{ 2616 struct drm_i915_private *i915 = uncore->i915; 2617 const unsigned int flr_timeout_ms = 3000; /* specs recommend a 3s wait */ 2618 int ret; 2619 2620 drm_dbg(&i915->drm, "Triggering Driver-FLR\n"); 2621 2622 /* 2623 * Make sure any pending FLR requests have cleared by waiting for the 2624 * FLR trigger bit to go to zero. Also clear GU_DEBUG's DRIVERFLR_STATUS 2625 * to make sure it's not still set from a prior attempt (it's a write to 2626 * clear bit). 2627 * Note that we should never be in a situation where a previous attempt 2628 * is still pending (unless the HW is totally dead), but better to be 2629 * safe in case something unexpected happens 2630 */ 2631 ret = intel_wait_for_register_fw(uncore, GU_CNTL, DRIVERFLR, 0, flr_timeout_ms); 2632 if (ret) { 2633 drm_err(&i915->drm, 2634 "Failed to wait for Driver-FLR bit to clear! %d\n", 2635 ret); 2636 return; 2637 } 2638 intel_uncore_write_fw(uncore, GU_DEBUG, DRIVERFLR_STATUS); 2639 2640 /* Trigger the actual Driver-FLR */ 2641 intel_uncore_rmw_fw(uncore, GU_CNTL, 0, DRIVERFLR); 2642 2643 /* Wait for hardware teardown to complete */ 2644 ret = intel_wait_for_register_fw(uncore, GU_CNTL, 2645 DRIVERFLR, 0, 2646 flr_timeout_ms); 2647 if (ret) { 2648 drm_err(&i915->drm, "Driver-FLR-teardown wait completion failed! %d\n", ret); 2649 return; 2650 } 2651 2652 /* Wait for hardware/firmware re-init to complete */ 2653 ret = intel_wait_for_register_fw(uncore, GU_DEBUG, 2654 DRIVERFLR_STATUS, DRIVERFLR_STATUS, 2655 flr_timeout_ms); 2656 if (ret) { 2657 drm_err(&i915->drm, "Driver-FLR-reinit wait completion failed! %d\n", ret); 2658 return; 2659 } 2660 2661 /* Clear sticky completion status */ 2662 intel_uncore_write_fw(uncore, GU_DEBUG, DRIVERFLR_STATUS); 2663} 2664 2665/* Called via drm-managed action */ 2666void intel_uncore_fini_mmio(struct drm_device *dev, void *data) 2667{ 2668 struct intel_uncore *uncore = data; 2669 2670 if (intel_uncore_has_forcewake(uncore)) { 2671 iosf_mbi_punit_acquire(); 2672 iosf_mbi_unregister_pmic_bus_access_notifier_unlocked( 2673 &uncore->pmic_bus_access_nb); 2674 intel_uncore_forcewake_reset(uncore); 2675 intel_uncore_fw_domains_fini(uncore); 2676 iosf_mbi_punit_release(); 2677 } 2678 2679 if (intel_uncore_needs_flr_on_fini(uncore)) 2680 driver_initiated_flr(uncore); 2681} 2682 2683/** 2684 * __intel_wait_for_register_fw - wait until register matches expected state 2685 * @uncore: the struct intel_uncore 2686 * @reg: the register to read 2687 * @mask: mask to apply to register value 2688 * @value: expected value 2689 * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait 2690 * @slow_timeout_ms: slow timeout in millisecond 2691 * @out_value: optional placeholder to hold registry value 2692 * 2693 * This routine waits until the target register @reg contains the expected 2694 * @value after applying the @mask, i.e. it waits until :: 2695 * 2696 * (intel_uncore_read_fw(uncore, reg) & mask) == value 2697 * 2698 * Otherwise, the wait will timeout after @slow_timeout_ms milliseconds. 2699 * For atomic context @slow_timeout_ms must be zero and @fast_timeout_us 2700 * must be not larger than 20,0000 microseconds. 2701 * 2702 * Note that this routine assumes the caller holds forcewake asserted, it is 2703 * not suitable for very long waits. See intel_wait_for_register() if you 2704 * wish to wait without holding forcewake for the duration (i.e. you expect 2705 * the wait to be slow). 2706 * 2707 * Return: 0 if the register matches the desired condition, or -ETIMEDOUT. 2708 */ 2709int __intel_wait_for_register_fw(struct intel_uncore *uncore, 2710 i915_reg_t reg, 2711 u32 mask, 2712 u32 value, 2713 unsigned int fast_timeout_us, 2714 unsigned int slow_timeout_ms, 2715 u32 *out_value) 2716{ 2717 u32 reg_value = 0; 2718#define done (((reg_value = intel_uncore_read_fw(uncore, reg)) & mask) == value) 2719 int ret; 2720 2721 /* Catch any overuse of this function */ 2722 might_sleep_if(slow_timeout_ms); 2723 GEM_BUG_ON(fast_timeout_us > 20000); 2724 GEM_BUG_ON(!fast_timeout_us && !slow_timeout_ms); 2725 2726 ret = -ETIMEDOUT; 2727 if (fast_timeout_us && fast_timeout_us <= 20000) 2728 ret = _wait_for_atomic(done, fast_timeout_us, 0); 2729 if (ret && slow_timeout_ms) 2730 ret = wait_for(done, slow_timeout_ms); 2731 2732 if (out_value) 2733 *out_value = reg_value; 2734 2735 return ret; 2736#undef done 2737} 2738 2739/** 2740 * __intel_wait_for_register - wait until register matches expected state 2741 * @uncore: the struct intel_uncore 2742 * @reg: the register to read 2743 * @mask: mask to apply to register value 2744 * @value: expected value 2745 * @fast_timeout_us: fast timeout in microsecond for atomic/tight wait 2746 * @slow_timeout_ms: slow timeout in millisecond 2747 * @out_value: optional placeholder to hold registry value 2748 * 2749 * This routine waits until the target register @reg contains the expected 2750 * @value after applying the @mask, i.e. it waits until :: 2751 * 2752 * (intel_uncore_read(uncore, reg) & mask) == value 2753 * 2754 * Otherwise, the wait will timeout after @timeout_ms milliseconds. 2755 * 2756 * Return: 0 if the register matches the desired condition, or -ETIMEDOUT. 2757 */ 2758int __intel_wait_for_register(struct intel_uncore *uncore, 2759 i915_reg_t reg, 2760 u32 mask, 2761 u32 value, 2762 unsigned int fast_timeout_us, 2763 unsigned int slow_timeout_ms, 2764 u32 *out_value) 2765{ 2766 unsigned fw = 2767 intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ); 2768 u32 reg_value; 2769 int ret; 2770 2771 might_sleep_if(slow_timeout_ms); 2772 2773 spin_lock_irq(&uncore->lock); 2774 intel_uncore_forcewake_get__locked(uncore, fw); 2775 2776 ret = __intel_wait_for_register_fw(uncore, 2777 reg, mask, value, 2778 fast_timeout_us, 0, ®_value); 2779 2780 intel_uncore_forcewake_put__locked(uncore, fw); 2781 spin_unlock_irq(&uncore->lock); 2782 2783 if (ret && slow_timeout_ms) 2784 ret = __wait_for(reg_value = intel_uncore_read_notrace(uncore, 2785 reg), 2786 (reg_value & mask) == value, 2787 slow_timeout_ms * 1000, 10, 1000); 2788 2789 /* just trace the final value */ 2790 trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true); 2791 2792 if (out_value) 2793 *out_value = reg_value; 2794 2795 return ret; 2796} 2797 2798bool intel_uncore_unclaimed_mmio(struct intel_uncore *uncore) 2799{ 2800 bool ret; 2801 2802 if (!uncore->debug) 2803 return false; 2804 2805 spin_lock_irq(&uncore->debug->lock); 2806 ret = check_for_unclaimed_mmio(uncore); 2807 spin_unlock_irq(&uncore->debug->lock); 2808 2809 return ret; 2810} 2811 2812bool 2813intel_uncore_arm_unclaimed_mmio_detection(struct intel_uncore *uncore) 2814{ 2815 bool ret = false; 2816 2817 if (drm_WARN_ON(&uncore->i915->drm, !uncore->debug)) 2818 return false; 2819 2820 spin_lock_irq(&uncore->debug->lock); 2821 2822 if (unlikely(uncore->debug->unclaimed_mmio_check <= 0)) 2823 goto out; 2824 2825 if (unlikely(check_for_unclaimed_mmio(uncore))) { 2826 if (!uncore->i915->params.mmio_debug) { 2827 drm_dbg(&uncore->i915->drm, 2828 "Unclaimed register detected, " 2829 "enabling oneshot unclaimed register reporting. " 2830 "Please use i915.mmio_debug=N for more information.\n"); 2831 uncore->i915->params.mmio_debug++; 2832 } 2833 uncore->debug->unclaimed_mmio_check--; 2834 ret = true; 2835 } 2836 2837out: 2838 spin_unlock_irq(&uncore->debug->lock); 2839 2840 return ret; 2841} 2842 2843/** 2844 * intel_uncore_forcewake_for_reg - which forcewake domains are needed to access 2845 * a register 2846 * @uncore: pointer to struct intel_uncore 2847 * @reg: register in question 2848 * @op: operation bitmask of FW_REG_READ and/or FW_REG_WRITE 2849 * 2850 * Returns a set of forcewake domains required to be taken with for example 2851 * intel_uncore_forcewake_get for the specified register to be accessible in the 2852 * specified mode (read, write or read/write) with raw mmio accessors. 2853 * 2854 * NOTE: On Gen6 and Gen7 write forcewake domain (FORCEWAKE_RENDER) requires the 2855 * callers to do FIFO management on their own or risk losing writes. 2856 */ 2857enum forcewake_domains 2858intel_uncore_forcewake_for_reg(struct intel_uncore *uncore, 2859 i915_reg_t reg, unsigned int op) 2860{ 2861 enum forcewake_domains fw_domains = 0; 2862 2863 drm_WARN_ON(&uncore->i915->drm, !op); 2864 2865 if (!intel_uncore_has_forcewake(uncore)) 2866 return 0; 2867 2868 if (op & FW_REG_READ) 2869 fw_domains = uncore->funcs.read_fw_domains(uncore, reg); 2870 2871 if (op & FW_REG_WRITE) 2872 fw_domains |= uncore->funcs.write_fw_domains(uncore, reg); 2873 2874 drm_WARN_ON(&uncore->i915->drm, fw_domains & ~uncore->fw_domains); 2875 2876 return fw_domains; 2877} 2878 2879#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) 2880#include "selftests/mock_uncore.c" 2881#include "selftests/intel_uncore.c" 2882#endif 2883