1/* 2 * Copyright �� 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25#include <linux/string_helpers.h> 26 27#include <drm/drm_print.h> 28#include <drm/i915_pciids.h> 29 30#include "gt/intel_gt_regs.h" 31#include "i915_drv.h" 32#include "i915_reg.h" 33#include "i915_utils.h" 34#include "intel_device_info.h" 35 36#define PLATFORM_NAME(x) [INTEL_##x] = #x 37static const char * const platform_names[] = { 38 PLATFORM_NAME(I830), 39 PLATFORM_NAME(I845G), 40 PLATFORM_NAME(I85X), 41 PLATFORM_NAME(I865G), 42 PLATFORM_NAME(I915G), 43 PLATFORM_NAME(I915GM), 44 PLATFORM_NAME(I945G), 45 PLATFORM_NAME(I945GM), 46 PLATFORM_NAME(G33), 47 PLATFORM_NAME(PINEVIEW), 48 PLATFORM_NAME(I965G), 49 PLATFORM_NAME(I965GM), 50 PLATFORM_NAME(G45), 51 PLATFORM_NAME(GM45), 52 PLATFORM_NAME(IRONLAKE), 53 PLATFORM_NAME(SANDYBRIDGE), 54 PLATFORM_NAME(IVYBRIDGE), 55 PLATFORM_NAME(VALLEYVIEW), 56 PLATFORM_NAME(HASWELL), 57 PLATFORM_NAME(BROADWELL), 58 PLATFORM_NAME(CHERRYVIEW), 59 PLATFORM_NAME(SKYLAKE), 60 PLATFORM_NAME(BROXTON), 61 PLATFORM_NAME(KABYLAKE), 62 PLATFORM_NAME(GEMINILAKE), 63 PLATFORM_NAME(COFFEELAKE), 64 PLATFORM_NAME(COMETLAKE), 65 PLATFORM_NAME(ICELAKE), 66 PLATFORM_NAME(ELKHARTLAKE), 67 PLATFORM_NAME(JASPERLAKE), 68 PLATFORM_NAME(TIGERLAKE), 69 PLATFORM_NAME(ROCKETLAKE), 70 PLATFORM_NAME(DG1), 71 PLATFORM_NAME(ALDERLAKE_S), 72 PLATFORM_NAME(ALDERLAKE_P), 73 PLATFORM_NAME(DG2), 74 PLATFORM_NAME(METEORLAKE), 75}; 76#undef PLATFORM_NAME 77 78const char *intel_platform_name(enum intel_platform platform) 79{ 80 BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS); 81 82 if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) || 83 platform_names[platform] == NULL)) 84 return "<unknown>"; 85 86 return platform_names[platform]; 87} 88 89void intel_device_info_print(const struct intel_device_info *info, 90 const struct intel_runtime_info *runtime, 91 struct drm_printer *p) 92{ 93 if (runtime->graphics.ip.rel) 94 drm_printf(p, "graphics version: %u.%02u\n", 95 runtime->graphics.ip.ver, 96 runtime->graphics.ip.rel); 97 else 98 drm_printf(p, "graphics version: %u\n", 99 runtime->graphics.ip.ver); 100 101 if (runtime->media.ip.rel) 102 drm_printf(p, "media version: %u.%02u\n", 103 runtime->media.ip.ver, 104 runtime->media.ip.rel); 105 else 106 drm_printf(p, "media version: %u\n", 107 runtime->media.ip.ver); 108 109 drm_printf(p, "graphics stepping: %s\n", intel_step_name(runtime->step.graphics_step)); 110 drm_printf(p, "media stepping: %s\n", intel_step_name(runtime->step.media_step)); 111 drm_printf(p, "display stepping: %s\n", intel_step_name(runtime->step.display_step)); 112 drm_printf(p, "base die stepping: %s\n", intel_step_name(runtime->step.basedie_step)); 113 114 drm_printf(p, "gt: %d\n", info->gt); 115 drm_printf(p, "memory-regions: 0x%x\n", info->memory_regions); 116 drm_printf(p, "page-sizes: 0x%x\n", runtime->page_sizes); 117 drm_printf(p, "platform: %s\n", intel_platform_name(info->platform)); 118 drm_printf(p, "ppgtt-size: %d\n", runtime->ppgtt_size); 119 drm_printf(p, "ppgtt-type: %d\n", runtime->ppgtt_type); 120 drm_printf(p, "dma_mask_size: %u\n", info->dma_mask_size); 121 122#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->name)) 123 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG); 124#undef PRINT_FLAG 125 126 drm_printf(p, "has_pooled_eu: %s\n", str_yes_no(runtime->has_pooled_eu)); 127 drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq); 128} 129 130#undef INTEL_VGA_DEVICE 131#define INTEL_VGA_DEVICE(id, info) (id) 132 133static const u16 subplatform_ult_ids[] = { 134 INTEL_HSW_ULT_GT1_IDS(0), 135 INTEL_HSW_ULT_GT2_IDS(0), 136 INTEL_HSW_ULT_GT3_IDS(0), 137 INTEL_BDW_ULT_GT1_IDS(0), 138 INTEL_BDW_ULT_GT2_IDS(0), 139 INTEL_BDW_ULT_GT3_IDS(0), 140 INTEL_BDW_ULT_RSVD_IDS(0), 141 INTEL_SKL_ULT_GT1_IDS(0), 142 INTEL_SKL_ULT_GT2_IDS(0), 143 INTEL_SKL_ULT_GT3_IDS(0), 144 INTEL_KBL_ULT_GT1_IDS(0), 145 INTEL_KBL_ULT_GT2_IDS(0), 146 INTEL_KBL_ULT_GT3_IDS(0), 147 INTEL_CFL_U_GT2_IDS(0), 148 INTEL_CFL_U_GT3_IDS(0), 149 INTEL_WHL_U_GT1_IDS(0), 150 INTEL_WHL_U_GT2_IDS(0), 151 INTEL_WHL_U_GT3_IDS(0), 152 INTEL_CML_U_GT1_IDS(0), 153 INTEL_CML_U_GT2_IDS(0), 154}; 155 156static const u16 subplatform_ulx_ids[] = { 157 INTEL_HSW_ULX_GT1_IDS(0), 158 INTEL_HSW_ULX_GT2_IDS(0), 159 INTEL_BDW_ULX_GT1_IDS(0), 160 INTEL_BDW_ULX_GT2_IDS(0), 161 INTEL_BDW_ULX_GT3_IDS(0), 162 INTEL_BDW_ULX_RSVD_IDS(0), 163 INTEL_SKL_ULX_GT1_IDS(0), 164 INTEL_SKL_ULX_GT2_IDS(0), 165 INTEL_KBL_ULX_GT1_IDS(0), 166 INTEL_KBL_ULX_GT2_IDS(0), 167 INTEL_AML_KBL_GT2_IDS(0), 168 INTEL_AML_CFL_GT2_IDS(0), 169}; 170 171static const u16 subplatform_portf_ids[] = { 172 INTEL_ICL_PORT_F_IDS(0), 173}; 174 175static const u16 subplatform_uy_ids[] = { 176 INTEL_TGL_12_GT2_IDS(0), 177}; 178 179static const u16 subplatform_n_ids[] = { 180 INTEL_ADLN_IDS(0), 181}; 182 183static const u16 subplatform_rpl_ids[] = { 184 INTEL_RPLS_IDS(0), 185 INTEL_RPLP_IDS(0), 186}; 187 188static const u16 subplatform_rplu_ids[] = { 189 INTEL_RPLU_IDS(0), 190}; 191 192static const u16 subplatform_g10_ids[] = { 193 INTEL_DG2_G10_IDS(0), 194 INTEL_ATS_M150_IDS(0), 195}; 196 197static const u16 subplatform_g11_ids[] = { 198 INTEL_DG2_G11_IDS(0), 199 INTEL_ATS_M75_IDS(0), 200}; 201 202static const u16 subplatform_g12_ids[] = { 203 INTEL_DG2_G12_IDS(0), 204}; 205 206static bool find_devid(u16 id, const u16 *p, unsigned int num) 207{ 208 for (; num; num--, p++) { 209 if (*p == id) 210 return true; 211 } 212 213 return false; 214} 215 216static void intel_device_info_subplatform_init(struct drm_i915_private *i915) 217{ 218 const struct intel_device_info *info = INTEL_INFO(i915); 219 const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915); 220 const unsigned int pi = __platform_mask_index(rinfo, info->platform); 221 const unsigned int pb = __platform_mask_bit(rinfo, info->platform); 222 u16 devid = INTEL_DEVID(i915); 223 u32 mask = 0; 224 225 /* Make sure IS_<platform> checks are working. */ 226 RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb); 227 228 /* Find and mark subplatform bits based on the PCI device id. */ 229 if (find_devid(devid, subplatform_ult_ids, 230 ARRAY_SIZE(subplatform_ult_ids))) { 231 mask = BIT(INTEL_SUBPLATFORM_ULT); 232 } else if (find_devid(devid, subplatform_ulx_ids, 233 ARRAY_SIZE(subplatform_ulx_ids))) { 234 mask = BIT(INTEL_SUBPLATFORM_ULX); 235 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { 236 /* ULX machines are also considered ULT. */ 237 mask |= BIT(INTEL_SUBPLATFORM_ULT); 238 } 239 } else if (find_devid(devid, subplatform_portf_ids, 240 ARRAY_SIZE(subplatform_portf_ids))) { 241 mask = BIT(INTEL_SUBPLATFORM_PORTF); 242 } else if (find_devid(devid, subplatform_uy_ids, 243 ARRAY_SIZE(subplatform_uy_ids))) { 244 mask = BIT(INTEL_SUBPLATFORM_UY); 245 } else if (find_devid(devid, subplatform_n_ids, 246 ARRAY_SIZE(subplatform_n_ids))) { 247 mask = BIT(INTEL_SUBPLATFORM_N); 248 } else if (find_devid(devid, subplatform_rpl_ids, 249 ARRAY_SIZE(subplatform_rpl_ids))) { 250 mask = BIT(INTEL_SUBPLATFORM_RPL); 251 if (find_devid(devid, subplatform_rplu_ids, 252 ARRAY_SIZE(subplatform_rplu_ids))) 253 mask |= BIT(INTEL_SUBPLATFORM_RPLU); 254 } else if (find_devid(devid, subplatform_g10_ids, 255 ARRAY_SIZE(subplatform_g10_ids))) { 256 mask = BIT(INTEL_SUBPLATFORM_G10); 257 } else if (find_devid(devid, subplatform_g11_ids, 258 ARRAY_SIZE(subplatform_g11_ids))) { 259 mask = BIT(INTEL_SUBPLATFORM_G11); 260 } else if (find_devid(devid, subplatform_g12_ids, 261 ARRAY_SIZE(subplatform_g12_ids))) { 262 mask = BIT(INTEL_SUBPLATFORM_G12); 263 } 264 265 GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK); 266 267 RUNTIME_INFO(i915)->platform_mask[pi] |= mask; 268} 269 270static void ip_ver_read(struct drm_i915_private *i915, u32 offset, struct intel_ip_version *ip) 271{ 272 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 273 void __iomem *addr; 274 u32 val; 275 u8 expected_ver = ip->ver; 276 u8 expected_rel = ip->rel; 277 278 addr = pci_iomap_range(pdev, 0, offset, sizeof(u32)); 279 if (drm_WARN_ON(&i915->drm, !addr)) 280 return; 281 282 val = ioread32(addr); 283 pci_iounmap(pdev, addr); 284 285 ip->ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val); 286 ip->rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val); 287 ip->step = REG_FIELD_GET(GMD_ID_STEP, val); 288 289 /* Sanity check against expected versions from device info */ 290 if (IP_VER(ip->ver, ip->rel) < IP_VER(expected_ver, expected_rel)) 291 drm_dbg(&i915->drm, 292 "Hardware reports GMD IP version %u.%u (REG[0x%x] = 0x%08x) but minimum expected is %u.%u\n", 293 ip->ver, ip->rel, offset, val, expected_ver, expected_rel); 294} 295 296/* 297 * Setup the graphics version for the current device. This must be done before 298 * any code that performs checks on GRAPHICS_VER or DISPLAY_VER, so this 299 * function should be called very early in the driver initialization sequence. 300 * 301 * Regular MMIO access is not yet setup at the point this function is called so 302 * we peek at the appropriate MMIO offset directly. The GMD_ID register is 303 * part of an 'always on' power well by design, so we don't need to worry about 304 * forcewake while reading it. 305 */ 306static void intel_ipver_early_init(struct drm_i915_private *i915) 307{ 308 struct intel_runtime_info *runtime = RUNTIME_INFO(i915); 309 310 if (!HAS_GMD_ID(i915)) { 311 drm_WARN_ON(&i915->drm, RUNTIME_INFO(i915)->graphics.ip.ver > 12); 312 /* 313 * On older platforms, graphics and media share the same ip 314 * version and release. 315 */ 316 RUNTIME_INFO(i915)->media.ip = 317 RUNTIME_INFO(i915)->graphics.ip; 318 return; 319 } 320 321 ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_GRAPHICS), 322 &runtime->graphics.ip); 323 /* Wa_22012778468 */ 324 if (runtime->graphics.ip.ver == 0x0 && 325 INTEL_INFO(i915)->platform == INTEL_METEORLAKE) { 326 RUNTIME_INFO(i915)->graphics.ip.ver = 12; 327 RUNTIME_INFO(i915)->graphics.ip.rel = 70; 328 } 329 ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_MEDIA), 330 &runtime->media.ip); 331} 332 333/** 334 * intel_device_info_runtime_init_early - initialize early runtime info 335 * @i915: the i915 device 336 * 337 * Determine early intel_device_info fields at runtime. This function needs 338 * to be called before the MMIO has been setup. 339 */ 340void intel_device_info_runtime_init_early(struct drm_i915_private *i915) 341{ 342 intel_ipver_early_init(i915); 343 intel_device_info_subplatform_init(i915); 344} 345 346/** 347 * intel_device_info_runtime_init - initialize runtime info 348 * @dev_priv: the i915 device 349 * 350 * Determine various intel_device_info fields at runtime. 351 * 352 * Use it when either: 353 * - it's judged too laborious to fill n static structures with the limit 354 * when a simple if statement does the job, 355 * - run-time checks (eg read fuse/strap registers) are needed. 356 * 357 * This function needs to be called: 358 * - after the MMIO has been setup as we are reading registers, 359 * - after the PCH has been detected, 360 * - before the first usage of the fields it can tweak. 361 */ 362void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) 363{ 364 struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv); 365 366 BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES); 367 368 if (GRAPHICS_VER(dev_priv) == 6 && i915_vtd_active(dev_priv)) { 369 drm_info(&dev_priv->drm, 370 "Disabling ppGTT for VT-d support\n"); 371 runtime->ppgtt_type = INTEL_PPGTT_NONE; 372 } 373 374 runtime->rawclk_freq = intel_read_rawclk(dev_priv); 375 drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq); 376 377} 378 379/* 380 * Set up device info and initial runtime info at driver create. 381 * 382 * Note: i915 is only an allocated blob of memory at this point. 383 */ 384void intel_device_info_driver_create(struct drm_i915_private *i915, 385 u16 device_id, 386 const struct intel_device_info *match_info) 387{ 388 struct intel_runtime_info *runtime; 389 390 /* Setup INTEL_INFO() */ 391 i915->__info = match_info; 392 393 /* Initialize initial runtime info from static const data and pdev. */ 394 runtime = RUNTIME_INFO(i915); 395 memcpy(runtime, &INTEL_INFO(i915)->__runtime, sizeof(*runtime)); 396 397 runtime->device_id = device_id; 398} 399 400void intel_driver_caps_print(const struct intel_driver_caps *caps, 401 struct drm_printer *p) 402{ 403 drm_printf(p, "Has logical contexts? %s\n", 404 str_yes_no(caps->has_logical_contexts)); 405 drm_printf(p, "scheduler: 0x%x\n", caps->scheduler); 406} 407