1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 2 */ 3/* 4 * 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All Rights Reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the 10 * "Software"), to deal in the Software without restriction, including 11 * without limitation the rights to use, copy, modify, merge, publish, 12 * distribute, sub license, and/or sell copies of the Software, and to 13 * permit persons to whom the Software is furnished to do so, subject to 14 * the following conditions: 15 * 16 * The above copyright notice and this permission notice (including the 17 * next paragraph) shall be included in all copies or substantial portions 18 * of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 * 28 */ 29 30#ifndef _I915_DRV_H_ 31#define _I915_DRV_H_ 32 33#include <uapi/drm/i915_drm.h> 34 35#include <linux/pm_qos.h> 36 37#include <drm/ttm/ttm_device.h> 38 39#include "display/intel_display_limits.h" 40#include "display/intel_display_core.h" 41 42#include "gem/i915_gem_context_types.h" 43#include "gem/i915_gem_shrinker.h" 44#include "gem/i915_gem_stolen.h" 45 46#include "gt/intel_engine.h" 47#include "gt/intel_gt_types.h" 48#include "gt/intel_region_lmem.h" 49#include "gt/intel_workarounds.h" 50#include "gt/uc/intel_uc.h" 51 52#include "soc/intel_pch.h" 53 54#include "i915_drm_client.h" 55#include "i915_gem.h" 56#include "i915_gpu_error.h" 57#include "i915_params.h" 58#include "i915_perf_types.h" 59#include "i915_scheduler.h" 60#include "i915_utils.h" 61#include "intel_device_info.h" 62#include "intel_memory_region.h" 63#include "intel_runtime_pm.h" 64#include "intel_step.h" 65#include "intel_uncore.h" 66 67struct drm_i915_clock_gating_funcs; 68struct vlv_s0ix_state; 69struct intel_pxp; 70 71#define GEM_QUIRK_PIN_SWIZZLED_PAGES BIT(0) 72 73/* Data Stolen Memory (DSM) aka "i915 stolen memory" */ 74struct i915_dsm { 75 /* 76 * The start and end of DSM which we can optionally use to create GEM 77 * objects backed by stolen memory. 78 * 79 * Note that usable_size tells us exactly how much of this we are 80 * actually allowed to use, given that some portion of it is in fact 81 * reserved for use by hardware functions. 82 */ 83 struct resource stolen; 84 85 /* 86 * Reserved portion of DSM. 87 */ 88 struct resource reserved; 89 90 /* 91 * Total size minus reserved ranges. 92 * 93 * DSM is segmented in hardware with different portions offlimits to 94 * certain functions. 95 * 96 * The drm_mm is initialised to the total accessible range, as found 97 * from the PCI config. On Broadwell+, this is further restricted to 98 * avoid the first page! The upper end of DSM is reserved for hardware 99 * functions and similarly removed from the accessible range. 100 */ 101 resource_size_t usable_size; 102}; 103 104struct i915_suspend_saved_registers { 105 u32 saveDSPARB; 106 u32 saveSWF0[16]; 107 u32 saveSWF1[16]; 108 u32 saveSWF3[3]; 109 u16 saveGCDGMBUS; 110}; 111 112#define MAX_L3_SLICES 2 113struct intel_l3_parity { 114 u32 *remap_info[MAX_L3_SLICES]; 115 struct work_struct error_work; 116 int which_slice; 117}; 118 119struct i915_gem_mm { 120 /* 121 * Shortcut for the stolen region. This points to either 122 * INTEL_REGION_STOLEN_SMEM for integrated platforms, or 123 * INTEL_REGION_STOLEN_LMEM for discrete, or NULL if the device doesn't 124 * support stolen. 125 */ 126 struct intel_memory_region *stolen_region; 127 /** Memory allocator for GTT stolen memory */ 128 struct drm_mm stolen; 129 /** Protects the usage of the GTT stolen memory allocator. This is 130 * always the inner lock when overlapping with struct_mutex. */ 131 struct mutex stolen_lock; 132 133 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */ 134 spinlock_t obj_lock; 135 136 /** 137 * List of objects which are purgeable. 138 */ 139 struct list_head purge_list; 140 141 /** 142 * List of objects which have allocated pages and are shrinkable. 143 */ 144 struct list_head shrink_list; 145 146 /** 147 * List of objects which are pending destruction. 148 */ 149 struct llist_head free_list; 150 struct work_struct free_work; 151 /** 152 * Count of objects pending destructions. Used to skip needlessly 153 * waiting on an RCU barrier if no objects are waiting to be freed. 154 */ 155 atomic_t free_count; 156 157 /** 158 * tmpfs instance used for shmem backed objects 159 */ 160 struct vfsmount *gemfs; 161 162 struct intel_memory_region *regions[INTEL_REGION_UNKNOWN]; 163 164 struct notifier_block oom_notifier; 165 struct notifier_block vmap_notifier; 166 struct shrinker *shrinker; 167 168 /* shrinker accounting, also useful for userland debugging */ 169 u64 shrink_memory; 170 u32 shrink_count; 171}; 172 173struct i915_virtual_gpu { 174 struct mutex lock; /* serialises sending of g2v_notify command pkts */ 175 bool active; 176 u32 caps; 177 u32 *initial_mmio; 178 u8 *initial_cfg_space; 179 struct list_head entry; 180}; 181 182struct i915_selftest_stash { 183 atomic_t counter; 184 struct ida mock_region_instances; 185}; 186 187struct drm_i915_private { 188 struct drm_device drm; 189 190 struct intel_display display; 191 192 /* FIXME: Device release actions should all be moved to drmm_ */ 193 bool do_release; 194 195 /* i915 device parameters */ 196 struct i915_params params; 197 198 const struct intel_device_info *__info; /* Use INTEL_INFO() to access. */ 199 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */ 200 struct intel_driver_caps caps; 201 202 struct i915_dsm dsm; 203 204 struct intel_uncore uncore; 205 struct intel_uncore_mmio_debug mmio_debug; 206 207 struct i915_virtual_gpu vgpu; 208 209 struct intel_gvt *gvt; 210 211 struct { 212 struct pci_dev *pdev; 213 struct resource mch_res; 214 bool mchbar_need_disable; 215 } gmch; 216 217 /* 218 * Chaining user engines happens in multiple stages, starting with a 219 * simple lock-less linked list created by intel_engine_add_user(), 220 * which later gets sorted and converted to an intermediate regular 221 * list, just to be converted once again to its final rb tree structure 222 * in intel_engines_driver_register(). 223 * 224 * Make sure to use the right iterator helper, depending on if the code 225 * in question runs before or after intel_engines_driver_register() -- 226 * for_each_uabi_engine() can only be used afterwards! 227 */ 228 union { 229 struct llist_head uabi_engines_llist; 230 struct list_head uabi_engines_list; 231 struct rb_root uabi_engines; 232 }; 233 unsigned int engine_uabi_class_count[I915_LAST_UABI_ENGINE_CLASS + 1]; 234 235 /* protects the irq masks */ 236 spinlock_t irq_lock; 237 238 /* Sideband mailbox protection */ 239 struct mutex sb_lock; 240 struct pm_qos_request sb_qos; 241 242 /** Cached value of IMR to avoid reads in updating the bitfield */ 243 u32 irq_mask; 244 245 bool preserve_bios_swizzle; 246 247 unsigned int fsb_freq, mem_freq, is_ddr3; 248 249 unsigned int hpll_freq; 250 unsigned int czclk_freq; 251 252 /** 253 * wq - Driver workqueue for GEM. 254 * 255 * NOTE: Work items scheduled here are not allowed to grab any modeset 256 * locks, for otherwise the flushing done in the pageflip code will 257 * result in deadlocks. 258 */ 259 struct workqueue_struct *wq; 260 261 /** 262 * unordered_wq - internal workqueue for unordered work 263 * 264 * This workqueue should be used for all unordered work 265 * scheduling within i915, which used to be scheduled on the 266 * system_wq before moving to a driver instance due 267 * deprecation of flush_scheduled_work(). 268 */ 269 struct workqueue_struct *unordered_wq; 270 271 /* pm private clock gating functions */ 272 const struct drm_i915_clock_gating_funcs *clock_gating_funcs; 273 274 /* PCH chipset type */ 275 enum intel_pch pch_type; 276 unsigned short pch_id; 277 278 unsigned long gem_quirks; 279 280 struct i915_gem_mm mm; 281 282 struct intel_l3_parity l3_parity; 283 284 /* 285 * edram size in MB. 286 * Cannot be determined by PCIID. You must always read a register. 287 */ 288 u32 edram_size_mb; 289 290 struct i915_gpu_error gpu_error; 291 292 u32 suspend_count; 293 struct i915_suspend_saved_registers regfile; 294 struct vlv_s0ix_state *vlv_s0ix_state; 295 296 struct dram_info { 297 bool wm_lv_0_adjust_needed; 298 u8 num_channels; 299 bool symmetric_memory; 300 enum intel_dram_type { 301 INTEL_DRAM_UNKNOWN, 302 INTEL_DRAM_DDR3, 303 INTEL_DRAM_DDR4, 304 INTEL_DRAM_LPDDR3, 305 INTEL_DRAM_LPDDR4, 306 INTEL_DRAM_DDR5, 307 INTEL_DRAM_LPDDR5, 308 } type; 309 u8 num_qgv_points; 310 u8 num_psf_gv_points; 311 } dram_info; 312 313 struct intel_runtime_pm runtime_pm; 314 315 struct i915_perf perf; 316 317 struct i915_hwmon *hwmon; 318 319 struct intel_gt *gt[I915_MAX_GT]; 320 321 struct kobject *sysfs_gt; 322 323 /* Quick lookup of media GT (current platforms only have one) */ 324 struct intel_gt *media_gt; 325 326 struct { 327 struct i915_gem_contexts { 328 spinlock_t lock; /* locks list */ 329 struct list_head list; 330 } contexts; 331 332 /* 333 * We replace the local file with a global mappings as the 334 * backing storage for the mmap is on the device and not 335 * on the struct file, and we do not want to prolong the 336 * lifetime of the local fd. To minimise the number of 337 * anonymous inodes we create, we use a global singleton to 338 * share the global mapping. 339 */ 340 struct file *mmap_singleton; 341 } gem; 342 343 struct intel_pxp *pxp; 344 345 bool irq_enabled; 346 347 struct i915_pmu pmu; 348 349 /* The TTM device structure. */ 350 struct ttm_device bdev; 351 352 I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;) 353 354 /* 355 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch 356 * will be rejected. Instead look for a better place. 357 */ 358}; 359 360static inline struct drm_i915_private *to_i915(const struct drm_device *dev) 361{ 362 return container_of(dev, struct drm_i915_private, drm); 363} 364 365static inline struct drm_i915_private *kdev_to_i915(struct device *kdev) 366{ 367 return dev_get_drvdata(kdev); 368} 369 370static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev) 371{ 372 return pci_get_drvdata(pdev); 373} 374 375static inline struct intel_gt *to_gt(const struct drm_i915_private *i915) 376{ 377 return i915->gt[0]; 378} 379 380#define rb_to_uabi_engine(rb) \ 381 rb_entry_safe(rb, struct intel_engine_cs, uabi_node) 382 383#define for_each_uabi_engine(engine__, i915__) \ 384 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\ 385 (engine__); \ 386 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node))) 387 388#define INTEL_INFO(i915) ((i915)->__info) 389#define RUNTIME_INFO(i915) (&(i915)->__runtime) 390#define DRIVER_CAPS(i915) (&(i915)->caps) 391 392#define INTEL_DEVID(i915) (RUNTIME_INFO(i915)->device_id) 393 394#define IP_VER(ver, rel) ((ver) << 8 | (rel)) 395 396#define GRAPHICS_VER(i915) (RUNTIME_INFO(i915)->graphics.ip.ver) 397#define GRAPHICS_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->graphics.ip.ver, \ 398 RUNTIME_INFO(i915)->graphics.ip.rel) 399#define IS_GRAPHICS_VER(i915, from, until) \ 400 (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until)) 401 402#define MEDIA_VER(i915) (RUNTIME_INFO(i915)->media.ip.ver) 403#define MEDIA_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \ 404 RUNTIME_INFO(i915)->media.ip.rel) 405#define IS_MEDIA_VER(i915, from, until) \ 406 (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until)) 407 408#define INTEL_REVID(i915) (to_pci_dev((i915)->drm.dev)->revision) 409 410#define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step) 411#define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step) 412#define INTEL_MEDIA_STEP(__i915) (RUNTIME_INFO(__i915)->step.media_step) 413#define INTEL_BASEDIE_STEP(__i915) (RUNTIME_INFO(__i915)->step.basedie_step) 414 415#define IS_DISPLAY_STEP(__i915, since, until) \ 416 (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \ 417 INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) < (until)) 418 419#define IS_GRAPHICS_STEP(__i915, since, until) \ 420 (drm_WARN_ON(&(__i915)->drm, INTEL_GRAPHICS_STEP(__i915) == STEP_NONE), \ 421 INTEL_GRAPHICS_STEP(__i915) >= (since) && INTEL_GRAPHICS_STEP(__i915) < (until)) 422 423#define IS_MEDIA_STEP(__i915, since, until) \ 424 (drm_WARN_ON(&(__i915)->drm, INTEL_MEDIA_STEP(__i915) == STEP_NONE), \ 425 INTEL_MEDIA_STEP(__i915) >= (since) && INTEL_MEDIA_STEP(__i915) < (until)) 426 427#define IS_BASEDIE_STEP(__i915, since, until) \ 428 (drm_WARN_ON(&(__i915)->drm, INTEL_BASEDIE_STEP(__i915) == STEP_NONE), \ 429 INTEL_BASEDIE_STEP(__i915) >= (since) && INTEL_BASEDIE_STEP(__i915) < (until)) 430 431static __always_inline unsigned int 432__platform_mask_index(const struct intel_runtime_info *info, 433 enum intel_platform p) 434{ 435 const unsigned int pbits = 436 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 437 438 /* Expand the platform_mask array if this fails. */ 439 BUILD_BUG_ON(INTEL_MAX_PLATFORMS > 440 pbits * ARRAY_SIZE(info->platform_mask)); 441 442 return p / pbits; 443} 444 445static __always_inline unsigned int 446__platform_mask_bit(const struct intel_runtime_info *info, 447 enum intel_platform p) 448{ 449 const unsigned int pbits = 450 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS; 451 452 return p % pbits + INTEL_SUBPLATFORM_BITS; 453} 454 455static inline u32 456intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p) 457{ 458 const unsigned int pi = __platform_mask_index(info, p); 459 460 return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK; 461} 462 463static __always_inline bool 464IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p) 465{ 466 const struct intel_runtime_info *info = RUNTIME_INFO(i915); 467 const unsigned int pi = __platform_mask_index(info, p); 468 const unsigned int pb = __platform_mask_bit(info, p); 469 470 BUILD_BUG_ON(!__builtin_constant_p(p)); 471 472 return info->platform_mask[pi] & BIT(pb); 473} 474 475static __always_inline bool 476IS_SUBPLATFORM(const struct drm_i915_private *i915, 477 enum intel_platform p, unsigned int s) 478{ 479 const struct intel_runtime_info *info = RUNTIME_INFO(i915); 480 const unsigned int pi = __platform_mask_index(info, p); 481 const unsigned int pb = __platform_mask_bit(info, p); 482 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1; 483 const u32 mask = info->platform_mask[pi]; 484 485 BUILD_BUG_ON(!__builtin_constant_p(p)); 486 BUILD_BUG_ON(!__builtin_constant_p(s)); 487 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS); 488 489 /* Shift and test on the MSB position so sign flag can be used. */ 490 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb); 491} 492 493#define IS_MOBILE(i915) (INTEL_INFO(i915)->is_mobile) 494#define IS_DGFX(i915) (INTEL_INFO(i915)->is_dgfx) 495 496#define IS_I830(i915) IS_PLATFORM(i915, INTEL_I830) 497#define IS_I845G(i915) IS_PLATFORM(i915, INTEL_I845G) 498#define IS_I85X(i915) IS_PLATFORM(i915, INTEL_I85X) 499#define IS_I865G(i915) IS_PLATFORM(i915, INTEL_I865G) 500#define IS_I915G(i915) IS_PLATFORM(i915, INTEL_I915G) 501#define IS_I915GM(i915) IS_PLATFORM(i915, INTEL_I915GM) 502#define IS_I945G(i915) IS_PLATFORM(i915, INTEL_I945G) 503#define IS_I945GM(i915) IS_PLATFORM(i915, INTEL_I945GM) 504#define IS_I965G(i915) IS_PLATFORM(i915, INTEL_I965G) 505#define IS_I965GM(i915) IS_PLATFORM(i915, INTEL_I965GM) 506#define IS_G45(i915) IS_PLATFORM(i915, INTEL_G45) 507#define IS_GM45(i915) IS_PLATFORM(i915, INTEL_GM45) 508#define IS_G4X(i915) (IS_G45(i915) || IS_GM45(i915)) 509#define IS_PINEVIEW(i915) IS_PLATFORM(i915, INTEL_PINEVIEW) 510#define IS_G33(i915) IS_PLATFORM(i915, INTEL_G33) 511#define IS_IRONLAKE(i915) IS_PLATFORM(i915, INTEL_IRONLAKE) 512#define IS_IRONLAKE_M(i915) \ 513 (IS_PLATFORM(i915, INTEL_IRONLAKE) && IS_MOBILE(i915)) 514#define IS_SANDYBRIDGE(i915) IS_PLATFORM(i915, INTEL_SANDYBRIDGE) 515#define IS_IVYBRIDGE(i915) IS_PLATFORM(i915, INTEL_IVYBRIDGE) 516#define IS_IVB_GT1(i915) (IS_IVYBRIDGE(i915) && \ 517 INTEL_INFO(i915)->gt == 1) 518#define IS_VALLEYVIEW(i915) IS_PLATFORM(i915, INTEL_VALLEYVIEW) 519#define IS_CHERRYVIEW(i915) IS_PLATFORM(i915, INTEL_CHERRYVIEW) 520#define IS_HASWELL(i915) IS_PLATFORM(i915, INTEL_HASWELL) 521#define IS_BROADWELL(i915) IS_PLATFORM(i915, INTEL_BROADWELL) 522#define IS_SKYLAKE(i915) IS_PLATFORM(i915, INTEL_SKYLAKE) 523#define IS_BROXTON(i915) IS_PLATFORM(i915, INTEL_BROXTON) 524#define IS_KABYLAKE(i915) IS_PLATFORM(i915, INTEL_KABYLAKE) 525#define IS_GEMINILAKE(i915) IS_PLATFORM(i915, INTEL_GEMINILAKE) 526#define IS_COFFEELAKE(i915) IS_PLATFORM(i915, INTEL_COFFEELAKE) 527#define IS_COMETLAKE(i915) IS_PLATFORM(i915, INTEL_COMETLAKE) 528#define IS_ICELAKE(i915) IS_PLATFORM(i915, INTEL_ICELAKE) 529#define IS_JASPERLAKE(i915) IS_PLATFORM(i915, INTEL_JASPERLAKE) 530#define IS_ELKHARTLAKE(i915) IS_PLATFORM(i915, INTEL_ELKHARTLAKE) 531#define IS_TIGERLAKE(i915) IS_PLATFORM(i915, INTEL_TIGERLAKE) 532#define IS_ROCKETLAKE(i915) IS_PLATFORM(i915, INTEL_ROCKETLAKE) 533#define IS_DG1(i915) IS_PLATFORM(i915, INTEL_DG1) 534#define IS_ALDERLAKE_S(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_S) 535#define IS_ALDERLAKE_P(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_P) 536#define IS_DG2(i915) IS_PLATFORM(i915, INTEL_DG2) 537#define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE) 538#define IS_LUNARLAKE(i915) 0 539 540#define IS_DG2_G10(i915) \ 541 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10) 542#define IS_DG2_G11(i915) \ 543 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G11) 544#define IS_DG2_G12(i915) \ 545 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12) 546#define IS_RAPTORLAKE_S(i915) \ 547 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL) 548#define IS_ALDERLAKE_P_N(i915) \ 549 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N) 550#define IS_RAPTORLAKE_P(i915) \ 551 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL) 552#define IS_RAPTORLAKE_U(i915) \ 553 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU) 554#define IS_HASWELL_EARLY_SDV(i915) (IS_HASWELL(i915) && \ 555 (INTEL_DEVID(i915) & 0xFF00) == 0x0C00) 556#define IS_BROADWELL_ULT(i915) \ 557 IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT) 558#define IS_BROADWELL_ULX(i915) \ 559 IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX) 560#define IS_BROADWELL_GT3(i915) (IS_BROADWELL(i915) && \ 561 INTEL_INFO(i915)->gt == 3) 562#define IS_HASWELL_ULT(i915) \ 563 IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT) 564#define IS_HASWELL_GT3(i915) (IS_HASWELL(i915) && \ 565 INTEL_INFO(i915)->gt == 3) 566#define IS_HASWELL_GT1(i915) (IS_HASWELL(i915) && \ 567 INTEL_INFO(i915)->gt == 1) 568/* ULX machines are also considered ULT. */ 569#define IS_HASWELL_ULX(i915) \ 570 IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX) 571#define IS_SKYLAKE_ULT(i915) \ 572 IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT) 573#define IS_SKYLAKE_ULX(i915) \ 574 IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX) 575#define IS_KABYLAKE_ULT(i915) \ 576 IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT) 577#define IS_KABYLAKE_ULX(i915) \ 578 IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX) 579#define IS_SKYLAKE_GT2(i915) (IS_SKYLAKE(i915) && \ 580 INTEL_INFO(i915)->gt == 2) 581#define IS_SKYLAKE_GT3(i915) (IS_SKYLAKE(i915) && \ 582 INTEL_INFO(i915)->gt == 3) 583#define IS_SKYLAKE_GT4(i915) (IS_SKYLAKE(i915) && \ 584 INTEL_INFO(i915)->gt == 4) 585#define IS_KABYLAKE_GT2(i915) (IS_KABYLAKE(i915) && \ 586 INTEL_INFO(i915)->gt == 2) 587#define IS_KABYLAKE_GT3(i915) (IS_KABYLAKE(i915) && \ 588 INTEL_INFO(i915)->gt == 3) 589#define IS_COFFEELAKE_ULT(i915) \ 590 IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT) 591#define IS_COFFEELAKE_ULX(i915) \ 592 IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX) 593#define IS_COFFEELAKE_GT2(i915) (IS_COFFEELAKE(i915) && \ 594 INTEL_INFO(i915)->gt == 2) 595#define IS_COFFEELAKE_GT3(i915) (IS_COFFEELAKE(i915) && \ 596 INTEL_INFO(i915)->gt == 3) 597 598#define IS_COMETLAKE_ULT(i915) \ 599 IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT) 600#define IS_COMETLAKE_ULX(i915) \ 601 IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX) 602#define IS_COMETLAKE_GT2(i915) (IS_COMETLAKE(i915) && \ 603 INTEL_INFO(i915)->gt == 2) 604 605#define IS_ICL_WITH_PORT_F(i915) \ 606 IS_SUBPLATFORM(i915, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF) 607 608#define IS_TIGERLAKE_UY(i915) \ 609 IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY) 610 611#define IS_LP(i915) (INTEL_INFO(i915)->is_lp) 612#define IS_GEN9_LP(i915) (GRAPHICS_VER(i915) == 9 && IS_LP(i915)) 613#define IS_GEN9_BC(i915) (GRAPHICS_VER(i915) == 9 && !IS_LP(i915)) 614 615#define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id)) 616#define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id) 617 618#define __ENGINE_INSTANCES_MASK(mask, first, count) ({ \ 619 unsigned int first__ = (first); \ 620 unsigned int count__ = (count); \ 621 ((mask) & GENMASK(first__ + count__ - 1, first__)) >> first__; \ 622}) 623 624#define ENGINE_INSTANCES_MASK(gt, first, count) \ 625 __ENGINE_INSTANCES_MASK((gt)->info.engine_mask, first, count) 626 627#define RCS_MASK(gt) \ 628 ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS) 629#define BCS_MASK(gt) \ 630 ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS) 631#define VDBOX_MASK(gt) \ 632 ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS) 633#define VEBOX_MASK(gt) \ 634 ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS) 635#define CCS_MASK(gt) \ 636 ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS) 637 638#define HAS_MEDIA_RATIO_MODE(i915) (INTEL_INFO(i915)->has_media_ratio_mode) 639 640/* 641 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution 642 * All later gens can run the final buffer from the ppgtt 643 */ 644#define CMDPARSER_USES_GGTT(i915) (GRAPHICS_VER(i915) == 7) 645 646#define HAS_LLC(i915) (INTEL_INFO(i915)->has_llc) 647#define HAS_SNOOP(i915) (INTEL_INFO(i915)->has_snoop) 648#define HAS_EDRAM(i915) ((i915)->edram_size_mb) 649#define HAS_SECURE_BATCHES(i915) (GRAPHICS_VER(i915) < 6) 650#define HAS_WT(i915) HAS_EDRAM(i915) 651 652#define HWS_NEEDS_PHYSICAL(i915) (INTEL_INFO(i915)->hws_needs_physical) 653 654#define HAS_LOGICAL_RING_CONTEXTS(i915) \ 655 (INTEL_INFO(i915)->has_logical_ring_contexts) 656#define HAS_LOGICAL_RING_ELSQ(i915) \ 657 (INTEL_INFO(i915)->has_logical_ring_elsq) 658 659#define HAS_EXECLISTS(i915) HAS_LOGICAL_RING_CONTEXTS(i915) 660 661#define INTEL_PPGTT(i915) (RUNTIME_INFO(i915)->ppgtt_type) 662#define HAS_PPGTT(i915) \ 663 (INTEL_PPGTT(i915) != INTEL_PPGTT_NONE) 664#define HAS_FULL_PPGTT(i915) \ 665 (INTEL_PPGTT(i915) >= INTEL_PPGTT_FULL) 666 667#define HAS_PAGE_SIZES(i915, sizes) ({ \ 668 GEM_BUG_ON((sizes) == 0); \ 669 ((sizes) & ~RUNTIME_INFO(i915)->page_sizes) == 0; \ 670}) 671 672/* Early gen2 have a totally busted CS tlb and require pinned batches. */ 673#define HAS_BROKEN_CS_TLB(i915) (IS_I830(i915) || IS_I845G(i915)) 674 675#define NEEDS_RC6_CTX_CORRUPTION_WA(i915) \ 676 (IS_BROADWELL(i915) || GRAPHICS_VER(i915) == 9) 677 678/* WaRsDisableCoarsePowerGating:skl,cnl */ 679#define NEEDS_WaRsDisableCoarsePowerGating(i915) \ 680 (IS_SKYLAKE_GT3(i915) || IS_SKYLAKE_GT4(i915)) 681 682/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 683 * rows, which changed the alignment requirements and fence programming. 684 */ 685#define HAS_128_BYTE_Y_TILING(i915) (GRAPHICS_VER(i915) != 2 && \ 686 !(IS_I915G(i915) || IS_I915GM(i915))) 687 688#define HAS_RC6(i915) (INTEL_INFO(i915)->has_rc6) 689#define HAS_RC6p(i915) (INTEL_INFO(i915)->has_rc6p) 690#define HAS_RC6pp(i915) (false) /* HW was never validated */ 691 692#define HAS_RPS(i915) (INTEL_INFO(i915)->has_rps) 693 694#define HAS_HECI_PXP(i915) \ 695 (INTEL_INFO(i915)->has_heci_pxp) 696 697#define HAS_HECI_GSCFI(i915) \ 698 (INTEL_INFO(i915)->has_heci_gscfi) 699 700#define HAS_HECI_GSC(i915) (HAS_HECI_PXP(i915) || HAS_HECI_GSCFI(i915)) 701 702#define HAS_RUNTIME_PM(i915) (INTEL_INFO(i915)->has_runtime_pm) 703#define HAS_64BIT_RELOC(i915) (INTEL_INFO(i915)->has_64bit_reloc) 704 705#define HAS_OA_BPC_REPORTING(i915) \ 706 (INTEL_INFO(i915)->has_oa_bpc_reporting) 707#define HAS_OA_SLICE_CONTRIB_LIMITS(i915) \ 708 (INTEL_INFO(i915)->has_oa_slice_contrib_limits) 709#define HAS_OAM(i915) \ 710 (INTEL_INFO(i915)->has_oam) 711 712/* 713 * Set this flag, when platform requires 64K GTT page sizes or larger for 714 * device local memory access. 715 */ 716#define HAS_64K_PAGES(i915) (INTEL_INFO(i915)->has_64k_pages) 717 718#define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i)) 719#define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM) 720 721#define HAS_EXTRA_GT_LIST(i915) (INTEL_INFO(i915)->extra_gt_list) 722 723/* 724 * Platform has the dedicated compression control state for each lmem surfaces 725 * stored in lmem to support the 3D and media compression formats. 726 */ 727#define HAS_FLAT_CCS(i915) (INTEL_INFO(i915)->has_flat_ccs) 728 729#define HAS_GT_UC(i915) (INTEL_INFO(i915)->has_gt_uc) 730 731#define HAS_POOLED_EU(i915) (RUNTIME_INFO(i915)->has_pooled_eu) 732 733#define HAS_GLOBAL_MOCS_REGISTERS(i915) (INTEL_INFO(i915)->has_global_mocs) 734 735#define HAS_GMD_ID(i915) (INTEL_INFO(i915)->has_gmd_id) 736 737#define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read) 738 739/* DPF == dynamic parity feature */ 740#define HAS_L3_DPF(i915) (INTEL_INFO(i915)->has_l3_dpf) 741#define NUM_L3_SLICES(i915) (IS_HASWELL_GT3(i915) ? \ 742 2 : HAS_L3_DPF(i915)) 743 744#define HAS_GUC_DEPRIVILEGE(i915) \ 745 (INTEL_INFO(i915)->has_guc_deprivilege) 746 747#define HAS_GUC_TLB_INVALIDATION(i915) (INTEL_INFO(i915)->has_guc_tlb_invalidation) 748 749#define HAS_3D_PIPELINE(i915) (INTEL_INFO(i915)->has_3d_pipeline) 750 751#define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit) 752 753#define HAS_LMEMBAR_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \ 754 GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) 755 756#endif 757