1238384Sjkim/* 2238384Sjkim * Copyright 2018 Advanced Micro Devices, Inc. 3238384Sjkim * 4238384Sjkim * Permission is hereby granted, free of charge, to any person obtaining a 5238384Sjkim * copy of this software and associated documentation files (the "Software"), 6238384Sjkim * to deal in the Software without restriction, including without limitation 7238384Sjkim * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8238384Sjkim * and/or sell copies of the Software, and to permit persons to whom the 9238384Sjkim * Software is furnished to do so, subject to the following conditions: 10238384Sjkim * 11238384Sjkim * The above copyright notice and this permission notice shall be included in 12238384Sjkim * all copies or substantial portions of the Software. 13238384Sjkim * 14238384Sjkim * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15238384Sjkim * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16238384Sjkim * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17238384Sjkim * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18238384Sjkim * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19238384Sjkim * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20238384Sjkim * OTHER DEALINGS IN THE SOFTWARE. 21238384Sjkim * 22238384Sjkim * Authors: AMD 23238384Sjkim * 24238384Sjkim */ 25238384Sjkim 26238384Sjkim/* 27238384Sjkim * Pre-requisites: headers required by header of this unit 28238384Sjkim */ 29238384Sjkim#include "hw_translate_dcn21.h" 30238384Sjkim 31238384Sjkim#include "dm_services.h" 32238384Sjkim#include "include/gpio_types.h" 33238384Sjkim#include "../hw_translate.h" 34238384Sjkim 35238384Sjkim#include "dcn/dcn_2_1_0_offset.h" 36238384Sjkim#include "dcn/dcn_2_1_0_sh_mask.h" 37238384Sjkim#include "renoir_ip_offset.h" 38238384Sjkim 39238384Sjkim 40238384Sjkim 41238384Sjkim 42238384Sjkim/* begin ********************* 43238384Sjkim * macros to expend register list macro defined in HW object header file */ 44238384Sjkim 45238384Sjkim/* DCN */ 46238384Sjkim#define block HPD 47238384Sjkim#define reg_num 0 48238384Sjkim 49238384Sjkim#undef BASE_INNER 50238384Sjkim#define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg 51238384Sjkim 52238384Sjkim#define BASE(seg) BASE_INNER(seg) 53238384Sjkim 54238384Sjkim#undef REG 55238384Sjkim#define REG(reg_name)\ 56238384Sjkim BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name 57238384Sjkim#define SF_HPD(reg_name, field_name, post_fix)\ 58238384Sjkim .field_name = reg_name ## __ ## field_name ## post_fix 59238384Sjkim 60238384Sjkim/* macros to expend register list macro defined in HW object header file 61238384Sjkim * end *********************/ 62238384Sjkim 63238384Sjkim 64238384Sjkimstatic bool offset_to_id( 65238384Sjkim uint32_t offset, 66238384Sjkim uint32_t mask, 67238384Sjkim enum gpio_id *id, 68238384Sjkim uint32_t *en) 69238384Sjkim{ 70238384Sjkim switch (offset) { 71238384Sjkim /* GENERIC */ 72238384Sjkim case REG(DC_GPIO_GENERIC_A): 73238384Sjkim *id = GPIO_ID_GENERIC; 74238384Sjkim switch (mask) { 75238384Sjkim case DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK: 76238384Sjkim *en = GPIO_GENERIC_A; 77238384Sjkim return true; 78238384Sjkim case DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK: 79238384Sjkim *en = GPIO_GENERIC_B; 80238384Sjkim return true; 81238384Sjkim case DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK: 82238384Sjkim *en = GPIO_GENERIC_C; 83238384Sjkim return true; 84238384Sjkim case DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK: 85238384Sjkim *en = GPIO_GENERIC_D; 86238384Sjkim return true; 87238384Sjkim case DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK: 88238384Sjkim *en = GPIO_GENERIC_E; 89238384Sjkim return true; 90238384Sjkim case DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK: 91238384Sjkim *en = GPIO_GENERIC_F; 92238384Sjkim return true; 93238384Sjkim case DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK: 94238384Sjkim *en = GPIO_GENERIC_G; 95238384Sjkim return true; 96238384Sjkim default: 97238384Sjkim ASSERT_CRITICAL(false); 98238384Sjkim return false; 99238384Sjkim } 100238384Sjkim break; 101238384Sjkim /* HPD */ 102238384Sjkim case REG(DC_GPIO_HPD_A): 103238384Sjkim *id = GPIO_ID_HPD; 104238384Sjkim switch (mask) { 105238384Sjkim case DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK: 106238384Sjkim *en = GPIO_HPD_1; 107238384Sjkim return true; 108238384Sjkim case DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK: 109238384Sjkim *en = GPIO_HPD_2; 110238384Sjkim return true; 111238384Sjkim case DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK: 112238384Sjkim *en = GPIO_HPD_3; 113238384Sjkim return true; 114238384Sjkim case DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK: 115238384Sjkim *en = GPIO_HPD_4; 116238384Sjkim return true; 117238384Sjkim case DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK: 118238384Sjkim *en = GPIO_HPD_5; 119238384Sjkim return true; 120238384Sjkim case DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK: 121238384Sjkim *en = GPIO_HPD_6; 122238384Sjkim return true; 123238384Sjkim default: 124238384Sjkim ASSERT_CRITICAL(false); 125238384Sjkim return false; 126238384Sjkim } 127238384Sjkim break; 128238384Sjkim /* REG(DC_GPIO_GENLK_MASK */ 129238384Sjkim case REG(DC_GPIO_GENLK_A): 130238384Sjkim *id = GPIO_ID_GSL; 131238384Sjkim switch (mask) { 132238384Sjkim case DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK: 133238384Sjkim *en = GPIO_GSL_GENLOCK_CLOCK; 134238384Sjkim return true; 135238384Sjkim case DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK: 136238384Sjkim *en = GPIO_GSL_GENLOCK_VSYNC; 137238384Sjkim return true; 138238384Sjkim case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK: 139238384Sjkim *en = GPIO_GSL_SWAPLOCK_A; 140238384Sjkim return true; 141238384Sjkim case DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK: 142238384Sjkim *en = GPIO_GSL_SWAPLOCK_B; 143238384Sjkim return true; 144238384Sjkim default: 145238384Sjkim ASSERT_CRITICAL(false); 146238384Sjkim return false; 147238384Sjkim } 148238384Sjkim break; 149238384Sjkim /* DDC */ 150238384Sjkim /* we don't care about the GPIO_ID for DDC 151238384Sjkim * in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK 152238384Sjkim * directly in the create method 153238384Sjkim */ 154238384Sjkim case REG(DC_GPIO_DDC1_A): 155238384Sjkim *en = GPIO_DDC_LINE_DDC1; 156238384Sjkim return true; 157238384Sjkim case REG(DC_GPIO_DDC2_A): 158238384Sjkim *en = GPIO_DDC_LINE_DDC2; 159238384Sjkim return true; 160238384Sjkim case REG(DC_GPIO_DDC3_A): 161238384Sjkim *en = GPIO_DDC_LINE_DDC3; 162238384Sjkim return true; 163238384Sjkim case REG(DC_GPIO_DDC4_A): 164238384Sjkim *en = GPIO_DDC_LINE_DDC4; 165238384Sjkim return true; 166238384Sjkim case REG(DC_GPIO_DDC5_A): 167238384Sjkim *en = GPIO_DDC_LINE_DDC5; 168238384Sjkim return true; 169238384Sjkim case REG(DC_GPIO_DDCVGA_A): 170238384Sjkim *en = GPIO_DDC_LINE_DDC_VGA; 171238384Sjkim return true; 172238384Sjkim 173238384Sjkim/* 174238384Sjkim * case REG(DC_GPIO_I2CPAD_A): not exit 175238384Sjkim * case REG(DC_GPIO_PWRSEQ_A): 176238384Sjkim * case REG(DC_GPIO_PAD_STRENGTH_1): 177238384Sjkim * case REG(DC_GPIO_PAD_STRENGTH_2): 178238384Sjkim * case REG(DC_GPIO_DEBUG): 179238384Sjkim */ 180238384Sjkim /* UNEXPECTED */ 181238384Sjkim default: 182238384Sjkim/* case REG(DC_GPIO_SYNCA_A): not exista */ 183238384Sjkim ASSERT_CRITICAL(false); 184238384Sjkim return false; 185238384Sjkim } 186238384Sjkim} 187238384Sjkim 188238384Sjkimstatic bool id_to_offset( 189238384Sjkim enum gpio_id id, 190238384Sjkim uint32_t en, 191238384Sjkim struct gpio_pin_info *info) 192238384Sjkim{ 193238384Sjkim bool result = true; 194238384Sjkim 195238384Sjkim switch (id) { 196238384Sjkim case GPIO_ID_DDC_DATA: 197238384Sjkim info->mask = DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK; 198238384Sjkim switch (en) { 199238384Sjkim case GPIO_DDC_LINE_DDC1: 200238384Sjkim info->offset = REG(DC_GPIO_DDC1_A); 201238384Sjkim break; 202238384Sjkim case GPIO_DDC_LINE_DDC2: 203238384Sjkim info->offset = REG(DC_GPIO_DDC2_A); 204238384Sjkim break; 205238384Sjkim case GPIO_DDC_LINE_DDC3: 206238384Sjkim info->offset = REG(DC_GPIO_DDC3_A); 207238384Sjkim break; 208238384Sjkim case GPIO_DDC_LINE_DDC4: 209238384Sjkim info->offset = REG(DC_GPIO_DDC4_A); 210238384Sjkim break; 211238384Sjkim case GPIO_DDC_LINE_DDC5: 212238384Sjkim info->offset = REG(DC_GPIO_DDC5_A); 213238384Sjkim break; 214238384Sjkim case GPIO_DDC_LINE_DDC_VGA: 215238384Sjkim info->offset = REG(DC_GPIO_DDCVGA_A); 216238384Sjkim break; 217238384Sjkim case GPIO_DDC_LINE_I2C_PAD: 218238384Sjkim default: 219238384Sjkim ASSERT_CRITICAL(false); 220238384Sjkim result = false; 221238384Sjkim } 222238384Sjkim break; 223238384Sjkim case GPIO_ID_DDC_CLOCK: 224238384Sjkim info->mask = DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK; 225238384Sjkim switch (en) { 226238384Sjkim case GPIO_DDC_LINE_DDC1: 227238384Sjkim info->offset = REG(DC_GPIO_DDC1_A); 228238384Sjkim break; 229238384Sjkim case GPIO_DDC_LINE_DDC2: 230238384Sjkim info->offset = REG(DC_GPIO_DDC2_A); 231238384Sjkim break; 232238384Sjkim case GPIO_DDC_LINE_DDC3: 233238384Sjkim info->offset = REG(DC_GPIO_DDC3_A); 234238384Sjkim break; 235238384Sjkim case GPIO_DDC_LINE_DDC4: 236238384Sjkim info->offset = REG(DC_GPIO_DDC4_A); 237238384Sjkim break; 238238384Sjkim case GPIO_DDC_LINE_DDC5: 239238384Sjkim info->offset = REG(DC_GPIO_DDC5_A); 240238384Sjkim break; 241238384Sjkim case GPIO_DDC_LINE_DDC_VGA: 242238384Sjkim info->offset = REG(DC_GPIO_DDCVGA_A); 243238384Sjkim break; 244238384Sjkim case GPIO_DDC_LINE_I2C_PAD: 245238384Sjkim default: 246238384Sjkim ASSERT_CRITICAL(false); 247238384Sjkim result = false; 248238384Sjkim } 249238384Sjkim break; 250238384Sjkim case GPIO_ID_GENERIC: 251238384Sjkim info->offset = REG(DC_GPIO_GENERIC_A); 252238384Sjkim switch (en) { 253238384Sjkim case GPIO_GENERIC_A: 254238384Sjkim info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK; 255238384Sjkim break; 256238384Sjkim case GPIO_GENERIC_B: 257238384Sjkim info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK; 258238384Sjkim break; 259238384Sjkim case GPIO_GENERIC_C: 260238384Sjkim info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK; 261238384Sjkim break; 262238384Sjkim case GPIO_GENERIC_D: 263238384Sjkim info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK; 264238384Sjkim break; 265238384Sjkim case GPIO_GENERIC_E: 266238384Sjkim info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK; 267238384Sjkim break; 268238384Sjkim case GPIO_GENERIC_F: 269238384Sjkim info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK; 270238384Sjkim break; 271238384Sjkim case GPIO_GENERIC_G: 272238384Sjkim info->mask = DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK; 273238384Sjkim break; 274238384Sjkim default: 275238384Sjkim ASSERT_CRITICAL(false); 276238384Sjkim result = false; 277238384Sjkim } 278238384Sjkim break; 279238384Sjkim case GPIO_ID_HPD: 280238384Sjkim info->offset = REG(DC_GPIO_HPD_A); 281238384Sjkim switch (en) { 282238384Sjkim case GPIO_HPD_1: 283238384Sjkim info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK; 284238384Sjkim break; 285238384Sjkim case GPIO_HPD_2: 286238384Sjkim info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK; 287238384Sjkim break; 288238384Sjkim case GPIO_HPD_3: 289238384Sjkim info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK; 290238384Sjkim break; 291238384Sjkim case GPIO_HPD_4: 292 info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK; 293 break; 294 case GPIO_HPD_5: 295 info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK; 296 break; 297 case GPIO_HPD_6: 298 info->mask = DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK; 299 break; 300 default: 301 ASSERT_CRITICAL(false); 302 result = false; 303 } 304 break; 305 case GPIO_ID_GSL: 306 switch (en) { 307 case GPIO_GSL_GENLOCK_CLOCK: 308 /*not implmented*/ 309 ASSERT_CRITICAL(false); 310 result = false; 311 break; 312 case GPIO_GSL_GENLOCK_VSYNC: 313 /*not implmented*/ 314 ASSERT_CRITICAL(false); 315 result = false; 316 break; 317 case GPIO_GSL_SWAPLOCK_A: 318 /*not implmented*/ 319 ASSERT_CRITICAL(false); 320 result = false; 321 break; 322 case GPIO_GSL_SWAPLOCK_B: 323 /*not implmented*/ 324 ASSERT_CRITICAL(false); 325 result = false; 326 327 break; 328 default: 329 ASSERT_CRITICAL(false); 330 result = false; 331 } 332 break; 333 case GPIO_ID_SYNC: 334 case GPIO_ID_VIP_PAD: 335 default: 336 ASSERT_CRITICAL(false); 337 result = false; 338 } 339 340 if (result) { 341 info->offset_y = info->offset + 2; 342 info->offset_en = info->offset + 1; 343 info->offset_mask = info->offset - 1; 344 345 info->mask_y = info->mask; 346 info->mask_en = info->mask; 347 info->mask_mask = info->mask; 348 } 349 350 return result; 351} 352 353/* function table */ 354static const struct hw_translate_funcs funcs = { 355 .offset_to_id = offset_to_id, 356 .id_to_offset = id_to_offset, 357}; 358 359/* 360 * dal_hw_translate_dcn10_init 361 * 362 * @brief 363 * Initialize Hw translate function pointers. 364 * 365 * @param 366 * struct hw_translate *tr - [out] struct of function pointers 367 * 368 */ 369void dal_hw_translate_dcn21_init(struct hw_translate *tr) 370{ 371 tr->funcs = &funcs; 372} 373 374