1// SPDX-License-Identifier: GPL-2.0
2/*
3 * GPIO interface for Intel Poulsbo SCH
4 *
5 *  Copyright (c) 2010 CompuLab Ltd
6 *  Author: Denis Turischev <denis@compulab.co.il>
7 */
8
9#include <linux/acpi.h>
10#include <linux/bitops.h>
11#include <linux/errno.h>
12#include <linux/gpio/driver.h>
13#include <linux/io.h>
14#include <linux/irq.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/pci_ids.h>
18#include <linux/platform_device.h>
19#include <linux/types.h>
20
21#define GEN	0x00
22#define GIO	0x04
23#define GLV	0x08
24#define GTPE	0x0c
25#define GTNE	0x10
26#define GGPE	0x14
27#define GSMI	0x18
28#define GTS	0x1c
29
30#define CORE_BANK_OFFSET	0x00
31#define RESUME_BANK_OFFSET	0x20
32
33/*
34 * iLB datasheet describes GPE0BLK registers, in particular GPE0E.GPIO bit.
35 * Document Number: 328195-001
36 */
37#define GPE0E_GPIO	14
38
39struct sch_gpio {
40	struct gpio_chip chip;
41	void __iomem *regs;
42	spinlock_t lock;
43	unsigned short resume_base;
44
45	/* GPE handling */
46	u32 gpe;
47	acpi_gpe_handler gpe_handler;
48};
49
50static unsigned int sch_gpio_offset(struct sch_gpio *sch, unsigned int gpio,
51				unsigned int reg)
52{
53	unsigned int base = CORE_BANK_OFFSET;
54
55	if (gpio >= sch->resume_base) {
56		gpio -= sch->resume_base;
57		base = RESUME_BANK_OFFSET;
58	}
59
60	return base + reg + gpio / 8;
61}
62
63static unsigned int sch_gpio_bit(struct sch_gpio *sch, unsigned int gpio)
64{
65	if (gpio >= sch->resume_base)
66		gpio -= sch->resume_base;
67	return gpio % 8;
68}
69
70static int sch_gpio_reg_get(struct sch_gpio *sch, unsigned int gpio, unsigned int reg)
71{
72	unsigned short offset, bit;
73	u8 reg_val;
74
75	offset = sch_gpio_offset(sch, gpio, reg);
76	bit = sch_gpio_bit(sch, gpio);
77
78	reg_val = !!(ioread8(sch->regs + offset) & BIT(bit));
79
80	return reg_val;
81}
82
83static void sch_gpio_reg_set(struct sch_gpio *sch, unsigned int gpio, unsigned int reg,
84			     int val)
85{
86	unsigned short offset, bit;
87	u8 reg_val;
88
89	offset = sch_gpio_offset(sch, gpio, reg);
90	bit = sch_gpio_bit(sch, gpio);
91
92	reg_val = ioread8(sch->regs + offset);
93
94	if (val)
95		reg_val |= BIT(bit);
96	else
97		reg_val &= ~BIT(bit);
98
99	iowrite8(reg_val, sch->regs + offset);
100}
101
102static int sch_gpio_direction_in(struct gpio_chip *gc, unsigned int gpio_num)
103{
104	struct sch_gpio *sch = gpiochip_get_data(gc);
105	unsigned long flags;
106
107	spin_lock_irqsave(&sch->lock, flags);
108	sch_gpio_reg_set(sch, gpio_num, GIO, 1);
109	spin_unlock_irqrestore(&sch->lock, flags);
110	return 0;
111}
112
113static int sch_gpio_get(struct gpio_chip *gc, unsigned int gpio_num)
114{
115	struct sch_gpio *sch = gpiochip_get_data(gc);
116
117	return sch_gpio_reg_get(sch, gpio_num, GLV);
118}
119
120static void sch_gpio_set(struct gpio_chip *gc, unsigned int gpio_num, int val)
121{
122	struct sch_gpio *sch = gpiochip_get_data(gc);
123	unsigned long flags;
124
125	spin_lock_irqsave(&sch->lock, flags);
126	sch_gpio_reg_set(sch, gpio_num, GLV, val);
127	spin_unlock_irqrestore(&sch->lock, flags);
128}
129
130static int sch_gpio_direction_out(struct gpio_chip *gc, unsigned int gpio_num,
131				  int val)
132{
133	struct sch_gpio *sch = gpiochip_get_data(gc);
134	unsigned long flags;
135
136	spin_lock_irqsave(&sch->lock, flags);
137	sch_gpio_reg_set(sch, gpio_num, GIO, 0);
138	spin_unlock_irqrestore(&sch->lock, flags);
139
140	/*
141	 * according to the datasheet, writing to the level register has no
142	 * effect when GPIO is programmed as input.
143	 * Actually the level register is read-only when configured as input.
144	 * Thus presetting the output level before switching to output is _NOT_ possible.
145	 * Hence we set the level after configuring the GPIO as output.
146	 * But we cannot prevent a short low pulse if direction is set to high
147	 * and an external pull-up is connected.
148	 */
149	sch_gpio_set(gc, gpio_num, val);
150	return 0;
151}
152
153static int sch_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio_num)
154{
155	struct sch_gpio *sch = gpiochip_get_data(gc);
156
157	if (sch_gpio_reg_get(sch, gpio_num, GIO))
158		return GPIO_LINE_DIRECTION_IN;
159
160	return GPIO_LINE_DIRECTION_OUT;
161}
162
163static const struct gpio_chip sch_gpio_chip = {
164	.label			= "sch_gpio",
165	.owner			= THIS_MODULE,
166	.direction_input	= sch_gpio_direction_in,
167	.get			= sch_gpio_get,
168	.direction_output	= sch_gpio_direction_out,
169	.set			= sch_gpio_set,
170	.get_direction		= sch_gpio_get_direction,
171};
172
173static int sch_irq_type(struct irq_data *d, unsigned int type)
174{
175	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
176	struct sch_gpio *sch = gpiochip_get_data(gc);
177	irq_hw_number_t gpio_num = irqd_to_hwirq(d);
178	unsigned long flags;
179	int rising, falling;
180
181	switch (type & IRQ_TYPE_SENSE_MASK) {
182	case IRQ_TYPE_EDGE_RISING:
183		rising = 1;
184		falling = 0;
185		break;
186	case IRQ_TYPE_EDGE_FALLING:
187		rising = 0;
188		falling = 1;
189		break;
190	case IRQ_TYPE_EDGE_BOTH:
191		rising = 1;
192		falling = 1;
193		break;
194	default:
195		return -EINVAL;
196	}
197
198	spin_lock_irqsave(&sch->lock, flags);
199
200	sch_gpio_reg_set(sch, gpio_num, GTPE, rising);
201	sch_gpio_reg_set(sch, gpio_num, GTNE, falling);
202
203	irq_set_handler_locked(d, handle_edge_irq);
204
205	spin_unlock_irqrestore(&sch->lock, flags);
206
207	return 0;
208}
209
210static void sch_irq_ack(struct irq_data *d)
211{
212	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
213	struct sch_gpio *sch = gpiochip_get_data(gc);
214	irq_hw_number_t gpio_num = irqd_to_hwirq(d);
215	unsigned long flags;
216
217	spin_lock_irqsave(&sch->lock, flags);
218	sch_gpio_reg_set(sch, gpio_num, GTS, 1);
219	spin_unlock_irqrestore(&sch->lock, flags);
220}
221
222static void sch_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t gpio_num, int val)
223{
224	struct sch_gpio *sch = gpiochip_get_data(gc);
225	unsigned long flags;
226
227	spin_lock_irqsave(&sch->lock, flags);
228	sch_gpio_reg_set(sch, gpio_num, GGPE, val);
229	spin_unlock_irqrestore(&sch->lock, flags);
230}
231
232static void sch_irq_mask(struct irq_data *d)
233{
234	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
235	irq_hw_number_t gpio_num = irqd_to_hwirq(d);
236
237	sch_irq_mask_unmask(gc, gpio_num, 0);
238	gpiochip_disable_irq(gc, gpio_num);
239}
240
241static void sch_irq_unmask(struct irq_data *d)
242{
243	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
244	irq_hw_number_t gpio_num = irqd_to_hwirq(d);
245
246	gpiochip_enable_irq(gc, gpio_num);
247	sch_irq_mask_unmask(gc, gpio_num, 1);
248}
249
250static const struct irq_chip sch_irqchip = {
251	.name = "sch_gpio",
252	.irq_ack = sch_irq_ack,
253	.irq_mask = sch_irq_mask,
254	.irq_unmask = sch_irq_unmask,
255	.irq_set_type = sch_irq_type,
256	.flags = IRQCHIP_IMMUTABLE,
257	GPIOCHIP_IRQ_RESOURCE_HELPERS,
258};
259
260static u32 sch_gpio_gpe_handler(acpi_handle gpe_device, u32 gpe, void *context)
261{
262	struct sch_gpio *sch = context;
263	struct gpio_chip *gc = &sch->chip;
264	unsigned long core_status, resume_status;
265	unsigned long pending;
266	unsigned long flags;
267	int offset;
268	u32 ret;
269
270	spin_lock_irqsave(&sch->lock, flags);
271
272	core_status = ioread32(sch->regs + CORE_BANK_OFFSET + GTS);
273	resume_status = ioread32(sch->regs + RESUME_BANK_OFFSET + GTS);
274
275	spin_unlock_irqrestore(&sch->lock, flags);
276
277	pending = (resume_status << sch->resume_base) | core_status;
278	for_each_set_bit(offset, &pending, sch->chip.ngpio)
279		generic_handle_domain_irq(gc->irq.domain, offset);
280
281	/* Set returning value depending on whether we handled an interrupt */
282	ret = pending ? ACPI_INTERRUPT_HANDLED : ACPI_INTERRUPT_NOT_HANDLED;
283
284	/* Acknowledge GPE to ACPICA */
285	ret |= ACPI_REENABLE_GPE;
286
287	return ret;
288}
289
290static void sch_gpio_remove_gpe_handler(void *data)
291{
292	struct sch_gpio *sch = data;
293
294	acpi_disable_gpe(NULL, sch->gpe);
295	acpi_remove_gpe_handler(NULL, sch->gpe, sch->gpe_handler);
296}
297
298static int sch_gpio_install_gpe_handler(struct sch_gpio *sch)
299{
300	struct device *dev = sch->chip.parent;
301	acpi_status status;
302
303	status = acpi_install_gpe_handler(NULL, sch->gpe, ACPI_GPE_LEVEL_TRIGGERED,
304					  sch->gpe_handler, sch);
305	if (ACPI_FAILURE(status)) {
306		dev_err(dev, "Failed to install GPE handler for %u: %s\n",
307			sch->gpe, acpi_format_exception(status));
308		return -ENODEV;
309	}
310
311	status = acpi_enable_gpe(NULL, sch->gpe);
312	if (ACPI_FAILURE(status)) {
313		dev_err(dev, "Failed to enable GPE handler for %u: %s\n",
314			sch->gpe, acpi_format_exception(status));
315		acpi_remove_gpe_handler(NULL, sch->gpe, sch->gpe_handler);
316		return -ENODEV;
317	}
318
319	return devm_add_action_or_reset(dev, sch_gpio_remove_gpe_handler, sch);
320}
321
322static int sch_gpio_probe(struct platform_device *pdev)
323{
324	struct device *dev = &pdev->dev;
325	struct gpio_irq_chip *girq;
326	struct sch_gpio *sch;
327	struct resource *res;
328	void __iomem *regs;
329	int ret;
330
331	sch = devm_kzalloc(dev, sizeof(*sch), GFP_KERNEL);
332	if (!sch)
333		return -ENOMEM;
334
335	res = platform_get_resource(pdev, IORESOURCE_IO, 0);
336	if (!res)
337		return -EBUSY;
338
339	regs = devm_ioport_map(dev, res->start, resource_size(res));
340	if (!regs)
341		return -EBUSY;
342
343	sch->regs = regs;
344
345	spin_lock_init(&sch->lock);
346	sch->chip = sch_gpio_chip;
347	sch->chip.label = dev_name(dev);
348	sch->chip.parent = dev;
349
350	switch (pdev->id) {
351	case PCI_DEVICE_ID_INTEL_SCH_LPC:
352		sch->resume_base = 10;
353		sch->chip.ngpio = 14;
354
355		/*
356		 * GPIO[6:0] enabled by default
357		 * GPIO7 is configured by the CMC as SLPIOVR
358		 * Enable GPIO[9:8] core powered gpios explicitly
359		 */
360		sch_gpio_reg_set(sch, 8, GEN, 1);
361		sch_gpio_reg_set(sch, 9, GEN, 1);
362		/*
363		 * SUS_GPIO[2:0] enabled by default
364		 * Enable SUS_GPIO3 resume powered gpio explicitly
365		 */
366		sch_gpio_reg_set(sch, 13, GEN, 1);
367		break;
368
369	case PCI_DEVICE_ID_INTEL_ITC_LPC:
370		sch->resume_base = 5;
371		sch->chip.ngpio = 14;
372		break;
373
374	case PCI_DEVICE_ID_INTEL_CENTERTON_ILB:
375		sch->resume_base = 21;
376		sch->chip.ngpio = 30;
377		break;
378
379	case PCI_DEVICE_ID_INTEL_QUARK_X1000_ILB:
380		sch->resume_base = 2;
381		sch->chip.ngpio = 8;
382		break;
383
384	default:
385		return -ENODEV;
386	}
387
388	girq = &sch->chip.irq;
389	gpio_irq_chip_set_chip(girq, &sch_irqchip);
390	girq->num_parents = 0;
391	girq->parents = NULL;
392	girq->parent_handler = NULL;
393	girq->default_type = IRQ_TYPE_NONE;
394	girq->handler = handle_bad_irq;
395
396	/* GPE setup is optional */
397	sch->gpe = GPE0E_GPIO;
398	sch->gpe_handler = sch_gpio_gpe_handler;
399
400	ret = sch_gpio_install_gpe_handler(sch);
401	if (ret)
402		dev_warn(dev, "Can't setup GPE, no IRQ support\n");
403
404	return devm_gpiochip_add_data(dev, &sch->chip, sch);
405}
406
407static struct platform_driver sch_gpio_driver = {
408	.driver = {
409		.name = "sch_gpio",
410	},
411	.probe		= sch_gpio_probe,
412};
413
414module_platform_driver(sch_gpio_driver);
415
416MODULE_AUTHOR("Denis Turischev <denis@compulab.co.il>");
417MODULE_DESCRIPTION("GPIO interface for Intel Poulsbo SCH");
418MODULE_LICENSE("GPL v2");
419MODULE_ALIAS("platform:sch_gpio");
420