1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * pata-legacy.c - Legacy port PATA/SATA controller driver. 4 * Copyright 2005/2006 Red Hat, all rights reserved. 5 * 6 * An ATA driver for the legacy ATA ports. 7 * 8 * Data Sources: 9 * Opti 82C465/82C611 support: Data sheets at opti-inc.com 10 * HT6560 series: 11 * Promise 20230/20620: 12 * http://www.ryston.cz/petr/vlb/pdc20230b.html 13 * http://www.ryston.cz/petr/vlb/pdc20230c.html 14 * http://www.ryston.cz/petr/vlb/pdc20630.html 15 * QDI65x0: 16 * http://www.ryston.cz/petr/vlb/qd6500.html 17 * http://www.ryston.cz/petr/vlb/qd6580.html 18 * 19 * QDI65x0 probe code based on drivers/ide/legacy/qd65xx.c 20 * Rewritten from the work of Colten Edwards <pje120@cs.usask.ca> by 21 * Samuel Thibault <samuel.thibault@ens-lyon.org> 22 * 23 * Unsupported but docs exist: 24 * Appian/Adaptec AIC25VL01/Cirrus Logic PD7220 25 * 26 * This driver handles legacy (that is "ISA/VLB side") IDE ports found 27 * on PC class systems. There are three hybrid devices that are exceptions 28 * The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and 29 * the MPIIX where the tuning is PCI side but the IDE is "ISA side". 30 * 31 * Specific support is included for the ht6560a/ht6560b/opti82c611a/ 32 * opti82c465mv/promise 20230c/20630/qdi65x0/winbond83759A 33 * 34 * Support for the Winbond 83759A when operating in advanced mode. 35 * Multichip mode is not currently supported. 36 * 37 * Use the autospeed and pio_mask options with: 38 * Appian ADI/2 aka CLPD7220 or AIC25VL01. 39 * Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with 40 * Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759, 41 * Winbond W83759A, Promise PDC20230-B 42 * 43 * For now use autospeed and pio_mask as above with the W83759A. This may 44 * change. 45 */ 46 47#include <linux/async.h> 48#include <linux/kernel.h> 49#include <linux/module.h> 50#include <linux/pci.h> 51#include <linux/init.h> 52#include <linux/blkdev.h> 53#include <linux/delay.h> 54#include <scsi/scsi_host.h> 55#include <linux/ata.h> 56#include <linux/libata.h> 57#include <linux/platform_device.h> 58 59#define DRV_NAME "pata_legacy" 60#define DRV_VERSION "0.6.5" 61 62#define NR_HOST 6 63 64static int all; 65module_param(all, int, 0444); 66MODULE_PARM_DESC(all, 67 "Set to probe unclaimed pri/sec ISA port ranges even if PCI"); 68 69static int probe_all; 70module_param(probe_all, int, 0); 71MODULE_PARM_DESC(probe_all, 72 "Set to probe tertiary+ ISA port ranges even if PCI"); 73 74static int probe_mask = ~0; 75module_param(probe_mask, int, 0); 76MODULE_PARM_DESC(probe_mask, "Probe mask for legacy ISA PATA ports"); 77 78static int autospeed; 79module_param(autospeed, int, 0); 80MODULE_PARM_DESC(autospeed, "Chip present that snoops speed changes"); 81 82static int pio_mask = ATA_PIO4; 83module_param(pio_mask, int, 0); 84MODULE_PARM_DESC(pio_mask, "PIO range for autospeed devices"); 85 86static int iordy_mask = 0xFFFFFFFF; 87module_param(iordy_mask, int, 0); 88MODULE_PARM_DESC(iordy_mask, "Use IORDY if available"); 89 90static int ht6560a; 91module_param(ht6560a, int, 0); 92MODULE_PARM_DESC(ht6560a, "HT 6560A on primary 1, second 2, both 3"); 93 94static int ht6560b; 95module_param(ht6560b, int, 0); 96MODULE_PARM_DESC(ht6560b, "HT 6560B on primary 1, secondary 2, both 3"); 97 98static int opti82c611a; 99module_param(opti82c611a, int, 0); 100MODULE_PARM_DESC(opti82c611a, 101 "Opti 82c611A on primary 1, secondary 2, both 3"); 102 103static int opti82c46x; 104module_param(opti82c46x, int, 0); 105MODULE_PARM_DESC(opti82c46x, 106 "Opti 82c465MV on primary 1, secondary 2, both 3"); 107 108#ifdef CONFIG_PATA_QDI_MODULE 109static int qdi = 1; 110#else 111static int qdi; 112#endif 113module_param(qdi, int, 0); 114MODULE_PARM_DESC(qdi, "Set to probe QDI controllers"); 115 116#ifdef CONFIG_PATA_WINBOND_VLB_MODULE 117static int winbond = 1; 118#else 119static int winbond; 120#endif 121module_param(winbond, int, 0); 122MODULE_PARM_DESC(winbond, 123 "Set to probe Winbond controllers, " 124 "give I/O port if non standard"); 125 126 127enum controller { 128 BIOS = 0, 129 SNOOP = 1, 130 PDC20230 = 2, 131 HT6560A = 3, 132 HT6560B = 4, 133 OPTI611A = 5, 134 OPTI46X = 6, 135 QDI6500 = 7, 136 QDI6580 = 8, 137 QDI6580DP = 9, /* Dual channel mode is different */ 138 W83759A = 10, 139 140 UNKNOWN = -1 141}; 142 143struct legacy_data { 144 unsigned long timing; 145 u8 clock[2]; 146 u8 last; 147 int fast; 148 enum controller type; 149 struct platform_device *platform_dev; 150}; 151 152struct legacy_probe { 153 unsigned char *name; 154 unsigned long port; 155 unsigned int irq; 156 unsigned int slot; 157 enum controller type; 158 unsigned long private; 159}; 160 161struct legacy_controller { 162 const char *name; 163 struct ata_port_operations *ops; 164 unsigned int pio_mask; 165 unsigned int flags; 166 unsigned int pflags; 167 int (*setup)(struct platform_device *, struct legacy_probe *probe, 168 struct legacy_data *data); 169}; 170 171static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 }; 172 173static struct legacy_probe probe_list[NR_HOST]; 174static struct legacy_data legacy_data[NR_HOST]; 175static struct ata_host *legacy_host[NR_HOST]; 176 177/** 178 * legacy_probe_add - Add interface to probe list 179 * @port: Controller port 180 * @irq: IRQ number 181 * @type: Controller type 182 * @private: Controller specific info 183 * 184 * Add an entry into the probe list for ATA controllers. This is used 185 * to add the default ISA slots and then to build up the table 186 * further according to other ISA/VLB/Weird device scans 187 * 188 * An I/O port list is used to keep ordering stable and sane, as we 189 * don't have any good way to talk about ordering otherwise 190 */ 191 192static int legacy_probe_add(unsigned long port, unsigned int irq, 193 enum controller type, unsigned long private) 194{ 195 struct legacy_probe *lp = &probe_list[0]; 196 int i; 197 struct legacy_probe *free = NULL; 198 199 for (i = 0; i < NR_HOST; i++) { 200 if (lp->port == 0 && free == NULL) 201 free = lp; 202 /* Matching port, or the correct slot for ordering */ 203 if (lp->port == port || legacy_port[i] == port) { 204 if (!(probe_mask & 1 << i)) 205 return -1; 206 free = lp; 207 break; 208 } 209 lp++; 210 } 211 if (free == NULL) { 212 printk(KERN_ERR "pata_legacy: Too many interfaces.\n"); 213 return -1; 214 } 215 /* Fill in the entry for later probing */ 216 free->port = port; 217 free->irq = irq; 218 free->type = type; 219 free->private = private; 220 return 0; 221} 222 223 224/** 225 * legacy_set_mode - mode setting 226 * @link: IDE link 227 * @unused: Device that failed when error is returned 228 * 229 * Use a non standard set_mode function. We don't want to be tuned. 230 * 231 * The BIOS configured everything. Our job is not to fiddle. Just use 232 * whatever PIO the hardware is using and leave it at that. When we 233 * get some kind of nice user driven API for control then we can 234 * expand on this as per hdparm in the base kernel. 235 */ 236 237static int legacy_set_mode(struct ata_link *link, struct ata_device **unused) 238{ 239 struct ata_device *dev; 240 241 ata_for_each_dev(dev, link, ENABLED) { 242 ata_dev_info(dev, "configured for PIO\n"); 243 dev->pio_mode = XFER_PIO_0; 244 dev->xfer_mode = XFER_PIO_0; 245 dev->xfer_shift = ATA_SHIFT_PIO; 246 dev->flags |= ATA_DFLAG_PIO; 247 } 248 return 0; 249} 250 251static const struct scsi_host_template legacy_sht = { 252 ATA_PIO_SHT(DRV_NAME), 253}; 254 255static const struct ata_port_operations legacy_base_port_ops = { 256 .inherits = &ata_sff_port_ops, 257 .cable_detect = ata_cable_40wire, 258}; 259 260/* 261 * These ops are used if the user indicates the hardware 262 * snoops the commands to decide on the mode and handles the 263 * mode selection "magically" itself. Several legacy controllers 264 * do this. The mode range can be set if it is not 0x1F by setting 265 * pio_mask as well. 266 */ 267 268static struct ata_port_operations simple_port_ops = { 269 .inherits = &legacy_base_port_ops, 270 .sff_data_xfer = ata_sff_data_xfer32, 271}; 272 273static struct ata_port_operations legacy_port_ops = { 274 .inherits = &legacy_base_port_ops, 275 .sff_data_xfer = ata_sff_data_xfer32, 276 .set_mode = legacy_set_mode, 277}; 278 279/* 280 * Promise 20230C and 20620 support 281 * 282 * This controller supports PIO0 to PIO2. We set PIO timings 283 * conservatively to allow for 50MHz Vesa Local Bus. The 20620 DMA 284 * support is weird being DMA to controller and PIO'd to the host 285 * and not supported. 286 */ 287 288static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev) 289{ 290 int tries = 5; 291 int pio = adev->pio_mode - XFER_PIO_0; 292 u8 rt; 293 unsigned long flags; 294 295 /* Safe as UP only. Force I/Os to occur together */ 296 297 local_irq_save(flags); 298 299 /* Unlock the control interface */ 300 do { 301 inb(0x1F5); 302 outb(inb(0x1F2) | 0x80, 0x1F2); 303 inb(0x1F2); 304 inb(0x3F6); 305 inb(0x3F6); 306 inb(0x1F2); 307 inb(0x1F2); 308 } 309 while ((inb(0x1F2) & 0x80) && --tries); 310 311 local_irq_restore(flags); 312 313 outb(inb(0x1F4) & 0x07, 0x1F4); 314 315 rt = inb(0x1F3); 316 rt &= ~(0x07 << (3 * !adev->devno)); 317 if (pio) 318 rt |= (1 + 3 * pio) << (3 * !adev->devno); 319 outb(rt, 0x1F3); 320 321 udelay(100); 322 outb(inb(0x1F2) | 0x01, 0x1F2); 323 udelay(100); 324 inb(0x1F5); 325 326} 327 328static unsigned int pdc_data_xfer_vlb(struct ata_queued_cmd *qc, 329 unsigned char *buf, unsigned int buflen, int rw) 330{ 331 struct ata_device *dev = qc->dev; 332 struct ata_port *ap = dev->link->ap; 333 int slop = buflen & 3; 334 335 /* 32bit I/O capable *and* we need to write a whole number of dwords */ 336 if (ata_id_has_dword_io(dev->id) && (slop == 0 || slop == 3) 337 && (ap->pflags & ATA_PFLAG_PIO32)) { 338 unsigned long flags; 339 340 local_irq_save(flags); 341 342 /* Perform the 32bit I/O synchronization sequence */ 343 ioread8(ap->ioaddr.nsect_addr); 344 ioread8(ap->ioaddr.nsect_addr); 345 ioread8(ap->ioaddr.nsect_addr); 346 347 /* Now the data */ 348 if (rw == READ) 349 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); 350 else 351 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); 352 353 if (unlikely(slop)) { 354 __le32 pad = 0; 355 356 if (rw == READ) { 357 pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr)); 358 memcpy(buf + buflen - slop, &pad, slop); 359 } else { 360 memcpy(&pad, buf + buflen - slop, slop); 361 iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr); 362 } 363 buflen += 4 - slop; 364 } 365 local_irq_restore(flags); 366 } else 367 buflen = ata_sff_data_xfer32(qc, buf, buflen, rw); 368 369 return buflen; 370} 371 372static struct ata_port_operations pdc20230_port_ops = { 373 .inherits = &legacy_base_port_ops, 374 .set_piomode = pdc20230_set_piomode, 375 .sff_data_xfer = pdc_data_xfer_vlb, 376}; 377 378/* 379 * Holtek 6560A support 380 * 381 * This controller supports PIO0 to PIO2 (no IORDY even though higher 382 * timings can be loaded). 383 */ 384 385static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev) 386{ 387 u8 active, recover; 388 struct ata_timing t; 389 390 /* Get the timing data in cycles. For now play safe at 50Mhz */ 391 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); 392 393 active = clamp_val(t.active, 2, 15); 394 recover = clamp_val(t.recover, 4, 15); 395 396 inb(0x3E6); 397 inb(0x3E6); 398 inb(0x3E6); 399 inb(0x3E6); 400 401 iowrite8(recover << 4 | active, ap->ioaddr.device_addr); 402 ioread8(ap->ioaddr.status_addr); 403} 404 405static struct ata_port_operations ht6560a_port_ops = { 406 .inherits = &legacy_base_port_ops, 407 .set_piomode = ht6560a_set_piomode, 408}; 409 410/* 411 * Holtek 6560B support 412 * 413 * This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO 414 * setting unless we see an ATAPI device in which case we force it off. 415 * 416 * FIXME: need to implement 2nd channel support. 417 */ 418 419static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev) 420{ 421 u8 active, recover; 422 struct ata_timing t; 423 424 /* Get the timing data in cycles. For now play safe at 50Mhz */ 425 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); 426 427 active = clamp_val(t.active, 2, 15); 428 recover = clamp_val(t.recover, 2, 16) & 0x0F; 429 430 inb(0x3E6); 431 inb(0x3E6); 432 inb(0x3E6); 433 inb(0x3E6); 434 435 iowrite8(recover << 4 | active, ap->ioaddr.device_addr); 436 437 if (adev->class != ATA_DEV_ATA) { 438 u8 rconf = inb(0x3E6); 439 if (rconf & 0x24) { 440 rconf &= ~0x24; 441 outb(rconf, 0x3E6); 442 } 443 } 444 ioread8(ap->ioaddr.status_addr); 445} 446 447static struct ata_port_operations ht6560b_port_ops = { 448 .inherits = &legacy_base_port_ops, 449 .set_piomode = ht6560b_set_piomode, 450}; 451 452/* 453 * Opti core chipset helpers 454 */ 455 456/** 457 * opti_syscfg - read OPTI chipset configuration 458 * @reg: Configuration register to read 459 * 460 * Returns the value of an OPTI system board configuration register. 461 */ 462 463static u8 opti_syscfg(u8 reg) 464{ 465 unsigned long flags; 466 u8 r; 467 468 /* Uniprocessor chipset and must force cycles adjancent */ 469 local_irq_save(flags); 470 outb(reg, 0x22); 471 r = inb(0x24); 472 local_irq_restore(flags); 473 return r; 474} 475 476/* 477 * Opti 82C611A 478 * 479 * This controller supports PIO0 to PIO3. 480 */ 481 482static void opti82c611a_set_piomode(struct ata_port *ap, 483 struct ata_device *adev) 484{ 485 u8 active, recover, setup; 486 struct ata_timing t; 487 struct ata_device *pair = ata_dev_pair(adev); 488 int clock; 489 int khz[4] = { 50000, 40000, 33000, 25000 }; 490 u8 rc; 491 492 /* Enter configuration mode */ 493 ioread16(ap->ioaddr.error_addr); 494 ioread16(ap->ioaddr.error_addr); 495 iowrite8(3, ap->ioaddr.nsect_addr); 496 497 /* Read VLB clock strapping */ 498 clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03]; 499 500 /* Get the timing data in cycles */ 501 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); 502 503 /* Setup timing is shared */ 504 if (pair) { 505 struct ata_timing tp; 506 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000); 507 508 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); 509 } 510 511 active = clamp_val(t.active, 2, 17) - 2; 512 recover = clamp_val(t.recover, 1, 16) - 1; 513 setup = clamp_val(t.setup, 1, 4) - 1; 514 515 /* Select the right timing bank for write timing */ 516 rc = ioread8(ap->ioaddr.lbal_addr); 517 rc &= 0x7F; 518 rc |= (adev->devno << 7); 519 iowrite8(rc, ap->ioaddr.lbal_addr); 520 521 /* Write the timings */ 522 iowrite8(active << 4 | recover, ap->ioaddr.error_addr); 523 524 /* Select the right bank for read timings, also 525 load the shared timings for address */ 526 rc = ioread8(ap->ioaddr.device_addr); 527 rc &= 0xC0; 528 rc |= adev->devno; /* Index select */ 529 rc |= (setup << 4) | 0x04; 530 iowrite8(rc, ap->ioaddr.device_addr); 531 532 /* Load the read timings */ 533 iowrite8(active << 4 | recover, ap->ioaddr.data_addr); 534 535 /* Ensure the timing register mode is right */ 536 rc = ioread8(ap->ioaddr.lbal_addr); 537 rc &= 0x73; 538 rc |= 0x84; 539 iowrite8(rc, ap->ioaddr.lbal_addr); 540 541 /* Exit command mode */ 542 iowrite8(0x83, ap->ioaddr.nsect_addr); 543} 544 545 546static struct ata_port_operations opti82c611a_port_ops = { 547 .inherits = &legacy_base_port_ops, 548 .set_piomode = opti82c611a_set_piomode, 549}; 550 551/* 552 * Opti 82C465MV 553 * 554 * This controller supports PIO0 to PIO3. Unlike the 611A the MVB 555 * version is dual channel but doesn't have a lot of unique registers. 556 */ 557 558static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev) 559{ 560 u8 active, recover, setup; 561 struct ata_timing t; 562 struct ata_device *pair = ata_dev_pair(adev); 563 int clock; 564 int khz[4] = { 50000, 40000, 33000, 25000 }; 565 u8 rc; 566 u8 sysclk; 567 568 /* Get the clock */ 569 sysclk = (opti_syscfg(0xAC) & 0xC0) >> 6; /* BIOS set */ 570 571 /* Enter configuration mode */ 572 ioread16(ap->ioaddr.error_addr); 573 ioread16(ap->ioaddr.error_addr); 574 iowrite8(3, ap->ioaddr.nsect_addr); 575 576 /* Read VLB clock strapping */ 577 clock = 1000000000 / khz[sysclk]; 578 579 /* Get the timing data in cycles */ 580 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); 581 582 /* Setup timing is shared */ 583 if (pair) { 584 struct ata_timing tp; 585 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000); 586 587 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); 588 } 589 590 active = clamp_val(t.active, 2, 17) - 2; 591 recover = clamp_val(t.recover, 1, 16) - 1; 592 setup = clamp_val(t.setup, 1, 4) - 1; 593 594 /* Select the right timing bank for write timing */ 595 rc = ioread8(ap->ioaddr.lbal_addr); 596 rc &= 0x7F; 597 rc |= (adev->devno << 7); 598 iowrite8(rc, ap->ioaddr.lbal_addr); 599 600 /* Write the timings */ 601 iowrite8(active << 4 | recover, ap->ioaddr.error_addr); 602 603 /* Select the right bank for read timings, also 604 load the shared timings for address */ 605 rc = ioread8(ap->ioaddr.device_addr); 606 rc &= 0xC0; 607 rc |= adev->devno; /* Index select */ 608 rc |= (setup << 4) | 0x04; 609 iowrite8(rc, ap->ioaddr.device_addr); 610 611 /* Load the read timings */ 612 iowrite8(active << 4 | recover, ap->ioaddr.data_addr); 613 614 /* Ensure the timing register mode is right */ 615 rc = ioread8(ap->ioaddr.lbal_addr); 616 rc &= 0x73; 617 rc |= 0x84; 618 iowrite8(rc, ap->ioaddr.lbal_addr); 619 620 /* Exit command mode */ 621 iowrite8(0x83, ap->ioaddr.nsect_addr); 622 623 /* We need to know this for quad device on the MVB */ 624 ap->host->private_data = ap; 625} 626 627/** 628 * opti82c46x_qc_issue - command issue 629 * @qc: command pending 630 * 631 * Called when the libata layer is about to issue a command. We wrap 632 * this interface so that we can load the correct ATA timings. The 633 * MVB has a single set of timing registers and these are shared 634 * across channels. As there are two registers we really ought to 635 * track the last two used values as a sort of register window. For 636 * now we just reload on a channel switch. On the single channel 637 * setup this condition never fires so we do nothing extra. 638 * 639 * FIXME: dual channel needs ->serialize support 640 */ 641 642static unsigned int opti82c46x_qc_issue(struct ata_queued_cmd *qc) 643{ 644 struct ata_port *ap = qc->ap; 645 struct ata_device *adev = qc->dev; 646 647 /* If timings are set and for the wrong channel (2nd test is 648 due to a libata shortcoming and will eventually go I hope) */ 649 if (ap->host->private_data != ap->host 650 && ap->host->private_data != NULL) 651 opti82c46x_set_piomode(ap, adev); 652 653 return ata_sff_qc_issue(qc); 654} 655 656static struct ata_port_operations opti82c46x_port_ops = { 657 .inherits = &legacy_base_port_ops, 658 .set_piomode = opti82c46x_set_piomode, 659 .qc_issue = opti82c46x_qc_issue, 660}; 661 662/** 663 * qdi65x0_set_piomode - PIO setup for QDI65x0 664 * @ap: Port 665 * @adev: Device 666 * 667 * In single channel mode the 6580 has one clock per device and we can 668 * avoid the requirement to clock switch. We also have to load the timing 669 * into the right clock according to whether we are master or slave. 670 * 671 * In dual channel mode the 6580 has one clock per channel and we have 672 * to software clockswitch in qc_issue. 673 */ 674 675static void qdi65x0_set_piomode(struct ata_port *ap, struct ata_device *adev) 676{ 677 struct ata_timing t; 678 struct legacy_data *ld_qdi = ap->host->private_data; 679 int active, recovery; 680 u8 timing; 681 682 /* Get the timing data in cycles */ 683 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); 684 685 if (ld_qdi->fast) { 686 active = 8 - clamp_val(t.active, 1, 8); 687 recovery = 18 - clamp_val(t.recover, 3, 18); 688 } else { 689 active = 9 - clamp_val(t.active, 2, 9); 690 recovery = 15 - clamp_val(t.recover, 0, 15); 691 } 692 timing = (recovery << 4) | active | 0x08; 693 ld_qdi->clock[adev->devno] = timing; 694 695 if (ld_qdi->type == QDI6580) 696 outb(timing, ld_qdi->timing + 2 * adev->devno); 697 else 698 outb(timing, ld_qdi->timing + 2 * ap->port_no); 699 700 /* Clear the FIFO */ 701 if (ld_qdi->type != QDI6500 && adev->class != ATA_DEV_ATA) 702 outb(0x5F, (ld_qdi->timing & 0xFFF0) + 3); 703} 704 705/** 706 * qdi_qc_issue - command issue 707 * @qc: command pending 708 * 709 * Called when the libata layer is about to issue a command. We wrap 710 * this interface so that we can load the correct ATA timings. 711 */ 712 713static unsigned int qdi_qc_issue(struct ata_queued_cmd *qc) 714{ 715 struct ata_port *ap = qc->ap; 716 struct ata_device *adev = qc->dev; 717 struct legacy_data *ld_qdi = ap->host->private_data; 718 719 if (ld_qdi->clock[adev->devno] != ld_qdi->last) { 720 if (adev->pio_mode) { 721 ld_qdi->last = ld_qdi->clock[adev->devno]; 722 outb(ld_qdi->clock[adev->devno], ld_qdi->timing + 723 2 * ap->port_no); 724 } 725 } 726 return ata_sff_qc_issue(qc); 727} 728 729static unsigned int vlb32_data_xfer(struct ata_queued_cmd *qc, 730 unsigned char *buf, 731 unsigned int buflen, int rw) 732{ 733 struct ata_device *adev = qc->dev; 734 struct ata_port *ap = adev->link->ap; 735 int slop = buflen & 3; 736 737 if (ata_id_has_dword_io(adev->id) && (slop == 0 || slop == 3) 738 && (ap->pflags & ATA_PFLAG_PIO32)) { 739 if (rw == WRITE) 740 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); 741 else 742 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); 743 744 if (unlikely(slop)) { 745 __le32 pad = 0; 746 747 if (rw == WRITE) { 748 memcpy(&pad, buf + buflen - slop, slop); 749 iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr); 750 } else { 751 pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr)); 752 memcpy(buf + buflen - slop, &pad, slop); 753 } 754 } 755 return (buflen + 3) & ~3; 756 } else 757 return ata_sff_data_xfer(qc, buf, buflen, rw); 758} 759 760static int qdi_port(struct platform_device *dev, 761 struct legacy_probe *lp, struct legacy_data *ld) 762{ 763 if (devm_request_region(&dev->dev, lp->private, 4, "qdi") == NULL) 764 return -EBUSY; 765 ld->timing = lp->private; 766 return 0; 767} 768 769static struct ata_port_operations qdi6500_port_ops = { 770 .inherits = &legacy_base_port_ops, 771 .set_piomode = qdi65x0_set_piomode, 772 .qc_issue = qdi_qc_issue, 773 .sff_data_xfer = vlb32_data_xfer, 774}; 775 776static struct ata_port_operations qdi6580_port_ops = { 777 .inherits = &legacy_base_port_ops, 778 .set_piomode = qdi65x0_set_piomode, 779 .sff_data_xfer = vlb32_data_xfer, 780}; 781 782static struct ata_port_operations qdi6580dp_port_ops = { 783 .inherits = &legacy_base_port_ops, 784 .set_piomode = qdi65x0_set_piomode, 785 .qc_issue = qdi_qc_issue, 786 .sff_data_xfer = vlb32_data_xfer, 787}; 788 789static DEFINE_SPINLOCK(winbond_lock); 790 791static void winbond_writecfg(unsigned long port, u8 reg, u8 val) 792{ 793 unsigned long flags; 794 spin_lock_irqsave(&winbond_lock, flags); 795 outb(reg, port + 0x01); 796 outb(val, port + 0x02); 797 spin_unlock_irqrestore(&winbond_lock, flags); 798} 799 800static u8 winbond_readcfg(unsigned long port, u8 reg) 801{ 802 u8 val; 803 804 unsigned long flags; 805 spin_lock_irqsave(&winbond_lock, flags); 806 outb(reg, port + 0x01); 807 val = inb(port + 0x02); 808 spin_unlock_irqrestore(&winbond_lock, flags); 809 810 return val; 811} 812 813static void winbond_set_piomode(struct ata_port *ap, struct ata_device *adev) 814{ 815 struct ata_timing t; 816 struct legacy_data *ld_winbond = ap->host->private_data; 817 int active, recovery; 818 u8 reg; 819 int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2); 820 821 reg = winbond_readcfg(ld_winbond->timing, 0x81); 822 823 /* Get the timing data in cycles */ 824 if (reg & 0x40) /* Fast VLB bus, assume 50MHz */ 825 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); 826 else 827 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000); 828 829 active = (clamp_val(t.active, 3, 17) - 1) & 0x0F; 830 recovery = (clamp_val(t.recover, 1, 15) + 1) & 0x0F; 831 timing = (active << 4) | recovery; 832 winbond_writecfg(ld_winbond->timing, timing, reg); 833 834 /* Load the setup timing */ 835 836 reg = 0x35; 837 if (adev->class != ATA_DEV_ATA) 838 reg |= 0x08; /* FIFO off */ 839 if (!ata_pio_need_iordy(adev)) 840 reg |= 0x02; /* IORDY off */ 841 reg |= (clamp_val(t.setup, 0, 3) << 6); 842 winbond_writecfg(ld_winbond->timing, timing + 1, reg); 843} 844 845static int winbond_port(struct platform_device *dev, 846 struct legacy_probe *lp, struct legacy_data *ld) 847{ 848 if (devm_request_region(&dev->dev, lp->private, 4, "winbond") == NULL) 849 return -EBUSY; 850 ld->timing = lp->private; 851 return 0; 852} 853 854static struct ata_port_operations winbond_port_ops = { 855 .inherits = &legacy_base_port_ops, 856 .set_piomode = winbond_set_piomode, 857 .sff_data_xfer = vlb32_data_xfer, 858}; 859 860static struct legacy_controller controllers[] = { 861 {"BIOS", &legacy_port_ops, ATA_PIO4, 862 ATA_FLAG_NO_IORDY, 0, NULL }, 863 {"Snooping", &simple_port_ops, ATA_PIO4, 864 0, 0, NULL }, 865 {"PDC20230", &pdc20230_port_ops, ATA_PIO2, 866 ATA_FLAG_NO_IORDY, 867 ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, NULL }, 868 {"HT6560A", &ht6560a_port_ops, ATA_PIO2, 869 ATA_FLAG_NO_IORDY, 0, NULL }, 870 {"HT6560B", &ht6560b_port_ops, ATA_PIO4, 871 ATA_FLAG_NO_IORDY, 0, NULL }, 872 {"OPTI82C611A", &opti82c611a_port_ops, ATA_PIO3, 873 0, 0, NULL }, 874 {"OPTI82C46X", &opti82c46x_port_ops, ATA_PIO3, 875 0, 0, NULL }, 876 {"QDI6500", &qdi6500_port_ops, ATA_PIO2, 877 ATA_FLAG_NO_IORDY, 878 ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port }, 879 {"QDI6580", &qdi6580_port_ops, ATA_PIO4, 880 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port }, 881 {"QDI6580DP", &qdi6580dp_port_ops, ATA_PIO4, 882 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port }, 883 {"W83759A", &winbond_port_ops, ATA_PIO4, 884 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, 885 winbond_port } 886}; 887 888/** 889 * probe_chip_type - Discover controller 890 * @probe: Probe entry to check 891 * 892 * Probe an ATA port and identify the type of controller. We don't 893 * check if the controller appears to be driveless at this point. 894 */ 895 896static __init int probe_chip_type(struct legacy_probe *probe) 897{ 898 int mask = 1 << probe->slot; 899 900 if (winbond && (probe->port == 0x1F0 || probe->port == 0x170)) { 901 u8 reg = winbond_readcfg(winbond, 0x81); 902 reg |= 0x80; /* jumpered mode off */ 903 winbond_writecfg(winbond, 0x81, reg); 904 reg = winbond_readcfg(winbond, 0x83); 905 reg |= 0xF0; /* local control */ 906 winbond_writecfg(winbond, 0x83, reg); 907 reg = winbond_readcfg(winbond, 0x85); 908 reg |= 0xF0; /* programmable timing */ 909 winbond_writecfg(winbond, 0x85, reg); 910 911 reg = winbond_readcfg(winbond, 0x81); 912 913 if (reg & mask) 914 return W83759A; 915 } 916 if (probe->port == 0x1F0) { 917 unsigned long flags; 918 local_irq_save(flags); 919 /* Probes */ 920 outb(inb(0x1F2) | 0x80, 0x1F2); 921 inb(0x1F5); 922 inb(0x1F2); 923 inb(0x3F6); 924 inb(0x3F6); 925 inb(0x1F2); 926 inb(0x1F2); 927 928 if ((inb(0x1F2) & 0x80) == 0) { 929 /* PDC20230c or 20630 ? */ 930 printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller" 931 " detected.\n"); 932 udelay(100); 933 inb(0x1F5); 934 local_irq_restore(flags); 935 return PDC20230; 936 } else { 937 outb(0x55, 0x1F2); 938 inb(0x1F2); 939 inb(0x1F2); 940 if (inb(0x1F2) == 0x00) 941 printk(KERN_INFO "PDC20230-B VLB ATA " 942 "controller detected.\n"); 943 local_irq_restore(flags); 944 return BIOS; 945 } 946 } 947 948 if (ht6560a & mask) 949 return HT6560A; 950 if (ht6560b & mask) 951 return HT6560B; 952 if (opti82c611a & mask) 953 return OPTI611A; 954 if (opti82c46x & mask) 955 return OPTI46X; 956 if (autospeed & mask) 957 return SNOOP; 958 return BIOS; 959} 960 961 962/** 963 * legacy_init_one - attach a legacy interface 964 * @probe: probe record 965 * 966 * Register an ISA bus IDE interface. Such interfaces are PIO and we 967 * assume do not support IRQ sharing. 968 */ 969 970static __init int legacy_init_one(struct legacy_probe *probe) 971{ 972 struct legacy_controller *controller = &controllers[probe->type]; 973 int pio_modes = controller->pio_mask; 974 unsigned long io = probe->port; 975 u32 mask = (1 << probe->slot); 976 struct ata_port_operations *ops = controller->ops; 977 struct legacy_data *ld = &legacy_data[probe->slot]; 978 struct ata_host *host = NULL; 979 struct ata_port *ap; 980 struct platform_device *pdev; 981 struct ata_device *dev; 982 void __iomem *io_addr, *ctrl_addr; 983 u32 iordy = (iordy_mask & mask) ? 0: ATA_FLAG_NO_IORDY; 984 int ret; 985 986 iordy |= controller->flags; 987 988 pdev = platform_device_register_simple(DRV_NAME, probe->slot, NULL, 0); 989 if (IS_ERR(pdev)) 990 return PTR_ERR(pdev); 991 992 ret = -EBUSY; 993 if (devm_request_region(&pdev->dev, io, 8, "pata_legacy") == NULL || 994 devm_request_region(&pdev->dev, io + 0x0206, 1, 995 "pata_legacy") == NULL) 996 goto fail; 997 998 ret = -ENOMEM; 999 io_addr = devm_ioport_map(&pdev->dev, io, 8); 1000 ctrl_addr = devm_ioport_map(&pdev->dev, io + 0x0206, 1); 1001 if (!io_addr || !ctrl_addr) 1002 goto fail; 1003 ld->type = probe->type; 1004 if (controller->setup) 1005 if (controller->setup(pdev, probe, ld) < 0) 1006 goto fail; 1007 host = ata_host_alloc(&pdev->dev, 1); 1008 if (!host) 1009 goto fail; 1010 ap = host->ports[0]; 1011 1012 ap->ops = ops; 1013 ap->pio_mask = pio_modes; 1014 ap->flags |= ATA_FLAG_SLAVE_POSS | iordy; 1015 ap->pflags |= controller->pflags; 1016 ap->ioaddr.cmd_addr = io_addr; 1017 ap->ioaddr.altstatus_addr = ctrl_addr; 1018 ap->ioaddr.ctl_addr = ctrl_addr; 1019 ata_sff_std_ports(&ap->ioaddr); 1020 ap->host->private_data = ld; 1021 1022 ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", io, io + 0x0206); 1023 1024 ret = ata_host_activate(host, probe->irq, ata_sff_interrupt, 0, 1025 &legacy_sht); 1026 if (ret) 1027 goto fail; 1028 async_synchronize_full(); 1029 ld->platform_dev = pdev; 1030 1031 /* Nothing found means we drop the port as its probably not there */ 1032 1033 ret = -ENODEV; 1034 ata_for_each_dev(dev, &ap->link, ALL) { 1035 if (!ata_dev_absent(dev)) { 1036 legacy_host[probe->slot] = host; 1037 ld->platform_dev = pdev; 1038 return 0; 1039 } 1040 } 1041 ata_host_detach(host); 1042fail: 1043 platform_device_unregister(pdev); 1044 return ret; 1045} 1046 1047/** 1048 * legacy_check_special_cases - ATA special cases 1049 * @p: PCI device to check 1050 * @primary: set this if we find an ATA master 1051 * @secondary: set this if we find an ATA secondary 1052 * 1053 * A small number of vendors implemented early PCI ATA interfaces 1054 * on bridge logic without the ATA interface being PCI visible. 1055 * Where we have a matching PCI driver we must skip the relevant 1056 * device here. If we don't know about it then the legacy driver 1057 * is the right driver anyway. 1058 */ 1059 1060static void __init legacy_check_special_cases(struct pci_dev *p, int *primary, 1061 int *secondary) 1062{ 1063 /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */ 1064 if (p->vendor == 0x1078 && p->device == 0x0000) { 1065 *primary = *secondary = 1; 1066 return; 1067 } 1068 /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */ 1069 if (p->vendor == 0x1078 && p->device == 0x0002) { 1070 *primary = *secondary = 1; 1071 return; 1072 } 1073 /* Intel MPIIX - PIO ATA on non PCI side of bridge */ 1074 if (p->vendor == 0x8086 && p->device == 0x1234) { 1075 u16 r; 1076 pci_read_config_word(p, 0x6C, &r); 1077 if (r & 0x8000) { 1078 /* ATA port enabled */ 1079 if (r & 0x4000) 1080 *secondary = 1; 1081 else 1082 *primary = 1; 1083 } 1084 return; 1085 } 1086} 1087 1088static __init void probe_opti_vlb(void) 1089{ 1090 /* If an OPTI 82C46X is present find out where the channels are */ 1091 static const char *optis[4] = { 1092 "3/463MV", "5MV", 1093 "5MVA", "5MVB" 1094 }; 1095 u8 chans = 1; 1096 u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6; 1097 1098 opti82c46x = 3; /* Assume master and slave first */ 1099 printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n", 1100 optis[ctrl]); 1101 if (ctrl == 3) 1102 chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1; 1103 ctrl = opti_syscfg(0xAC); 1104 /* Check enabled and this port is the 465MV port. On the 1105 MVB we may have two channels */ 1106 if (ctrl & 8) { 1107 if (chans == 2) { 1108 legacy_probe_add(0x1F0, 14, OPTI46X, 0); 1109 legacy_probe_add(0x170, 15, OPTI46X, 0); 1110 } 1111 if (ctrl & 4) 1112 legacy_probe_add(0x170, 15, OPTI46X, 0); 1113 else 1114 legacy_probe_add(0x1F0, 14, OPTI46X, 0); 1115 } else 1116 legacy_probe_add(0x1F0, 14, OPTI46X, 0); 1117} 1118 1119static __init void qdi65_identify_port(u8 r, u8 res, unsigned long port) 1120{ 1121 static const unsigned long ide_port[2] = { 0x170, 0x1F0 }; 1122 /* Check card type */ 1123 if ((r & 0xF0) == 0xC0) { 1124 /* QD6500: single channel */ 1125 if (r & 8) 1126 /* Disabled ? */ 1127 return; 1128 legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01), 1129 QDI6500, port); 1130 } 1131 if (((r & 0xF0) == 0xA0) || (r & 0xF0) == 0x50) { 1132 /* QD6580: dual channel */ 1133 if (!request_region(port + 2 , 2, "pata_qdi")) { 1134 release_region(port, 2); 1135 return; 1136 } 1137 res = inb(port + 3); 1138 /* Single channel mode ? */ 1139 if (res & 1) 1140 legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01), 1141 QDI6580, port); 1142 else { /* Dual channel mode */ 1143 legacy_probe_add(0x1F0, 14, QDI6580DP, port); 1144 /* port + 0x02, r & 0x04 */ 1145 legacy_probe_add(0x170, 15, QDI6580DP, port + 2); 1146 } 1147 release_region(port + 2, 2); 1148 } 1149} 1150 1151static __init void probe_qdi_vlb(void) 1152{ 1153 unsigned long flags; 1154 static const unsigned long qd_port[2] = { 0x30, 0xB0 }; 1155 int i; 1156 1157 /* 1158 * Check each possible QD65xx base address 1159 */ 1160 1161 for (i = 0; i < 2; i++) { 1162 unsigned long port = qd_port[i]; 1163 u8 r, res; 1164 1165 1166 if (request_region(port, 2, "pata_qdi")) { 1167 /* Check for a card */ 1168 local_irq_save(flags); 1169 /* I have no h/w that needs this delay but it 1170 is present in the historic code */ 1171 r = inb(port); 1172 udelay(1); 1173 outb(0x19, port); 1174 udelay(1); 1175 res = inb(port); 1176 udelay(1); 1177 outb(r, port); 1178 udelay(1); 1179 local_irq_restore(flags); 1180 1181 /* Fail */ 1182 if (res == 0x19) { 1183 release_region(port, 2); 1184 continue; 1185 } 1186 /* Passes the presence test */ 1187 r = inb(port + 1); 1188 udelay(1); 1189 /* Check port agrees with port set */ 1190 if ((r & 2) >> 1 == i) 1191 qdi65_identify_port(r, res, port); 1192 release_region(port, 2); 1193 } 1194 } 1195} 1196 1197/** 1198 * legacy_init - attach legacy interfaces 1199 * 1200 * Attach legacy IDE interfaces by scanning the usual IRQ/port suspects. 1201 * Right now we do not scan the ide0 and ide1 address but should do so 1202 * for non PCI systems or systems with no PCI IDE legacy mode devices. 1203 * If you fix that note there are special cases to consider like VLB 1204 * drivers and CS5510/20. 1205 */ 1206 1207static __init int legacy_init(void) 1208{ 1209 int i; 1210 int ct = 0; 1211 int primary = 0; 1212 int secondary = 0; 1213 int pci_present = 0; 1214 struct legacy_probe *pl = &probe_list[0]; 1215 int slot = 0; 1216 1217 struct pci_dev *p = NULL; 1218 1219 for_each_pci_dev(p) { 1220 int r; 1221 /* Check for any overlap of the system ATA mappings. Native 1222 mode controllers stuck on these addresses or some devices 1223 in 'raid' mode won't be found by the storage class test */ 1224 for (r = 0; r < 6; r++) { 1225 if (pci_resource_start(p, r) == 0x1f0) 1226 primary = 1; 1227 if (pci_resource_start(p, r) == 0x170) 1228 secondary = 1; 1229 } 1230 /* Check for special cases */ 1231 legacy_check_special_cases(p, &primary, &secondary); 1232 1233 /* If PCI bus is present then don't probe for tertiary 1234 legacy ports */ 1235 pci_present = 1; 1236 } 1237 1238 if (winbond == 1) 1239 winbond = 0x130; /* Default port, alt is 1B0 */ 1240 1241 if (primary == 0 || all) 1242 legacy_probe_add(0x1F0, 14, UNKNOWN, 0); 1243 if (secondary == 0 || all) 1244 legacy_probe_add(0x170, 15, UNKNOWN, 0); 1245 1246 if (probe_all || !pci_present) { 1247 /* ISA/VLB extra ports */ 1248 legacy_probe_add(0x1E8, 11, UNKNOWN, 0); 1249 legacy_probe_add(0x168, 10, UNKNOWN, 0); 1250 legacy_probe_add(0x1E0, 8, UNKNOWN, 0); 1251 legacy_probe_add(0x160, 12, UNKNOWN, 0); 1252 } 1253 1254 if (opti82c46x) 1255 probe_opti_vlb(); 1256 if (qdi) 1257 probe_qdi_vlb(); 1258 1259 for (i = 0; i < NR_HOST; i++, pl++) { 1260 if (pl->port == 0) 1261 continue; 1262 if (pl->type == UNKNOWN) 1263 pl->type = probe_chip_type(pl); 1264 pl->slot = slot++; 1265 if (legacy_init_one(pl) == 0) 1266 ct++; 1267 } 1268 if (ct != 0) 1269 return 0; 1270 return -ENODEV; 1271} 1272 1273static __exit void legacy_exit(void) 1274{ 1275 int i; 1276 1277 for (i = 0; i < NR_HOST; i++) { 1278 struct legacy_data *ld = &legacy_data[i]; 1279 1280 if (legacy_host[i]) 1281 ata_host_detach(legacy_host[i]); 1282 platform_device_unregister(ld->platform_dev); 1283 } 1284} 1285 1286MODULE_AUTHOR("Alan Cox"); 1287MODULE_DESCRIPTION("low-level driver for legacy ATA"); 1288MODULE_LICENSE("GPL"); 1289MODULE_VERSION(DRV_VERSION); 1290MODULE_ALIAS("pata_qdi"); 1291MODULE_ALIAS("pata_winbond"); 1292 1293module_init(legacy_init); 1294module_exit(legacy_exit); 1295