1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * vmx.h: VMX Architecture related definitions 4 * Copyright (c) 2004, Intel Corporation. 5 * 6 * A few random additions are: 7 * Copyright (C) 2006 Qumranet 8 * Avi Kivity <avi@qumranet.com> 9 * Yaniv Kamay <yaniv@qumranet.com> 10 */ 11#ifndef VMX_H 12#define VMX_H 13 14 15#include <linux/bitops.h> 16#include <linux/bug.h> 17#include <linux/types.h> 18 19#include <uapi/asm/vmx.h> 20#include <asm/trapnr.h> 21#include <asm/vmxfeatures.h> 22 23#define VMCS_CONTROL_BIT(x) BIT(VMX_FEATURE_##x & 0x1f) 24 25/* 26 * Definitions of Primary Processor-Based VM-Execution Controls. 27 */ 28#define CPU_BASED_INTR_WINDOW_EXITING VMCS_CONTROL_BIT(INTR_WINDOW_EXITING) 29#define CPU_BASED_USE_TSC_OFFSETTING VMCS_CONTROL_BIT(USE_TSC_OFFSETTING) 30#define CPU_BASED_HLT_EXITING VMCS_CONTROL_BIT(HLT_EXITING) 31#define CPU_BASED_INVLPG_EXITING VMCS_CONTROL_BIT(INVLPG_EXITING) 32#define CPU_BASED_MWAIT_EXITING VMCS_CONTROL_BIT(MWAIT_EXITING) 33#define CPU_BASED_RDPMC_EXITING VMCS_CONTROL_BIT(RDPMC_EXITING) 34#define CPU_BASED_RDTSC_EXITING VMCS_CONTROL_BIT(RDTSC_EXITING) 35#define CPU_BASED_CR3_LOAD_EXITING VMCS_CONTROL_BIT(CR3_LOAD_EXITING) 36#define CPU_BASED_CR3_STORE_EXITING VMCS_CONTROL_BIT(CR3_STORE_EXITING) 37#define CPU_BASED_ACTIVATE_TERTIARY_CONTROLS VMCS_CONTROL_BIT(TERTIARY_CONTROLS) 38#define CPU_BASED_CR8_LOAD_EXITING VMCS_CONTROL_BIT(CR8_LOAD_EXITING) 39#define CPU_BASED_CR8_STORE_EXITING VMCS_CONTROL_BIT(CR8_STORE_EXITING) 40#define CPU_BASED_TPR_SHADOW VMCS_CONTROL_BIT(VIRTUAL_TPR) 41#define CPU_BASED_NMI_WINDOW_EXITING VMCS_CONTROL_BIT(NMI_WINDOW_EXITING) 42#define CPU_BASED_MOV_DR_EXITING VMCS_CONTROL_BIT(MOV_DR_EXITING) 43#define CPU_BASED_UNCOND_IO_EXITING VMCS_CONTROL_BIT(UNCOND_IO_EXITING) 44#define CPU_BASED_USE_IO_BITMAPS VMCS_CONTROL_BIT(USE_IO_BITMAPS) 45#define CPU_BASED_MONITOR_TRAP_FLAG VMCS_CONTROL_BIT(MONITOR_TRAP_FLAG) 46#define CPU_BASED_USE_MSR_BITMAPS VMCS_CONTROL_BIT(USE_MSR_BITMAPS) 47#define CPU_BASED_MONITOR_EXITING VMCS_CONTROL_BIT(MONITOR_EXITING) 48#define CPU_BASED_PAUSE_EXITING VMCS_CONTROL_BIT(PAUSE_EXITING) 49#define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS VMCS_CONTROL_BIT(SEC_CONTROLS) 50 51#define CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x0401e172 52 53/* 54 * Definitions of Secondary Processor-Based VM-Execution Controls. 55 */ 56#define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES VMCS_CONTROL_BIT(VIRT_APIC_ACCESSES) 57#define SECONDARY_EXEC_ENABLE_EPT VMCS_CONTROL_BIT(EPT) 58#define SECONDARY_EXEC_DESC VMCS_CONTROL_BIT(DESC_EXITING) 59#define SECONDARY_EXEC_ENABLE_RDTSCP VMCS_CONTROL_BIT(RDTSCP) 60#define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE VMCS_CONTROL_BIT(VIRTUAL_X2APIC) 61#define SECONDARY_EXEC_ENABLE_VPID VMCS_CONTROL_BIT(VPID) 62#define SECONDARY_EXEC_WBINVD_EXITING VMCS_CONTROL_BIT(WBINVD_EXITING) 63#define SECONDARY_EXEC_UNRESTRICTED_GUEST VMCS_CONTROL_BIT(UNRESTRICTED_GUEST) 64#define SECONDARY_EXEC_APIC_REGISTER_VIRT VMCS_CONTROL_BIT(APIC_REGISTER_VIRT) 65#define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY VMCS_CONTROL_BIT(VIRT_INTR_DELIVERY) 66#define SECONDARY_EXEC_PAUSE_LOOP_EXITING VMCS_CONTROL_BIT(PAUSE_LOOP_EXITING) 67#define SECONDARY_EXEC_RDRAND_EXITING VMCS_CONTROL_BIT(RDRAND_EXITING) 68#define SECONDARY_EXEC_ENABLE_INVPCID VMCS_CONTROL_BIT(INVPCID) 69#define SECONDARY_EXEC_ENABLE_VMFUNC VMCS_CONTROL_BIT(VMFUNC) 70#define SECONDARY_EXEC_SHADOW_VMCS VMCS_CONTROL_BIT(SHADOW_VMCS) 71#define SECONDARY_EXEC_ENCLS_EXITING VMCS_CONTROL_BIT(ENCLS_EXITING) 72#define SECONDARY_EXEC_RDSEED_EXITING VMCS_CONTROL_BIT(RDSEED_EXITING) 73#define SECONDARY_EXEC_ENABLE_PML VMCS_CONTROL_BIT(PAGE_MOD_LOGGING) 74#define SECONDARY_EXEC_EPT_VIOLATION_VE VMCS_CONTROL_BIT(EPT_VIOLATION_VE) 75#define SECONDARY_EXEC_PT_CONCEAL_VMX VMCS_CONTROL_BIT(PT_CONCEAL_VMX) 76#define SECONDARY_EXEC_ENABLE_XSAVES VMCS_CONTROL_BIT(XSAVES) 77#define SECONDARY_EXEC_MODE_BASED_EPT_EXEC VMCS_CONTROL_BIT(MODE_BASED_EPT_EXEC) 78#define SECONDARY_EXEC_PT_USE_GPA VMCS_CONTROL_BIT(PT_USE_GPA) 79#define SECONDARY_EXEC_TSC_SCALING VMCS_CONTROL_BIT(TSC_SCALING) 80#define SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE VMCS_CONTROL_BIT(USR_WAIT_PAUSE) 81#define SECONDARY_EXEC_BUS_LOCK_DETECTION VMCS_CONTROL_BIT(BUS_LOCK_DETECTION) 82#define SECONDARY_EXEC_NOTIFY_VM_EXITING VMCS_CONTROL_BIT(NOTIFY_VM_EXITING) 83 84/* 85 * Definitions of Tertiary Processor-Based VM-Execution Controls. 86 */ 87#define TERTIARY_EXEC_IPI_VIRT VMCS_CONTROL_BIT(IPI_VIRT) 88 89#define PIN_BASED_EXT_INTR_MASK VMCS_CONTROL_BIT(INTR_EXITING) 90#define PIN_BASED_NMI_EXITING VMCS_CONTROL_BIT(NMI_EXITING) 91#define PIN_BASED_VIRTUAL_NMIS VMCS_CONTROL_BIT(VIRTUAL_NMIS) 92#define PIN_BASED_VMX_PREEMPTION_TIMER VMCS_CONTROL_BIT(PREEMPTION_TIMER) 93#define PIN_BASED_POSTED_INTR VMCS_CONTROL_BIT(POSTED_INTR) 94 95#define PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x00000016 96 97#define VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004 98#define VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200 99#define VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000 100#define VM_EXIT_ACK_INTR_ON_EXIT 0x00008000 101#define VM_EXIT_SAVE_IA32_PAT 0x00040000 102#define VM_EXIT_LOAD_IA32_PAT 0x00080000 103#define VM_EXIT_SAVE_IA32_EFER 0x00100000 104#define VM_EXIT_LOAD_IA32_EFER 0x00200000 105#define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000 106#define VM_EXIT_CLEAR_BNDCFGS 0x00800000 107#define VM_EXIT_PT_CONCEAL_PIP 0x01000000 108#define VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000 109 110#define VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR 0x00036dff 111 112#define VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004 113#define VM_ENTRY_IA32E_MODE 0x00000200 114#define VM_ENTRY_SMM 0x00000400 115#define VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800 116#define VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000 117#define VM_ENTRY_LOAD_IA32_PAT 0x00004000 118#define VM_ENTRY_LOAD_IA32_EFER 0x00008000 119#define VM_ENTRY_LOAD_BNDCFGS 0x00010000 120#define VM_ENTRY_PT_CONCEAL_PIP 0x00020000 121#define VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000 122 123#define VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR 0x000011ff 124 125#define VMX_MISC_PREEMPTION_TIMER_RATE_MASK 0x0000001f 126#define VMX_MISC_SAVE_EFER_LMA 0x00000020 127#define VMX_MISC_ACTIVITY_HLT 0x00000040 128#define VMX_MISC_ACTIVITY_WAIT_SIPI 0x00000100 129#define VMX_MISC_ZERO_LEN_INS 0x40000000 130#define VMX_MISC_MSR_LIST_MULTIPLIER 512 131 132/* VMFUNC functions */ 133#define VMFUNC_CONTROL_BIT(x) BIT((VMX_FEATURE_##x & 0x1f) - 28) 134 135#define VMX_VMFUNC_EPTP_SWITCHING VMFUNC_CONTROL_BIT(EPTP_SWITCHING) 136#define VMFUNC_EPTP_ENTRIES 512 137 138static inline u32 vmx_basic_vmcs_revision_id(u64 vmx_basic) 139{ 140 return vmx_basic & GENMASK_ULL(30, 0); 141} 142 143static inline u32 vmx_basic_vmcs_size(u64 vmx_basic) 144{ 145 return (vmx_basic & GENMASK_ULL(44, 32)) >> 32; 146} 147 148static inline int vmx_misc_preemption_timer_rate(u64 vmx_misc) 149{ 150 return vmx_misc & VMX_MISC_PREEMPTION_TIMER_RATE_MASK; 151} 152 153static inline int vmx_misc_cr3_count(u64 vmx_misc) 154{ 155 return (vmx_misc & GENMASK_ULL(24, 16)) >> 16; 156} 157 158static inline int vmx_misc_max_msr(u64 vmx_misc) 159{ 160 return (vmx_misc & GENMASK_ULL(27, 25)) >> 25; 161} 162 163static inline int vmx_misc_mseg_revid(u64 vmx_misc) 164{ 165 return (vmx_misc & GENMASK_ULL(63, 32)) >> 32; 166} 167 168/* VMCS Encodings */ 169enum vmcs_field { 170 VIRTUAL_PROCESSOR_ID = 0x00000000, 171 POSTED_INTR_NV = 0x00000002, 172 LAST_PID_POINTER_INDEX = 0x00000008, 173 GUEST_ES_SELECTOR = 0x00000800, 174 GUEST_CS_SELECTOR = 0x00000802, 175 GUEST_SS_SELECTOR = 0x00000804, 176 GUEST_DS_SELECTOR = 0x00000806, 177 GUEST_FS_SELECTOR = 0x00000808, 178 GUEST_GS_SELECTOR = 0x0000080a, 179 GUEST_LDTR_SELECTOR = 0x0000080c, 180 GUEST_TR_SELECTOR = 0x0000080e, 181 GUEST_INTR_STATUS = 0x00000810, 182 GUEST_PML_INDEX = 0x00000812, 183 HOST_ES_SELECTOR = 0x00000c00, 184 HOST_CS_SELECTOR = 0x00000c02, 185 HOST_SS_SELECTOR = 0x00000c04, 186 HOST_DS_SELECTOR = 0x00000c06, 187 HOST_FS_SELECTOR = 0x00000c08, 188 HOST_GS_SELECTOR = 0x00000c0a, 189 HOST_TR_SELECTOR = 0x00000c0c, 190 IO_BITMAP_A = 0x00002000, 191 IO_BITMAP_A_HIGH = 0x00002001, 192 IO_BITMAP_B = 0x00002002, 193 IO_BITMAP_B_HIGH = 0x00002003, 194 MSR_BITMAP = 0x00002004, 195 MSR_BITMAP_HIGH = 0x00002005, 196 VM_EXIT_MSR_STORE_ADDR = 0x00002006, 197 VM_EXIT_MSR_STORE_ADDR_HIGH = 0x00002007, 198 VM_EXIT_MSR_LOAD_ADDR = 0x00002008, 199 VM_EXIT_MSR_LOAD_ADDR_HIGH = 0x00002009, 200 VM_ENTRY_MSR_LOAD_ADDR = 0x0000200a, 201 VM_ENTRY_MSR_LOAD_ADDR_HIGH = 0x0000200b, 202 PML_ADDRESS = 0x0000200e, 203 PML_ADDRESS_HIGH = 0x0000200f, 204 TSC_OFFSET = 0x00002010, 205 TSC_OFFSET_HIGH = 0x00002011, 206 VIRTUAL_APIC_PAGE_ADDR = 0x00002012, 207 VIRTUAL_APIC_PAGE_ADDR_HIGH = 0x00002013, 208 APIC_ACCESS_ADDR = 0x00002014, 209 APIC_ACCESS_ADDR_HIGH = 0x00002015, 210 POSTED_INTR_DESC_ADDR = 0x00002016, 211 POSTED_INTR_DESC_ADDR_HIGH = 0x00002017, 212 VM_FUNCTION_CONTROL = 0x00002018, 213 VM_FUNCTION_CONTROL_HIGH = 0x00002019, 214 EPT_POINTER = 0x0000201a, 215 EPT_POINTER_HIGH = 0x0000201b, 216 EOI_EXIT_BITMAP0 = 0x0000201c, 217 EOI_EXIT_BITMAP0_HIGH = 0x0000201d, 218 EOI_EXIT_BITMAP1 = 0x0000201e, 219 EOI_EXIT_BITMAP1_HIGH = 0x0000201f, 220 EOI_EXIT_BITMAP2 = 0x00002020, 221 EOI_EXIT_BITMAP2_HIGH = 0x00002021, 222 EOI_EXIT_BITMAP3 = 0x00002022, 223 EOI_EXIT_BITMAP3_HIGH = 0x00002023, 224 EPTP_LIST_ADDRESS = 0x00002024, 225 EPTP_LIST_ADDRESS_HIGH = 0x00002025, 226 VMREAD_BITMAP = 0x00002026, 227 VMREAD_BITMAP_HIGH = 0x00002027, 228 VMWRITE_BITMAP = 0x00002028, 229 VMWRITE_BITMAP_HIGH = 0x00002029, 230 VE_INFORMATION_ADDRESS = 0x0000202A, 231 VE_INFORMATION_ADDRESS_HIGH = 0x0000202B, 232 XSS_EXIT_BITMAP = 0x0000202C, 233 XSS_EXIT_BITMAP_HIGH = 0x0000202D, 234 ENCLS_EXITING_BITMAP = 0x0000202E, 235 ENCLS_EXITING_BITMAP_HIGH = 0x0000202F, 236 TSC_MULTIPLIER = 0x00002032, 237 TSC_MULTIPLIER_HIGH = 0x00002033, 238 TERTIARY_VM_EXEC_CONTROL = 0x00002034, 239 TERTIARY_VM_EXEC_CONTROL_HIGH = 0x00002035, 240 PID_POINTER_TABLE = 0x00002042, 241 PID_POINTER_TABLE_HIGH = 0x00002043, 242 GUEST_PHYSICAL_ADDRESS = 0x00002400, 243 GUEST_PHYSICAL_ADDRESS_HIGH = 0x00002401, 244 VMCS_LINK_POINTER = 0x00002800, 245 VMCS_LINK_POINTER_HIGH = 0x00002801, 246 GUEST_IA32_DEBUGCTL = 0x00002802, 247 GUEST_IA32_DEBUGCTL_HIGH = 0x00002803, 248 GUEST_IA32_PAT = 0x00002804, 249 GUEST_IA32_PAT_HIGH = 0x00002805, 250 GUEST_IA32_EFER = 0x00002806, 251 GUEST_IA32_EFER_HIGH = 0x00002807, 252 GUEST_IA32_PERF_GLOBAL_CTRL = 0x00002808, 253 GUEST_IA32_PERF_GLOBAL_CTRL_HIGH= 0x00002809, 254 GUEST_PDPTR0 = 0x0000280a, 255 GUEST_PDPTR0_HIGH = 0x0000280b, 256 GUEST_PDPTR1 = 0x0000280c, 257 GUEST_PDPTR1_HIGH = 0x0000280d, 258 GUEST_PDPTR2 = 0x0000280e, 259 GUEST_PDPTR2_HIGH = 0x0000280f, 260 GUEST_PDPTR3 = 0x00002810, 261 GUEST_PDPTR3_HIGH = 0x00002811, 262 GUEST_BNDCFGS = 0x00002812, 263 GUEST_BNDCFGS_HIGH = 0x00002813, 264 GUEST_IA32_RTIT_CTL = 0x00002814, 265 GUEST_IA32_RTIT_CTL_HIGH = 0x00002815, 266 HOST_IA32_PAT = 0x00002c00, 267 HOST_IA32_PAT_HIGH = 0x00002c01, 268 HOST_IA32_EFER = 0x00002c02, 269 HOST_IA32_EFER_HIGH = 0x00002c03, 270 HOST_IA32_PERF_GLOBAL_CTRL = 0x00002c04, 271 HOST_IA32_PERF_GLOBAL_CTRL_HIGH = 0x00002c05, 272 PIN_BASED_VM_EXEC_CONTROL = 0x00004000, 273 CPU_BASED_VM_EXEC_CONTROL = 0x00004002, 274 EXCEPTION_BITMAP = 0x00004004, 275 PAGE_FAULT_ERROR_CODE_MASK = 0x00004006, 276 PAGE_FAULT_ERROR_CODE_MATCH = 0x00004008, 277 CR3_TARGET_COUNT = 0x0000400a, 278 VM_EXIT_CONTROLS = 0x0000400c, 279 VM_EXIT_MSR_STORE_COUNT = 0x0000400e, 280 VM_EXIT_MSR_LOAD_COUNT = 0x00004010, 281 VM_ENTRY_CONTROLS = 0x00004012, 282 VM_ENTRY_MSR_LOAD_COUNT = 0x00004014, 283 VM_ENTRY_INTR_INFO_FIELD = 0x00004016, 284 VM_ENTRY_EXCEPTION_ERROR_CODE = 0x00004018, 285 VM_ENTRY_INSTRUCTION_LEN = 0x0000401a, 286 TPR_THRESHOLD = 0x0000401c, 287 SECONDARY_VM_EXEC_CONTROL = 0x0000401e, 288 PLE_GAP = 0x00004020, 289 PLE_WINDOW = 0x00004022, 290 NOTIFY_WINDOW = 0x00004024, 291 VM_INSTRUCTION_ERROR = 0x00004400, 292 VM_EXIT_REASON = 0x00004402, 293 VM_EXIT_INTR_INFO = 0x00004404, 294 VM_EXIT_INTR_ERROR_CODE = 0x00004406, 295 IDT_VECTORING_INFO_FIELD = 0x00004408, 296 IDT_VECTORING_ERROR_CODE = 0x0000440a, 297 VM_EXIT_INSTRUCTION_LEN = 0x0000440c, 298 VMX_INSTRUCTION_INFO = 0x0000440e, 299 GUEST_ES_LIMIT = 0x00004800, 300 GUEST_CS_LIMIT = 0x00004802, 301 GUEST_SS_LIMIT = 0x00004804, 302 GUEST_DS_LIMIT = 0x00004806, 303 GUEST_FS_LIMIT = 0x00004808, 304 GUEST_GS_LIMIT = 0x0000480a, 305 GUEST_LDTR_LIMIT = 0x0000480c, 306 GUEST_TR_LIMIT = 0x0000480e, 307 GUEST_GDTR_LIMIT = 0x00004810, 308 GUEST_IDTR_LIMIT = 0x00004812, 309 GUEST_ES_AR_BYTES = 0x00004814, 310 GUEST_CS_AR_BYTES = 0x00004816, 311 GUEST_SS_AR_BYTES = 0x00004818, 312 GUEST_DS_AR_BYTES = 0x0000481a, 313 GUEST_FS_AR_BYTES = 0x0000481c, 314 GUEST_GS_AR_BYTES = 0x0000481e, 315 GUEST_LDTR_AR_BYTES = 0x00004820, 316 GUEST_TR_AR_BYTES = 0x00004822, 317 GUEST_INTERRUPTIBILITY_INFO = 0x00004824, 318 GUEST_ACTIVITY_STATE = 0x00004826, 319 GUEST_SYSENTER_CS = 0x0000482A, 320 VMX_PREEMPTION_TIMER_VALUE = 0x0000482E, 321 HOST_IA32_SYSENTER_CS = 0x00004c00, 322 CR0_GUEST_HOST_MASK = 0x00006000, 323 CR4_GUEST_HOST_MASK = 0x00006002, 324 CR0_READ_SHADOW = 0x00006004, 325 CR4_READ_SHADOW = 0x00006006, 326 CR3_TARGET_VALUE0 = 0x00006008, 327 CR3_TARGET_VALUE1 = 0x0000600a, 328 CR3_TARGET_VALUE2 = 0x0000600c, 329 CR3_TARGET_VALUE3 = 0x0000600e, 330 EXIT_QUALIFICATION = 0x00006400, 331 GUEST_LINEAR_ADDRESS = 0x0000640a, 332 GUEST_CR0 = 0x00006800, 333 GUEST_CR3 = 0x00006802, 334 GUEST_CR4 = 0x00006804, 335 GUEST_ES_BASE = 0x00006806, 336 GUEST_CS_BASE = 0x00006808, 337 GUEST_SS_BASE = 0x0000680a, 338 GUEST_DS_BASE = 0x0000680c, 339 GUEST_FS_BASE = 0x0000680e, 340 GUEST_GS_BASE = 0x00006810, 341 GUEST_LDTR_BASE = 0x00006812, 342 GUEST_TR_BASE = 0x00006814, 343 GUEST_GDTR_BASE = 0x00006816, 344 GUEST_IDTR_BASE = 0x00006818, 345 GUEST_DR7 = 0x0000681a, 346 GUEST_RSP = 0x0000681c, 347 GUEST_RIP = 0x0000681e, 348 GUEST_RFLAGS = 0x00006820, 349 GUEST_PENDING_DBG_EXCEPTIONS = 0x00006822, 350 GUEST_SYSENTER_ESP = 0x00006824, 351 GUEST_SYSENTER_EIP = 0x00006826, 352 HOST_CR0 = 0x00006c00, 353 HOST_CR3 = 0x00006c02, 354 HOST_CR4 = 0x00006c04, 355 HOST_FS_BASE = 0x00006c06, 356 HOST_GS_BASE = 0x00006c08, 357 HOST_TR_BASE = 0x00006c0a, 358 HOST_GDTR_BASE = 0x00006c0c, 359 HOST_IDTR_BASE = 0x00006c0e, 360 HOST_IA32_SYSENTER_ESP = 0x00006c10, 361 HOST_IA32_SYSENTER_EIP = 0x00006c12, 362 HOST_RSP = 0x00006c14, 363 HOST_RIP = 0x00006c16, 364}; 365 366/* 367 * Interruption-information format 368 */ 369#define INTR_INFO_VECTOR_MASK 0xff /* 7:0 */ 370#define INTR_INFO_INTR_TYPE_MASK 0x700 /* 10:8 */ 371#define INTR_INFO_DELIVER_CODE_MASK 0x800 /* 11 */ 372#define INTR_INFO_UNBLOCK_NMI 0x1000 /* 12 */ 373#define INTR_INFO_VALID_MASK 0x80000000 /* 31 */ 374#define INTR_INFO_RESVD_BITS_MASK 0x7ffff000 375 376#define VECTORING_INFO_VECTOR_MASK INTR_INFO_VECTOR_MASK 377#define VECTORING_INFO_TYPE_MASK INTR_INFO_INTR_TYPE_MASK 378#define VECTORING_INFO_DELIVER_CODE_MASK INTR_INFO_DELIVER_CODE_MASK 379#define VECTORING_INFO_VALID_MASK INTR_INFO_VALID_MASK 380 381#define INTR_TYPE_EXT_INTR (EVENT_TYPE_EXTINT << 8) /* external interrupt */ 382#define INTR_TYPE_RESERVED (EVENT_TYPE_RESERVED << 8) /* reserved */ 383#define INTR_TYPE_NMI_INTR (EVENT_TYPE_NMI << 8) /* NMI */ 384#define INTR_TYPE_HARD_EXCEPTION (EVENT_TYPE_HWEXC << 8) /* processor exception */ 385#define INTR_TYPE_SOFT_INTR (EVENT_TYPE_SWINT << 8) /* software interrupt */ 386#define INTR_TYPE_PRIV_SW_EXCEPTION (EVENT_TYPE_PRIV_SWEXC << 8) /* ICE breakpoint */ 387#define INTR_TYPE_SOFT_EXCEPTION (EVENT_TYPE_SWEXC << 8) /* software exception */ 388#define INTR_TYPE_OTHER_EVENT (EVENT_TYPE_OTHER << 8) /* other event */ 389 390/* GUEST_INTERRUPTIBILITY_INFO flags. */ 391#define GUEST_INTR_STATE_STI 0x00000001 392#define GUEST_INTR_STATE_MOV_SS 0x00000002 393#define GUEST_INTR_STATE_SMI 0x00000004 394#define GUEST_INTR_STATE_NMI 0x00000008 395#define GUEST_INTR_STATE_ENCLAVE_INTR 0x00000010 396 397/* GUEST_ACTIVITY_STATE flags */ 398#define GUEST_ACTIVITY_ACTIVE 0 399#define GUEST_ACTIVITY_HLT 1 400#define GUEST_ACTIVITY_SHUTDOWN 2 401#define GUEST_ACTIVITY_WAIT_SIPI 3 402 403/* 404 * Exit Qualifications for MOV for Control Register Access 405 */ 406#define CONTROL_REG_ACCESS_NUM 0x7 /* 2:0, number of control reg.*/ 407#define CONTROL_REG_ACCESS_TYPE 0x30 /* 5:4, access type */ 408#define CONTROL_REG_ACCESS_REG 0xf00 /* 10:8, general purpose reg. */ 409#define LMSW_SOURCE_DATA_SHIFT 16 410#define LMSW_SOURCE_DATA (0xFFFF << LMSW_SOURCE_DATA_SHIFT) /* 16:31 lmsw source */ 411#define REG_EAX (0 << 8) 412#define REG_ECX (1 << 8) 413#define REG_EDX (2 << 8) 414#define REG_EBX (3 << 8) 415#define REG_ESP (4 << 8) 416#define REG_EBP (5 << 8) 417#define REG_ESI (6 << 8) 418#define REG_EDI (7 << 8) 419#define REG_R8 (8 << 8) 420#define REG_R9 (9 << 8) 421#define REG_R10 (10 << 8) 422#define REG_R11 (11 << 8) 423#define REG_R12 (12 << 8) 424#define REG_R13 (13 << 8) 425#define REG_R14 (14 << 8) 426#define REG_R15 (15 << 8) 427 428/* 429 * Exit Qualifications for MOV for Debug Register Access 430 */ 431#define DEBUG_REG_ACCESS_NUM 0x7 /* 2:0, number of debug reg. */ 432#define DEBUG_REG_ACCESS_TYPE 0x10 /* 4, direction of access */ 433#define TYPE_MOV_TO_DR (0 << 4) 434#define TYPE_MOV_FROM_DR (1 << 4) 435#define DEBUG_REG_ACCESS_REG(eq) (((eq) >> 8) & 0xf) /* 11:8, general purpose reg. */ 436 437 438/* 439 * Exit Qualifications for APIC-Access 440 */ 441#define APIC_ACCESS_OFFSET 0xfff /* 11:0, offset within the APIC page */ 442#define APIC_ACCESS_TYPE 0xf000 /* 15:12, access type */ 443#define TYPE_LINEAR_APIC_INST_READ (0 << 12) 444#define TYPE_LINEAR_APIC_INST_WRITE (1 << 12) 445#define TYPE_LINEAR_APIC_INST_FETCH (2 << 12) 446#define TYPE_LINEAR_APIC_EVENT (3 << 12) 447#define TYPE_PHYSICAL_APIC_EVENT (10 << 12) 448#define TYPE_PHYSICAL_APIC_INST (15 << 12) 449 450/* segment AR in VMCS -- these are different from what LAR reports */ 451#define VMX_SEGMENT_AR_L_MASK (1 << 13) 452 453#define VMX_AR_TYPE_ACCESSES_MASK 1 454#define VMX_AR_TYPE_READABLE_MASK (1 << 1) 455#define VMX_AR_TYPE_WRITEABLE_MASK (1 << 2) 456#define VMX_AR_TYPE_CODE_MASK (1 << 3) 457#define VMX_AR_TYPE_MASK 0x0f 458#define VMX_AR_TYPE_BUSY_64_TSS 11 459#define VMX_AR_TYPE_BUSY_32_TSS 11 460#define VMX_AR_TYPE_BUSY_16_TSS 3 461#define VMX_AR_TYPE_LDT 2 462 463#define VMX_AR_UNUSABLE_MASK (1 << 16) 464#define VMX_AR_S_MASK (1 << 4) 465#define VMX_AR_P_MASK (1 << 7) 466#define VMX_AR_L_MASK (1 << 13) 467#define VMX_AR_DB_MASK (1 << 14) 468#define VMX_AR_G_MASK (1 << 15) 469#define VMX_AR_DPL_SHIFT 5 470#define VMX_AR_DPL(ar) (((ar) >> VMX_AR_DPL_SHIFT) & 3) 471 472#define VMX_AR_RESERVD_MASK 0xfffe0f00 473 474#define TSS_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 0) 475#define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 1) 476#define IDENTITY_PAGETABLE_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 2) 477 478#define VMX_NR_VPIDS (1 << 16) 479#define VMX_VPID_EXTENT_INDIVIDUAL_ADDR 0 480#define VMX_VPID_EXTENT_SINGLE_CONTEXT 1 481#define VMX_VPID_EXTENT_ALL_CONTEXT 2 482#define VMX_VPID_EXTENT_SINGLE_NON_GLOBAL 3 483 484#define VMX_EPT_EXTENT_CONTEXT 1 485#define VMX_EPT_EXTENT_GLOBAL 2 486#define VMX_EPT_EXTENT_SHIFT 24 487 488#define VMX_EPT_EXECUTE_ONLY_BIT (1ull) 489#define VMX_EPT_PAGE_WALK_4_BIT (1ull << 6) 490#define VMX_EPT_PAGE_WALK_5_BIT (1ull << 7) 491#define VMX_EPTP_UC_BIT (1ull << 8) 492#define VMX_EPTP_WB_BIT (1ull << 14) 493#define VMX_EPT_2MB_PAGE_BIT (1ull << 16) 494#define VMX_EPT_1GB_PAGE_BIT (1ull << 17) 495#define VMX_EPT_INVEPT_BIT (1ull << 20) 496#define VMX_EPT_AD_BIT (1ull << 21) 497#define VMX_EPT_EXTENT_CONTEXT_BIT (1ull << 25) 498#define VMX_EPT_EXTENT_GLOBAL_BIT (1ull << 26) 499 500#define VMX_VPID_INVVPID_BIT (1ull << 0) /* (32 - 32) */ 501#define VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT (1ull << 8) /* (40 - 32) */ 502#define VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT (1ull << 9) /* (41 - 32) */ 503#define VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT (1ull << 10) /* (42 - 32) */ 504#define VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT (1ull << 11) /* (43 - 32) */ 505 506#define VMX_EPT_MT_EPTE_SHIFT 3 507#define VMX_EPTP_PWL_MASK 0x38ull 508#define VMX_EPTP_PWL_4 0x18ull 509#define VMX_EPTP_PWL_5 0x20ull 510#define VMX_EPTP_AD_ENABLE_BIT (1ull << 6) 511#define VMX_EPTP_MT_MASK 0x7ull 512#define VMX_EPTP_MT_WB 0x6ull 513#define VMX_EPTP_MT_UC 0x0ull 514#define VMX_EPT_READABLE_MASK 0x1ull 515#define VMX_EPT_WRITABLE_MASK 0x2ull 516#define VMX_EPT_EXECUTABLE_MASK 0x4ull 517#define VMX_EPT_IPAT_BIT (1ull << 6) 518#define VMX_EPT_ACCESS_BIT (1ull << 8) 519#define VMX_EPT_DIRTY_BIT (1ull << 9) 520#define VMX_EPT_SUPPRESS_VE_BIT (1ull << 63) 521#define VMX_EPT_RWX_MASK (VMX_EPT_READABLE_MASK | \ 522 VMX_EPT_WRITABLE_MASK | \ 523 VMX_EPT_EXECUTABLE_MASK) 524#define VMX_EPT_MT_MASK (7ull << VMX_EPT_MT_EPTE_SHIFT) 525 526static inline u8 vmx_eptp_page_walk_level(u64 eptp) 527{ 528 u64 encoded_level = eptp & VMX_EPTP_PWL_MASK; 529 530 if (encoded_level == VMX_EPTP_PWL_5) 531 return 5; 532 533 /* @eptp must be pre-validated by the caller. */ 534 WARN_ON_ONCE(encoded_level != VMX_EPTP_PWL_4); 535 return 4; 536} 537 538/* The mask to use to trigger an EPT Misconfiguration in order to track MMIO */ 539#define VMX_EPT_MISCONFIG_WX_VALUE (VMX_EPT_WRITABLE_MASK | \ 540 VMX_EPT_EXECUTABLE_MASK) 541 542#define VMX_EPT_IDENTITY_PAGETABLE_ADDR 0xfffbc000ul 543 544struct vmx_msr_entry { 545 u32 index; 546 u32 reserved; 547 u64 value; 548} __aligned(16); 549 550/* 551 * Exit Qualifications for entry failure during or after loading guest state 552 */ 553enum vm_entry_failure_code { 554 ENTRY_FAIL_DEFAULT = 0, 555 ENTRY_FAIL_PDPTE = 2, 556 ENTRY_FAIL_NMI = 3, 557 ENTRY_FAIL_VMCS_LINK_PTR = 4, 558}; 559 560/* 561 * Exit Qualifications for EPT Violations 562 */ 563#define EPT_VIOLATION_ACC_READ_BIT 0 564#define EPT_VIOLATION_ACC_WRITE_BIT 1 565#define EPT_VIOLATION_ACC_INSTR_BIT 2 566#define EPT_VIOLATION_RWX_SHIFT 3 567#define EPT_VIOLATION_GVA_IS_VALID_BIT 7 568#define EPT_VIOLATION_GVA_TRANSLATED_BIT 8 569#define EPT_VIOLATION_ACC_READ (1 << EPT_VIOLATION_ACC_READ_BIT) 570#define EPT_VIOLATION_ACC_WRITE (1 << EPT_VIOLATION_ACC_WRITE_BIT) 571#define EPT_VIOLATION_ACC_INSTR (1 << EPT_VIOLATION_ACC_INSTR_BIT) 572#define EPT_VIOLATION_RWX_MASK (VMX_EPT_RWX_MASK << EPT_VIOLATION_RWX_SHIFT) 573#define EPT_VIOLATION_GVA_IS_VALID (1 << EPT_VIOLATION_GVA_IS_VALID_BIT) 574#define EPT_VIOLATION_GVA_TRANSLATED (1 << EPT_VIOLATION_GVA_TRANSLATED_BIT) 575 576/* 577 * Exit Qualifications for NOTIFY VM EXIT 578 */ 579#define NOTIFY_VM_CONTEXT_INVALID BIT(0) 580 581/* 582 * VM-instruction error numbers 583 */ 584enum vm_instruction_error_number { 585 VMXERR_VMCALL_IN_VMX_ROOT_OPERATION = 1, 586 VMXERR_VMCLEAR_INVALID_ADDRESS = 2, 587 VMXERR_VMCLEAR_VMXON_POINTER = 3, 588 VMXERR_VMLAUNCH_NONCLEAR_VMCS = 4, 589 VMXERR_VMRESUME_NONLAUNCHED_VMCS = 5, 590 VMXERR_VMRESUME_AFTER_VMXOFF = 6, 591 VMXERR_ENTRY_INVALID_CONTROL_FIELD = 7, 592 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD = 8, 593 VMXERR_VMPTRLD_INVALID_ADDRESS = 9, 594 VMXERR_VMPTRLD_VMXON_POINTER = 10, 595 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID = 11, 596 VMXERR_UNSUPPORTED_VMCS_COMPONENT = 12, 597 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT = 13, 598 VMXERR_VMXON_IN_VMX_ROOT_OPERATION = 15, 599 VMXERR_ENTRY_INVALID_EXECUTIVE_VMCS_POINTER = 16, 600 VMXERR_ENTRY_NONLAUNCHED_EXECUTIVE_VMCS = 17, 601 VMXERR_ENTRY_EXECUTIVE_VMCS_POINTER_NOT_VMXON_POINTER = 18, 602 VMXERR_VMCALL_NONCLEAR_VMCS = 19, 603 VMXERR_VMCALL_INVALID_VM_EXIT_CONTROL_FIELDS = 20, 604 VMXERR_VMCALL_INCORRECT_MSEG_REVISION_ID = 22, 605 VMXERR_VMXOFF_UNDER_DUAL_MONITOR_TREATMENT_OF_SMIS_AND_SMM = 23, 606 VMXERR_VMCALL_INVALID_SMM_MONITOR_FEATURES = 24, 607 VMXERR_ENTRY_INVALID_VM_EXECUTION_CONTROL_FIELDS_IN_EXECUTIVE_VMCS = 25, 608 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS = 26, 609 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID = 28, 610}; 611 612/* 613 * VM-instruction errors that can be encountered on VM-Enter, used to trace 614 * nested VM-Enter failures reported by hardware. Errors unique to VM-Enter 615 * from a SMI Transfer Monitor are not included as things have gone seriously 616 * sideways if we get one of those... 617 */ 618#define VMX_VMENTER_INSTRUCTION_ERRORS \ 619 { VMXERR_VMLAUNCH_NONCLEAR_VMCS, "VMLAUNCH_NONCLEAR_VMCS" }, \ 620 { VMXERR_VMRESUME_NONLAUNCHED_VMCS, "VMRESUME_NONLAUNCHED_VMCS" }, \ 621 { VMXERR_VMRESUME_AFTER_VMXOFF, "VMRESUME_AFTER_VMXOFF" }, \ 622 { VMXERR_ENTRY_INVALID_CONTROL_FIELD, "VMENTRY_INVALID_CONTROL_FIELD" }, \ 623 { VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, "VMENTRY_INVALID_HOST_STATE_FIELD" }, \ 624 { VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, "VMENTRY_EVENTS_BLOCKED_BY_MOV_SS" } 625 626enum vmx_l1d_flush_state { 627 VMENTER_L1D_FLUSH_AUTO, 628 VMENTER_L1D_FLUSH_NEVER, 629 VMENTER_L1D_FLUSH_COND, 630 VMENTER_L1D_FLUSH_ALWAYS, 631 VMENTER_L1D_FLUSH_EPT_DISABLED, 632 VMENTER_L1D_FLUSH_NOT_REQUIRED, 633}; 634 635extern enum vmx_l1d_flush_state l1tf_vmx_mitigation; 636 637struct vmx_ve_information { 638 u32 exit_reason; 639 u32 delivery; 640 u64 exit_qualification; 641 u64 guest_linear_address; 642 u64 guest_physical_address; 643 u16 eptp_index; 644}; 645 646#endif 647