150472Speter#ifndef _ASM_INTEL_DS_H 239145Sbrian#define _ASM_INTEL_DS_H 3149Srgrimes 437Srgrimes#include <linux/percpu-defs.h> 537Srgrimes 637Srgrimes#define BTS_BUFFER_SIZE (PAGE_SIZE << 4) 737Srgrimes#define PEBS_BUFFER_SIZE (PAGE_SIZE << 4) 837Srgrimes 925376Sjkh/* The maximal number of PEBS events: */ 1037Srgrimes#define MAX_PEBS_EVENTS_FMT4 8 1137Srgrimes#define MAX_PEBS_EVENTS 32 121280Sjkh#define MAX_FIXED_PEBS_EVENTS 16 1337Srgrimes 1437Srgrimes/* 1537Srgrimes * A debug store configuration. 1641441Sdillon * 171642Sache * We only support architectures that use 64bit fields. 1814592Sphk */ 1914594Sphkstruct debug_store { 2029082Sbrian u64 bts_buffer_base; 218573Srgrimes u64 bts_index; 228539Sache u64 bts_absolute_maximum; 23 u64 bts_interrupt_threshold; 24 u64 pebs_buffer_base; 25 u64 pebs_index; 26 u64 pebs_absolute_maximum; 27 u64 pebs_interrupt_threshold; 28 u64 pebs_event_reset[MAX_PEBS_EVENTS + MAX_FIXED_PEBS_EVENTS]; 29} __aligned(PAGE_SIZE); 30 31DECLARE_PER_CPU_PAGE_ALIGNED(struct debug_store, cpu_debug_store); 32 33struct debug_store_buffers { 34 char bts_buffer[BTS_BUFFER_SIZE]; 35 char pebs_buffer[PEBS_BUFFER_SIZE]; 36}; 37 38#endif 39