150276Speter/* SPDX-License-Identifier: GPL-2.0-only */ 2166124Srafan#ifndef _ASM_X86_APIC_H 3166124Srafan#define _ASM_X86_APIC_H 4166124Srafan 5166124Srafan#include <linux/cpumask.h> 6166124Srafan#include <linux/static_call.h> 7166124Srafan 8166124Srafan#include <asm/alternative.h> 9166124Srafan#include <asm/cpufeature.h> 10166124Srafan#include <asm/apicdef.h> 11166124Srafan#include <linux/atomic.h> 12166124Srafan#include <asm/fixmap.h> 13166124Srafan#include <asm/mpspec.h> 14166124Srafan#include <asm/msr.h> 15166124Srafan#include <asm/hardirq.h> 16166124Srafan#include <asm/io.h> 17166124Srafan#include <asm/posted_intr.h> 18166124Srafan 19166124Srafan#define ARCH_APICTIMER_STOPS_ON_C3 1 20166124Srafan 21166124Srafan/* 22166124Srafan * Debugging macros 23166124Srafan */ 24166124Srafan#define APIC_QUIET 0 25166124Srafan#define APIC_VERBOSE 1 26166124Srafan#define APIC_DEBUG 2 27166124Srafan 28166124Srafan/* Macros for apic_extnmi which controls external NMI masking */ 29166124Srafan#define APIC_EXTNMI_BSP 0 /* Default */ 3050276Speter#define APIC_EXTNMI_ALL 1 3150276Speter#define APIC_EXTNMI_NONE 2 3250276Speter 3350276Speter/* 3450276Speter * Define the default level of output to be very little 3550276Speter * This can be turned up by using apic=verbose for more 3650276Speter * information and apic=debug for _lots_ of information. 3750276Speter * apic_verbosity is defined in apic.c 3850276Speter */ 3950276Speter#define apic_printk(v, s, a...) do { \ 4066963Speter if ((v) <= apic_verbosity) \ 4150276Speter printk(s, ##a); \ 4250276Speter } while (0) 4350276Speter 4450276Speter 4550276Speter#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 4650276Speterextern void x86_32_probe_apic(void); 4750276Speter#else 4856639Speterstatic inline void x86_32_probe_apic(void) { } 4950276Speter#endif 5050276Speter 5150276Speterextern u32 cpuid_to_apicid[]; 5250276Speter 5350276Speter#define CPU_ACPIID_INVALID U32_MAX 5450276Speter 5550276Speter#ifdef CONFIG_X86_LOCAL_APIC 5650276Speter 5750276Speterextern int apic_verbosity; 5850276Speterextern int local_apic_timer_c2_ok; 5950276Speter 6050276Speterextern bool apic_is_disabled; 6150276Speterextern unsigned int lapic_timer_period; 6250276Speter 6350276Speterextern enum apic_intr_mode_id apic_intr_mode; 6450276Speterenum apic_intr_mode_id { 6550276Speter APIC_PIC, 6650276Speter APIC_VIRTUAL_WIRE, 6750276Speter APIC_VIRTUAL_WIRE_NO_CONFIG, 6850276Speter APIC_SYMMETRIC_IO, 6950276Speter APIC_SYMMETRIC_IO_NO_ROUTING 7050276Speter}; 7150276Speter 7250276Speter/* 73166124Srafan * With 82489DX we can't rely on apic feature bit 74166124Srafan * retrieved via cpuid but still have to deal with 75166124Srafan * such an apic chip so we assume that SMP configuration 76166124Srafan * is found from MP table (64bit case uses ACPI mostly 77166124Srafan * which set smp presence flag as well so we are safe 78166124Srafan * to use this helper too). 79166124Srafan */ 80166124Srafanstatic inline bool apic_from_smp_config(void) 8150276Speter{ 8250276Speter return smp_found_config && !apic_is_disabled; 8350276Speter} 8450276Speter 8550276Speter/* 8650276Speter * Basic functions accessing APICs. 8750276Speter */ 8850276Speter#ifdef CONFIG_PARAVIRT 8950276Speter#include <asm/paravirt.h> 9050276Speter#endif 9150276Speter 9250276Speterstatic inline void native_apic_mem_write(u32 reg, u32 v) 9350276Speter{ 94166124Srafan volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); 9550276Speter 9650276Speter alternative_io("movl %0, %1", "xchgl %0, %1", X86_BUG_11AP, 9750276Speter ASM_OUTPUT2("=r" (v), "=m" (*addr)), 9850276Speter ASM_OUTPUT2("0" (v), "m" (*addr))); 9950276Speter} 10050276Speter 10150276Speterstatic inline u32 native_apic_mem_read(u32 reg) 10250276Speter{ 10350276Speter return readl((void __iomem *)(APIC_BASE + reg)); 10450276Speter} 10550276Speter 10650276Speterstatic inline void native_apic_mem_eoi(void) 10750276Speter{ 10850276Speter native_apic_mem_write(APIC_EOI, APIC_EOI_ACK); 10950276Speter} 11050276Speter 11150276Speterextern void native_apic_icr_write(u32 low, u32 id); 11250276Speterextern u64 native_apic_icr_read(void); 11350276Speter 11450276Speterstatic inline bool apic_is_x2apic_enabled(void) 11550276Speter{ 11650276Speter u64 msr; 11750276Speter 11850276Speter if (rdmsrl_safe(MSR_IA32_APICBASE, &msr)) 11950276Speter return false; 12050276Speter return msr & X2APIC_ENABLE; 12150276Speter} 12250276Speter 12350276Speterextern void enable_IR_x2apic(void); 12450276Speter 12550276Speterextern int get_physical_broadcast(void); 12650276Speter 12750276Speterextern int lapic_get_maxlvt(void); 12850276Speterextern void clear_local_APIC(void); 12950276Speterextern void disconnect_bsp_APIC(int virt_wire_setup); 13050276Speterextern void disable_local_APIC(void); 13150276Speterextern void apic_soft_disable(void); 13250276Speterextern void lapic_shutdown(void); 13350276Speterextern void sync_Arb_IDs(void); 13466963Speterextern void init_bsp_APIC(void); 13566963Speterextern void apic_intr_mode_select(void); 13666963Speterextern void apic_intr_mode_init(void); 13766963Speterextern void init_apic_mappings(void); 13850276Spetervoid register_lapic_address(unsigned long address); 13950276Speterextern void setup_boot_APIC_clock(void); 14050276Speterextern void setup_secondary_APIC_clock(void); 14150276Speterextern void lapic_update_tsc_freq(void); 14250276Speter 14350276Speter#ifdef CONFIG_X86_64 14450276Speterstatic inline bool apic_force_enable(unsigned long addr) 14550276Speter{ 14650276Speter return false; 14750276Speter} 14850276Speter#else 14950276Speterextern bool apic_force_enable(unsigned long addr); 15050276Speter#endif 15150276Speter 15256639Speterextern void apic_ap_setup(void); 15350276Speter 15450276Speter/* 15550276Speter * On 32bit this is mach-xxx local 15650276Speter */ 15750276Speter#ifdef CONFIG_X86_64 15850276Speterextern int apic_is_clustered_box(void); 15950276Speter#else 16050276Speterstatic inline int apic_is_clustered_box(void) 16150276Speter{ 16250276Speter return 0; 16350276Speter} 16450276Speter#endif 16550276Speter 16650276Speterextern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask); 16750276Speterextern void lapic_assign_system_vectors(void); 16850276Speterextern void lapic_assign_legacy_vector(unsigned int isairq, bool replace); 16950276Speterextern void lapic_update_legacy_vectors(void); 17050276Speterextern void lapic_online(void); 17150276Speterextern void lapic_offline(void); 17250276Speterextern bool apic_needs_pit(void); 17350276Speter 17450276Speterextern void apic_send_IPI_allbutself(unsigned int vector); 17550276Speter 17650276Speterextern void topology_register_apic(u32 apic_id, u32 acpi_id, bool present); 17750276Speterextern void topology_register_boot_apic(u32 apic_id); 17850276Speterextern int topology_hotplug_apic(u32 apic_id, u32 acpi_id); 17950276Speterextern void topology_hotunplug_apic(unsigned int cpu); 18050276Speterextern void topology_apply_cmdline_limits_early(void); 18150276Speterextern void topology_init_possible_cpus(void); 18250276Speterextern void topology_reset_possible_cpus_up(void); 18350276Speter 18450276Speter#else /* !CONFIG_X86_LOCAL_APIC */ 18550276Speterstatic inline void lapic_shutdown(void) { } 18650276Speter#define local_apic_timer_c2_ok 1 18750276Speterstatic inline void init_apic_mappings(void) { } 18850276Speterstatic inline void disable_local_APIC(void) { } 18950276Speter# define setup_boot_APIC_clock x86_init_noop 19050276Speter# define setup_secondary_APIC_clock x86_init_noop 19150276Speterstatic inline void lapic_update_tsc_freq(void) { } 19250276Speterstatic inline void init_bsp_APIC(void) { } 19350276Speterstatic inline void apic_intr_mode_select(void) { } 19450276Speterstatic inline void apic_intr_mode_init(void) { } 19550276Speterstatic inline void lapic_assign_system_vectors(void) { } 19650276Speterstatic inline void lapic_assign_legacy_vector(unsigned int i, bool r) { } 19750276Speterstatic inline bool apic_needs_pit(void) { return true; } 19850276Speterstatic inline void topology_apply_cmdline_limits_early(void) { } 19950276Speterstatic inline void topology_init_possible_cpus(void) { } 20050276Speter#endif /* !CONFIG_X86_LOCAL_APIC */ 20150276Speter 20250276Speter#ifdef CONFIG_X86_X2APIC 20350276Speterstatic inline void native_apic_msr_write(u32 reg, u32 v) 20450276Speter{ 20550276Speter if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || 20650276Speter reg == APIC_LVR) 20750276Speter return; 20850276Speter 20966963Speter wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); 21050276Speter} 211 212static inline void native_apic_msr_eoi(void) 213{ 214 __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0); 215} 216 217static inline u32 native_apic_msr_read(u32 reg) 218{ 219 u64 msr; 220 221 if (reg == APIC_DFR) 222 return -1; 223 224 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr); 225 return (u32)msr; 226} 227 228static inline void native_x2apic_icr_write(u32 low, u32 id) 229{ 230 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); 231} 232 233static inline u64 native_x2apic_icr_read(void) 234{ 235 unsigned long val; 236 237 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); 238 return val; 239} 240 241extern int x2apic_mode; 242extern int x2apic_phys; 243extern void __init x2apic_set_max_apicid(u32 apicid); 244extern void x2apic_setup(void); 245static inline int x2apic_enabled(void) 246{ 247 return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled(); 248} 249 250#define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC)) 251#else /* !CONFIG_X86_X2APIC */ 252static inline void x2apic_setup(void) { } 253static inline int x2apic_enabled(void) { return 0; } 254static inline u32 native_apic_msr_read(u32 reg) { BUG(); } 255#define x2apic_mode (0) 256#define x2apic_supported() (0) 257#endif /* !CONFIG_X86_X2APIC */ 258extern void __init check_x2apic(void); 259 260struct irq_data; 261 262/* 263 * Copyright 2004 James Cleverdon, IBM. 264 * 265 * Generic APIC sub-arch data struct. 266 * 267 * Hacked for x86-64 by James Cleverdon from i386 architecture code by 268 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and 269 * James Cleverdon. 270 */ 271struct apic { 272 /* Hotpath functions first */ 273 void (*eoi)(void); 274 void (*native_eoi)(void); 275 void (*write)(u32 reg, u32 v); 276 u32 (*read)(u32 reg); 277 278 /* IPI related functions */ 279 void (*wait_icr_idle)(void); 280 u32 (*safe_wait_icr_idle)(void); 281 282 void (*send_IPI)(int cpu, int vector); 283 void (*send_IPI_mask)(const struct cpumask *mask, int vector); 284 void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec); 285 void (*send_IPI_allbutself)(int vector); 286 void (*send_IPI_all)(int vector); 287 void (*send_IPI_self)(int vector); 288 289 u32 disable_esr : 1, 290 dest_mode_logical : 1, 291 x2apic_set_max_apicid : 1, 292 nmi_to_offline_cpu : 1; 293 294 u32 (*calc_dest_apicid)(unsigned int cpu); 295 296 /* ICR related functions */ 297 u64 (*icr_read)(void); 298 void (*icr_write)(u32 low, u32 high); 299 300 /* The limit of the APIC ID space. */ 301 u32 max_apic_id; 302 303 /* Probe, setup and smpboot functions */ 304 int (*probe)(void); 305 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); 306 307 void (*init_apic_ldr)(void); 308 u32 (*cpu_present_to_apicid)(int mps_cpu); 309 310 u32 (*get_apic_id)(u32 id); 311 312 /* wakeup_secondary_cpu */ 313 int (*wakeup_secondary_cpu)(u32 apicid, unsigned long start_eip); 314 /* wakeup secondary CPU using 64-bit wakeup point */ 315 int (*wakeup_secondary_cpu_64)(u32 apicid, unsigned long start_eip); 316 317 char *name; 318}; 319 320struct apic_override { 321 void (*eoi)(void); 322 void (*native_eoi)(void); 323 void (*write)(u32 reg, u32 v); 324 u32 (*read)(u32 reg); 325 void (*send_IPI)(int cpu, int vector); 326 void (*send_IPI_mask)(const struct cpumask *mask, int vector); 327 void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec); 328 void (*send_IPI_allbutself)(int vector); 329 void (*send_IPI_all)(int vector); 330 void (*send_IPI_self)(int vector); 331 u64 (*icr_read)(void); 332 void (*icr_write)(u32 low, u32 high); 333 int (*wakeup_secondary_cpu)(u32 apicid, unsigned long start_eip); 334 int (*wakeup_secondary_cpu_64)(u32 apicid, unsigned long start_eip); 335}; 336 337/* 338 * Pointer to the local APIC driver in use on this system (there's 339 * always just one such driver in use - the kernel decides via an 340 * early probing process which one it picks - and then sticks to it): 341 */ 342extern struct apic *apic; 343 344/* 345 * APIC drivers are probed based on how they are listed in the .apicdrivers 346 * section. So the order is important and enforced by the ordering 347 * of different apic driver files in the Makefile. 348 * 349 * For the files having two apic drivers, we use apic_drivers() 350 * to enforce the order with in them. 351 */ 352#define apic_driver(sym) \ 353 static const struct apic *__apicdrivers_##sym __used \ 354 __aligned(sizeof(struct apic *)) \ 355 __section(".apicdrivers") = { &sym } 356 357#define apic_drivers(sym1, sym2) \ 358 static struct apic *__apicdrivers_##sym1##sym2[2] __used \ 359 __aligned(sizeof(struct apic *)) \ 360 __section(".apicdrivers") = { &sym1, &sym2 } 361 362extern struct apic *__apicdrivers[], *__apicdrivers_end[]; 363 364/* 365 * APIC functionality to boot other CPUs - only used on SMP: 366 */ 367#ifdef CONFIG_SMP 368extern int lapic_can_unplug_cpu(void); 369#endif 370 371#ifdef CONFIG_X86_LOCAL_APIC 372extern struct apic_override __x86_apic_override; 373 374void __init apic_setup_apic_calls(void); 375void __init apic_install_driver(struct apic *driver); 376 377#define apic_update_callback(_callback, _fn) { \ 378 __x86_apic_override._callback = _fn; \ 379 apic->_callback = _fn; \ 380 static_call_update(apic_call_##_callback, _fn); \ 381 pr_info("APIC: %s() replaced with %ps()\n", #_callback, _fn); \ 382} 383 384#define DECLARE_APIC_CALL(__cb) \ 385 DECLARE_STATIC_CALL(apic_call_##__cb, *apic->__cb) 386 387DECLARE_APIC_CALL(eoi); 388DECLARE_APIC_CALL(native_eoi); 389DECLARE_APIC_CALL(icr_read); 390DECLARE_APIC_CALL(icr_write); 391DECLARE_APIC_CALL(read); 392DECLARE_APIC_CALL(send_IPI); 393DECLARE_APIC_CALL(send_IPI_mask); 394DECLARE_APIC_CALL(send_IPI_mask_allbutself); 395DECLARE_APIC_CALL(send_IPI_allbutself); 396DECLARE_APIC_CALL(send_IPI_all); 397DECLARE_APIC_CALL(send_IPI_self); 398DECLARE_APIC_CALL(wait_icr_idle); 399DECLARE_APIC_CALL(wakeup_secondary_cpu); 400DECLARE_APIC_CALL(wakeup_secondary_cpu_64); 401DECLARE_APIC_CALL(write); 402 403static __always_inline u32 apic_read(u32 reg) 404{ 405 return static_call(apic_call_read)(reg); 406} 407 408static __always_inline void apic_write(u32 reg, u32 val) 409{ 410 static_call(apic_call_write)(reg, val); 411} 412 413static __always_inline void apic_eoi(void) 414{ 415 static_call(apic_call_eoi)(); 416} 417 418static __always_inline void apic_native_eoi(void) 419{ 420 static_call(apic_call_native_eoi)(); 421} 422 423static __always_inline u64 apic_icr_read(void) 424{ 425 return static_call(apic_call_icr_read)(); 426} 427 428static __always_inline void apic_icr_write(u32 low, u32 high) 429{ 430 static_call(apic_call_icr_write)(low, high); 431} 432 433static __always_inline void __apic_send_IPI(int cpu, int vector) 434{ 435 static_call(apic_call_send_IPI)(cpu, vector); 436} 437 438static __always_inline void __apic_send_IPI_mask(const struct cpumask *mask, int vector) 439{ 440 static_call_mod(apic_call_send_IPI_mask)(mask, vector); 441} 442 443static __always_inline void __apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) 444{ 445 static_call(apic_call_send_IPI_mask_allbutself)(mask, vector); 446} 447 448static __always_inline void __apic_send_IPI_allbutself(int vector) 449{ 450 static_call(apic_call_send_IPI_allbutself)(vector); 451} 452 453static __always_inline void __apic_send_IPI_all(int vector) 454{ 455 static_call(apic_call_send_IPI_all)(vector); 456} 457 458static __always_inline void __apic_send_IPI_self(int vector) 459{ 460 static_call_mod(apic_call_send_IPI_self)(vector); 461} 462 463static __always_inline void apic_wait_icr_idle(void) 464{ 465 static_call_cond(apic_call_wait_icr_idle)(); 466} 467 468static __always_inline u32 safe_apic_wait_icr_idle(void) 469{ 470 return apic->safe_wait_icr_idle ? apic->safe_wait_icr_idle() : 0; 471} 472 473static __always_inline bool apic_id_valid(u32 apic_id) 474{ 475 return apic_id <= apic->max_apic_id; 476} 477 478#else /* CONFIG_X86_LOCAL_APIC */ 479 480static inline u32 apic_read(u32 reg) { return 0; } 481static inline void apic_write(u32 reg, u32 val) { } 482static inline void apic_eoi(void) { } 483static inline u64 apic_icr_read(void) { return 0; } 484static inline void apic_icr_write(u32 low, u32 high) { } 485static inline void apic_wait_icr_idle(void) { } 486static inline u32 safe_apic_wait_icr_idle(void) { return 0; } 487static inline void apic_set_eoi_cb(void (*eoi)(void)) {} 488static inline void apic_native_eoi(void) { WARN_ON_ONCE(1); } 489static inline void apic_setup_apic_calls(void) { } 490 491#define apic_update_callback(_callback, _fn) do { } while (0) 492 493#endif /* CONFIG_X86_LOCAL_APIC */ 494 495extern void apic_ack_irq(struct irq_data *data); 496 497static inline bool lapic_vector_set_in_irr(unsigned int vector) 498{ 499 u32 irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); 500 501 return !!(irr & (1U << (vector % 32))); 502} 503 504static inline bool is_vector_pending(unsigned int vector) 505{ 506 return lapic_vector_set_in_irr(vector) || pi_pending_this_cpu(vector); 507} 508 509/* 510 * Warm reset vector position: 511 */ 512#define TRAMPOLINE_PHYS_LOW 0x467 513#define TRAMPOLINE_PHYS_HIGH 0x469 514 515extern void generic_bigsmp_probe(void); 516 517#ifdef CONFIG_X86_LOCAL_APIC 518 519#include <asm/smp.h> 520 521extern struct apic apic_noop; 522 523static inline u32 read_apic_id(void) 524{ 525 u32 reg = apic_read(APIC_ID); 526 527 return apic->get_apic_id(reg); 528} 529 530#ifdef CONFIG_X86_64 531typedef int (*wakeup_cpu_handler)(int apicid, unsigned long start_eip); 532extern int default_acpi_madt_oem_check(char *, char *); 533extern void x86_64_probe_apic(void); 534#else 535static inline int default_acpi_madt_oem_check(char *a, char *b) { return 0; } 536static inline void x86_64_probe_apic(void) { } 537#endif 538 539extern int default_apic_id_valid(u32 apicid); 540 541extern u32 apic_default_calc_apicid(unsigned int cpu); 542extern u32 apic_flat_calc_apicid(unsigned int cpu); 543 544extern u32 default_cpu_present_to_apicid(int mps_cpu); 545 546void apic_send_nmi_to_offline_cpu(unsigned int cpu); 547 548#else /* CONFIG_X86_LOCAL_APIC */ 549 550static inline u32 read_apic_id(void) { return 0; } 551 552#endif /* !CONFIG_X86_LOCAL_APIC */ 553 554#ifdef CONFIG_SMP 555void apic_smt_update(void); 556#else 557static inline void apic_smt_update(void) { } 558#endif 559 560struct msi_msg; 561struct irq_cfg; 562 563extern void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg, 564 bool dmar); 565 566extern void ioapic_zap_locks(void); 567 568#endif /* _ASM_X86_APIC_H */ 569