1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation 4 * 5 * Rewrite, cleanup: 6 * 7 * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation 8 * Copyright (C) 2006 Olof Johansson <olof@lixom.net> 9 * 10 * Dynamic DMA mapping support, pSeries-specific parts, both SMP and LPAR. 11 */ 12 13#include <linux/init.h> 14#include <linux/types.h> 15#include <linux/slab.h> 16#include <linux/mm.h> 17#include <linux/memblock.h> 18#include <linux/spinlock.h> 19#include <linux/string.h> 20#include <linux/pci.h> 21#include <linux/dma-mapping.h> 22#include <linux/crash_dump.h> 23#include <linux/memory.h> 24#include <linux/of.h> 25#include <linux/of_address.h> 26#include <linux/iommu.h> 27#include <linux/rculist.h> 28#include <asm/io.h> 29#include <asm/prom.h> 30#include <asm/rtas.h> 31#include <asm/iommu.h> 32#include <asm/pci-bridge.h> 33#include <asm/machdep.h> 34#include <asm/firmware.h> 35#include <asm/tce.h> 36#include <asm/ppc-pci.h> 37#include <asm/udbg.h> 38#include <asm/mmzone.h> 39#include <asm/plpar_wrappers.h> 40 41#include "pseries.h" 42 43enum { 44 DDW_QUERY_PE_DMA_WIN = 0, 45 DDW_CREATE_PE_DMA_WIN = 1, 46 DDW_REMOVE_PE_DMA_WIN = 2, 47 48 DDW_APPLICABLE_SIZE 49}; 50 51enum { 52 DDW_EXT_SIZE = 0, 53 DDW_EXT_RESET_DMA_WIN = 1, 54 DDW_EXT_QUERY_OUT_SIZE = 2 55}; 56 57static struct iommu_table *iommu_pseries_alloc_table(int node) 58{ 59 struct iommu_table *tbl; 60 61 tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, node); 62 if (!tbl) 63 return NULL; 64 65 INIT_LIST_HEAD_RCU(&tbl->it_group_list); 66 kref_init(&tbl->it_kref); 67 return tbl; 68} 69 70static struct iommu_table_group *iommu_pseries_alloc_group(int node) 71{ 72 struct iommu_table_group *table_group; 73 74 table_group = kzalloc_node(sizeof(*table_group), GFP_KERNEL, node); 75 if (!table_group) 76 return NULL; 77 78#ifdef CONFIG_IOMMU_API 79 table_group->ops = &spapr_tce_table_group_ops; 80 table_group->pgsizes = SZ_4K; 81#endif 82 83 table_group->tables[0] = iommu_pseries_alloc_table(node); 84 if (table_group->tables[0]) 85 return table_group; 86 87 kfree(table_group); 88 return NULL; 89} 90 91static void iommu_pseries_free_group(struct iommu_table_group *table_group, 92 const char *node_name) 93{ 94 if (!table_group) 95 return; 96 97#ifdef CONFIG_IOMMU_API 98 if (table_group->group) { 99 iommu_group_put(table_group->group); 100 BUG_ON(table_group->group); 101 } 102#endif 103 104 /* Default DMA window table is at index 0, while DDW at 1. SR-IOV 105 * adapters only have table on index 1. 106 */ 107 if (table_group->tables[0]) 108 iommu_tce_table_put(table_group->tables[0]); 109 110 if (table_group->tables[1]) 111 iommu_tce_table_put(table_group->tables[1]); 112 113 kfree(table_group); 114} 115 116static int tce_build_pSeries(struct iommu_table *tbl, long index, 117 long npages, unsigned long uaddr, 118 enum dma_data_direction direction, 119 unsigned long attrs) 120{ 121 u64 proto_tce; 122 __be64 *tcep; 123 u64 rpn; 124 const unsigned long tceshift = tbl->it_page_shift; 125 const unsigned long pagesize = IOMMU_PAGE_SIZE(tbl); 126 127 proto_tce = TCE_PCI_READ; // Read allowed 128 129 if (direction != DMA_TO_DEVICE) 130 proto_tce |= TCE_PCI_WRITE; 131 132 tcep = ((__be64 *)tbl->it_base) + index; 133 134 while (npages--) { 135 /* can't move this out since we might cross MEMBLOCK boundary */ 136 rpn = __pa(uaddr) >> tceshift; 137 *tcep = cpu_to_be64(proto_tce | rpn << tceshift); 138 139 uaddr += pagesize; 140 tcep++; 141 } 142 return 0; 143} 144 145 146static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages) 147{ 148 __be64 *tcep; 149 150 tcep = ((__be64 *)tbl->it_base) + index; 151 152 while (npages--) 153 *(tcep++) = 0; 154} 155 156static unsigned long tce_get_pseries(struct iommu_table *tbl, long index) 157{ 158 __be64 *tcep; 159 160 tcep = ((__be64 *)tbl->it_base) + index; 161 162 return be64_to_cpu(*tcep); 163} 164 165static void tce_free_pSeriesLP(unsigned long liobn, long, long, long); 166static void tce_freemulti_pSeriesLP(struct iommu_table*, long, long); 167 168static int tce_build_pSeriesLP(unsigned long liobn, long tcenum, long tceshift, 169 long npages, unsigned long uaddr, 170 enum dma_data_direction direction, 171 unsigned long attrs) 172{ 173 u64 rc = 0; 174 u64 proto_tce, tce; 175 u64 rpn; 176 int ret = 0; 177 long tcenum_start = tcenum, npages_start = npages; 178 179 rpn = __pa(uaddr) >> tceshift; 180 proto_tce = TCE_PCI_READ; 181 if (direction != DMA_TO_DEVICE) 182 proto_tce |= TCE_PCI_WRITE; 183 184 while (npages--) { 185 tce = proto_tce | rpn << tceshift; 186 rc = plpar_tce_put((u64)liobn, (u64)tcenum << tceshift, tce); 187 188 if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) { 189 ret = (int)rc; 190 tce_free_pSeriesLP(liobn, tcenum_start, tceshift, 191 (npages_start - (npages + 1))); 192 break; 193 } 194 195 if (rc && printk_ratelimit()) { 196 printk("tce_build_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc); 197 printk("\tindex = 0x%llx\n", (u64)liobn); 198 printk("\ttcenum = 0x%llx\n", (u64)tcenum); 199 printk("\ttce val = 0x%llx\n", tce ); 200 dump_stack(); 201 } 202 203 tcenum++; 204 rpn++; 205 } 206 return ret; 207} 208 209static DEFINE_PER_CPU(__be64 *, tce_page); 210 211static int tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum, 212 long npages, unsigned long uaddr, 213 enum dma_data_direction direction, 214 unsigned long attrs) 215{ 216 u64 rc = 0; 217 u64 proto_tce; 218 __be64 *tcep; 219 u64 rpn; 220 long l, limit; 221 long tcenum_start = tcenum, npages_start = npages; 222 int ret = 0; 223 unsigned long flags; 224 const unsigned long tceshift = tbl->it_page_shift; 225 226 if ((npages == 1) || !firmware_has_feature(FW_FEATURE_PUT_TCE_IND)) { 227 return tce_build_pSeriesLP(tbl->it_index, tcenum, 228 tceshift, npages, uaddr, 229 direction, attrs); 230 } 231 232 local_irq_save(flags); /* to protect tcep and the page behind it */ 233 234 tcep = __this_cpu_read(tce_page); 235 236 /* This is safe to do since interrupts are off when we're called 237 * from iommu_alloc{,_sg}() 238 */ 239 if (!tcep) { 240 tcep = (__be64 *)__get_free_page(GFP_ATOMIC); 241 /* If allocation fails, fall back to the loop implementation */ 242 if (!tcep) { 243 local_irq_restore(flags); 244 return tce_build_pSeriesLP(tbl->it_index, tcenum, 245 tceshift, 246 npages, uaddr, direction, attrs); 247 } 248 __this_cpu_write(tce_page, tcep); 249 } 250 251 rpn = __pa(uaddr) >> tceshift; 252 proto_tce = TCE_PCI_READ; 253 if (direction != DMA_TO_DEVICE) 254 proto_tce |= TCE_PCI_WRITE; 255 256 /* We can map max one pageful of TCEs at a time */ 257 do { 258 /* 259 * Set up the page with TCE data, looping through and setting 260 * the values. 261 */ 262 limit = min_t(long, npages, 4096 / TCE_ENTRY_SIZE); 263 264 for (l = 0; l < limit; l++) { 265 tcep[l] = cpu_to_be64(proto_tce | rpn << tceshift); 266 rpn++; 267 } 268 269 rc = plpar_tce_put_indirect((u64)tbl->it_index, 270 (u64)tcenum << tceshift, 271 (u64)__pa(tcep), 272 limit); 273 274 npages -= limit; 275 tcenum += limit; 276 } while (npages > 0 && !rc); 277 278 local_irq_restore(flags); 279 280 if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) { 281 ret = (int)rc; 282 tce_freemulti_pSeriesLP(tbl, tcenum_start, 283 (npages_start - (npages + limit))); 284 return ret; 285 } 286 287 if (rc && printk_ratelimit()) { 288 printk("tce_buildmulti_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc); 289 printk("\tindex = 0x%llx\n", (u64)tbl->it_index); 290 printk("\tnpages = 0x%llx\n", (u64)npages); 291 printk("\ttce[0] val = 0x%llx\n", tcep[0]); 292 dump_stack(); 293 } 294 return ret; 295} 296 297static void tce_free_pSeriesLP(unsigned long liobn, long tcenum, long tceshift, 298 long npages) 299{ 300 u64 rc; 301 302 while (npages--) { 303 rc = plpar_tce_put((u64)liobn, (u64)tcenum << tceshift, 0); 304 305 if (rc && printk_ratelimit()) { 306 printk("tce_free_pSeriesLP: plpar_tce_put failed. rc=%lld\n", rc); 307 printk("\tindex = 0x%llx\n", (u64)liobn); 308 printk("\ttcenum = 0x%llx\n", (u64)tcenum); 309 dump_stack(); 310 } 311 312 tcenum++; 313 } 314} 315 316 317static void tce_freemulti_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages) 318{ 319 u64 rc; 320 long rpages = npages; 321 unsigned long limit; 322 323 if (!firmware_has_feature(FW_FEATURE_STUFF_TCE)) 324 return tce_free_pSeriesLP(tbl->it_index, tcenum, 325 tbl->it_page_shift, npages); 326 327 do { 328 limit = min_t(unsigned long, rpages, 512); 329 330 rc = plpar_tce_stuff((u64)tbl->it_index, 331 (u64)tcenum << tbl->it_page_shift, 0, limit); 332 333 rpages -= limit; 334 tcenum += limit; 335 } while (rpages > 0 && !rc); 336 337 if (rc && printk_ratelimit()) { 338 printk("tce_freemulti_pSeriesLP: plpar_tce_stuff failed\n"); 339 printk("\trc = %lld\n", rc); 340 printk("\tindex = 0x%llx\n", (u64)tbl->it_index); 341 printk("\tnpages = 0x%llx\n", (u64)npages); 342 dump_stack(); 343 } 344} 345 346static unsigned long tce_get_pSeriesLP(struct iommu_table *tbl, long tcenum) 347{ 348 u64 rc; 349 unsigned long tce_ret; 350 351 rc = plpar_tce_get((u64)tbl->it_index, 352 (u64)tcenum << tbl->it_page_shift, &tce_ret); 353 354 if (rc && printk_ratelimit()) { 355 printk("tce_get_pSeriesLP: plpar_tce_get failed. rc=%lld\n", rc); 356 printk("\tindex = 0x%llx\n", (u64)tbl->it_index); 357 printk("\ttcenum = 0x%llx\n", (u64)tcenum); 358 dump_stack(); 359 } 360 361 return tce_ret; 362} 363 364/* this is compatible with cells for the device tree property */ 365struct dynamic_dma_window_prop { 366 __be32 liobn; /* tce table number */ 367 __be64 dma_base; /* address hi,lo */ 368 __be32 tce_shift; /* ilog2(tce_page_size) */ 369 __be32 window_shift; /* ilog2(tce_window_size) */ 370}; 371 372struct dma_win { 373 struct device_node *device; 374 const struct dynamic_dma_window_prop *prop; 375 bool direct; 376 struct list_head list; 377}; 378 379/* Dynamic DMA Window support */ 380struct ddw_query_response { 381 u32 windows_available; 382 u64 largest_available_block; 383 u32 page_size; 384 u32 migration_capable; 385}; 386 387struct ddw_create_response { 388 u32 liobn; 389 u32 addr_hi; 390 u32 addr_lo; 391}; 392 393static LIST_HEAD(dma_win_list); 394/* prevents races between memory on/offline and window creation */ 395static DEFINE_SPINLOCK(dma_win_list_lock); 396/* protects initializing window twice for same device */ 397static DEFINE_MUTEX(dma_win_init_mutex); 398 399static int tce_clearrange_multi_pSeriesLP(unsigned long start_pfn, 400 unsigned long num_pfn, const void *arg) 401{ 402 const struct dynamic_dma_window_prop *maprange = arg; 403 int rc; 404 u64 tce_size, num_tce, dma_offset, next; 405 u32 tce_shift; 406 long limit; 407 408 tce_shift = be32_to_cpu(maprange->tce_shift); 409 tce_size = 1ULL << tce_shift; 410 next = start_pfn << PAGE_SHIFT; 411 num_tce = num_pfn << PAGE_SHIFT; 412 413 /* round back to the beginning of the tce page size */ 414 num_tce += next & (tce_size - 1); 415 next &= ~(tce_size - 1); 416 417 /* covert to number of tces */ 418 num_tce |= tce_size - 1; 419 num_tce >>= tce_shift; 420 421 do { 422 /* 423 * Set up the page with TCE data, looping through and setting 424 * the values. 425 */ 426 limit = min_t(long, num_tce, 512); 427 dma_offset = next + be64_to_cpu(maprange->dma_base); 428 429 rc = plpar_tce_stuff((u64)be32_to_cpu(maprange->liobn), 430 dma_offset, 431 0, limit); 432 next += limit * tce_size; 433 num_tce -= limit; 434 } while (num_tce > 0 && !rc); 435 436 return rc; 437} 438 439static int tce_setrange_multi_pSeriesLP(unsigned long start_pfn, 440 unsigned long num_pfn, const void *arg) 441{ 442 const struct dynamic_dma_window_prop *maprange = arg; 443 u64 tce_size, num_tce, dma_offset, next, proto_tce, liobn; 444 __be64 *tcep; 445 u32 tce_shift; 446 u64 rc = 0; 447 long l, limit; 448 449 if (!firmware_has_feature(FW_FEATURE_PUT_TCE_IND)) { 450 unsigned long tceshift = be32_to_cpu(maprange->tce_shift); 451 unsigned long dmastart = (start_pfn << PAGE_SHIFT) + 452 be64_to_cpu(maprange->dma_base); 453 unsigned long tcenum = dmastart >> tceshift; 454 unsigned long npages = num_pfn << PAGE_SHIFT >> tceshift; 455 void *uaddr = __va(start_pfn << PAGE_SHIFT); 456 457 return tce_build_pSeriesLP(be32_to_cpu(maprange->liobn), 458 tcenum, tceshift, npages, (unsigned long) uaddr, 459 DMA_BIDIRECTIONAL, 0); 460 } 461 462 local_irq_disable(); /* to protect tcep and the page behind it */ 463 tcep = __this_cpu_read(tce_page); 464 465 if (!tcep) { 466 tcep = (__be64 *)__get_free_page(GFP_ATOMIC); 467 if (!tcep) { 468 local_irq_enable(); 469 return -ENOMEM; 470 } 471 __this_cpu_write(tce_page, tcep); 472 } 473 474 proto_tce = TCE_PCI_READ | TCE_PCI_WRITE; 475 476 liobn = (u64)be32_to_cpu(maprange->liobn); 477 tce_shift = be32_to_cpu(maprange->tce_shift); 478 tce_size = 1ULL << tce_shift; 479 next = start_pfn << PAGE_SHIFT; 480 num_tce = num_pfn << PAGE_SHIFT; 481 482 /* round back to the beginning of the tce page size */ 483 num_tce += next & (tce_size - 1); 484 next &= ~(tce_size - 1); 485 486 /* covert to number of tces */ 487 num_tce |= tce_size - 1; 488 num_tce >>= tce_shift; 489 490 /* We can map max one pageful of TCEs at a time */ 491 do { 492 /* 493 * Set up the page with TCE data, looping through and setting 494 * the values. 495 */ 496 limit = min_t(long, num_tce, 4096 / TCE_ENTRY_SIZE); 497 dma_offset = next + be64_to_cpu(maprange->dma_base); 498 499 for (l = 0; l < limit; l++) { 500 tcep[l] = cpu_to_be64(proto_tce | next); 501 next += tce_size; 502 } 503 504 rc = plpar_tce_put_indirect(liobn, 505 dma_offset, 506 (u64)__pa(tcep), 507 limit); 508 509 num_tce -= limit; 510 } while (num_tce > 0 && !rc); 511 512 /* error cleanup: caller will clear whole range */ 513 514 local_irq_enable(); 515 return rc; 516} 517 518static int tce_setrange_multi_pSeriesLP_walk(unsigned long start_pfn, 519 unsigned long num_pfn, void *arg) 520{ 521 return tce_setrange_multi_pSeriesLP(start_pfn, num_pfn, arg); 522} 523 524static void iommu_table_setparms_common(struct iommu_table *tbl, unsigned long busno, 525 unsigned long liobn, unsigned long win_addr, 526 unsigned long window_size, unsigned long page_shift, 527 void *base, struct iommu_table_ops *table_ops) 528{ 529 tbl->it_busno = busno; 530 tbl->it_index = liobn; 531 tbl->it_offset = win_addr >> page_shift; 532 tbl->it_size = window_size >> page_shift; 533 tbl->it_page_shift = page_shift; 534 tbl->it_base = (unsigned long)base; 535 tbl->it_blocksize = 16; 536 tbl->it_type = TCE_PCI; 537 tbl->it_ops = table_ops; 538} 539 540struct iommu_table_ops iommu_table_pseries_ops; 541 542static void iommu_table_setparms(struct pci_controller *phb, 543 struct device_node *dn, 544 struct iommu_table *tbl) 545{ 546 struct device_node *node; 547 const unsigned long *basep; 548 const u32 *sizep; 549 550 /* Test if we are going over 2GB of DMA space */ 551 if (phb->dma_window_base_cur + phb->dma_window_size > SZ_2G) { 552 udbg_printf("PCI_DMA: Unexpected number of IOAs under this PHB.\n"); 553 panic("PCI_DMA: Unexpected number of IOAs under this PHB.\n"); 554 } 555 556 node = phb->dn; 557 basep = of_get_property(node, "linux,tce-base", NULL); 558 sizep = of_get_property(node, "linux,tce-size", NULL); 559 if (basep == NULL || sizep == NULL) { 560 printk(KERN_ERR "PCI_DMA: iommu_table_setparms: %pOF has " 561 "missing tce entries !\n", dn); 562 return; 563 } 564 565 iommu_table_setparms_common(tbl, phb->bus->number, 0, phb->dma_window_base_cur, 566 phb->dma_window_size, IOMMU_PAGE_SHIFT_4K, 567 __va(*basep), &iommu_table_pseries_ops); 568 569 if (!is_kdump_kernel()) 570 memset((void *)tbl->it_base, 0, *sizep); 571 572 phb->dma_window_base_cur += phb->dma_window_size; 573} 574 575struct iommu_table_ops iommu_table_lpar_multi_ops; 576 577struct iommu_table_ops iommu_table_pseries_ops = { 578 .set = tce_build_pSeries, 579 .clear = tce_free_pSeries, 580 .get = tce_get_pseries 581}; 582 583static void pci_dma_bus_setup_pSeries(struct pci_bus *bus) 584{ 585 struct device_node *dn; 586 struct iommu_table *tbl; 587 struct device_node *isa_dn, *isa_dn_orig; 588 struct device_node *tmp; 589 struct pci_dn *pci; 590 int children; 591 592 dn = pci_bus_to_OF_node(bus); 593 594 pr_debug("pci_dma_bus_setup_pSeries: setting up bus %pOF\n", dn); 595 596 if (bus->self) { 597 /* This is not a root bus, any setup will be done for the 598 * device-side of the bridge in iommu_dev_setup_pSeries(). 599 */ 600 return; 601 } 602 pci = PCI_DN(dn); 603 604 /* Check if the ISA bus on the system is under 605 * this PHB. 606 */ 607 isa_dn = isa_dn_orig = of_find_node_by_type(NULL, "isa"); 608 609 while (isa_dn && isa_dn != dn) 610 isa_dn = isa_dn->parent; 611 612 of_node_put(isa_dn_orig); 613 614 /* Count number of direct PCI children of the PHB. */ 615 for (children = 0, tmp = dn->child; tmp; tmp = tmp->sibling) 616 children++; 617 618 pr_debug("Children: %d\n", children); 619 620 /* Calculate amount of DMA window per slot. Each window must be 621 * a power of two (due to pci_alloc_consistent requirements). 622 * 623 * Keep 256MB aside for PHBs with ISA. 624 */ 625 626 if (!isa_dn) { 627 /* No ISA/IDE - just set window size and return */ 628 pci->phb->dma_window_size = 0x80000000ul; /* To be divided */ 629 630 while (pci->phb->dma_window_size * children > 0x80000000ul) 631 pci->phb->dma_window_size >>= 1; 632 pr_debug("No ISA/IDE, window size is 0x%llx\n", 633 pci->phb->dma_window_size); 634 pci->phb->dma_window_base_cur = 0; 635 636 return; 637 } 638 639 /* If we have ISA, then we probably have an IDE 640 * controller too. Allocate a 128MB table but 641 * skip the first 128MB to avoid stepping on ISA 642 * space. 643 */ 644 pci->phb->dma_window_size = 0x8000000ul; 645 pci->phb->dma_window_base_cur = 0x8000000ul; 646 647 pci->table_group = iommu_pseries_alloc_group(pci->phb->node); 648 tbl = pci->table_group->tables[0]; 649 650 iommu_table_setparms(pci->phb, dn, tbl); 651 652 if (!iommu_init_table(tbl, pci->phb->node, 0, 0)) 653 panic("Failed to initialize iommu table"); 654 655 /* Divide the rest (1.75GB) among the children */ 656 pci->phb->dma_window_size = 0x80000000ul; 657 while (pci->phb->dma_window_size * children > 0x70000000ul) 658 pci->phb->dma_window_size >>= 1; 659 660 pr_debug("ISA/IDE, window size is 0x%llx\n", pci->phb->dma_window_size); 661} 662 663#ifdef CONFIG_IOMMU_API 664static int tce_exchange_pseries(struct iommu_table *tbl, long index, unsigned 665 long *tce, enum dma_data_direction *direction) 666{ 667 long rc; 668 unsigned long ioba = (unsigned long) index << tbl->it_page_shift; 669 unsigned long flags, oldtce = 0; 670 u64 proto_tce = iommu_direction_to_tce_perm(*direction); 671 unsigned long newtce = *tce | proto_tce; 672 673 spin_lock_irqsave(&tbl->large_pool.lock, flags); 674 675 rc = plpar_tce_get((u64)tbl->it_index, ioba, &oldtce); 676 if (!rc) 677 rc = plpar_tce_put((u64)tbl->it_index, ioba, newtce); 678 679 if (!rc) { 680 *direction = iommu_tce_direction(oldtce); 681 *tce = oldtce & ~(TCE_PCI_READ | TCE_PCI_WRITE); 682 } 683 684 spin_unlock_irqrestore(&tbl->large_pool.lock, flags); 685 686 return rc; 687} 688#endif 689 690struct iommu_table_ops iommu_table_lpar_multi_ops = { 691 .set = tce_buildmulti_pSeriesLP, 692#ifdef CONFIG_IOMMU_API 693 .xchg_no_kill = tce_exchange_pseries, 694#endif 695 .clear = tce_freemulti_pSeriesLP, 696 .get = tce_get_pSeriesLP 697}; 698 699/* 700 * Find nearest ibm,dma-window (default DMA window) or direct DMA window or 701 * dynamic 64bit DMA window, walking up the device tree. 702 */ 703static struct device_node *pci_dma_find(struct device_node *dn, 704 struct dynamic_dma_window_prop *prop) 705{ 706 const __be32 *default_prop = NULL; 707 const __be32 *ddw_prop = NULL; 708 struct device_node *rdn = NULL; 709 bool default_win = false, ddw_win = false; 710 711 for ( ; dn && PCI_DN(dn); dn = dn->parent) { 712 default_prop = of_get_property(dn, "ibm,dma-window", NULL); 713 if (default_prop) { 714 rdn = dn; 715 default_win = true; 716 } 717 ddw_prop = of_get_property(dn, DIRECT64_PROPNAME, NULL); 718 if (ddw_prop) { 719 rdn = dn; 720 ddw_win = true; 721 break; 722 } 723 ddw_prop = of_get_property(dn, DMA64_PROPNAME, NULL); 724 if (ddw_prop) { 725 rdn = dn; 726 ddw_win = true; 727 break; 728 } 729 730 /* At least found default window, which is the case for normal boot */ 731 if (default_win) 732 break; 733 } 734 735 /* For PCI devices there will always be a DMA window, either on the device 736 * or parent bus 737 */ 738 WARN_ON(!(default_win | ddw_win)); 739 740 /* caller doesn't want to get DMA window property */ 741 if (!prop) 742 return rdn; 743 744 /* parse DMA window property. During normal system boot, only default 745 * DMA window is passed in OF. But, for kdump, a dedicated adapter might 746 * have both default and DDW in FDT. In this scenario, DDW takes precedence 747 * over default window. 748 */ 749 if (ddw_win) { 750 struct dynamic_dma_window_prop *p; 751 752 p = (struct dynamic_dma_window_prop *)ddw_prop; 753 prop->liobn = p->liobn; 754 prop->dma_base = p->dma_base; 755 prop->tce_shift = p->tce_shift; 756 prop->window_shift = p->window_shift; 757 } else if (default_win) { 758 unsigned long offset, size, liobn; 759 760 of_parse_dma_window(rdn, default_prop, &liobn, &offset, &size); 761 762 prop->liobn = cpu_to_be32((u32)liobn); 763 prop->dma_base = cpu_to_be64(offset); 764 prop->tce_shift = cpu_to_be32(IOMMU_PAGE_SHIFT_4K); 765 prop->window_shift = cpu_to_be32(order_base_2(size)); 766 } 767 768 return rdn; 769} 770 771static void pci_dma_bus_setup_pSeriesLP(struct pci_bus *bus) 772{ 773 struct iommu_table *tbl; 774 struct device_node *dn, *pdn; 775 struct pci_dn *ppci; 776 struct dynamic_dma_window_prop prop; 777 778 dn = pci_bus_to_OF_node(bus); 779 780 pr_debug("pci_dma_bus_setup_pSeriesLP: setting up bus %pOF\n", 781 dn); 782 783 pdn = pci_dma_find(dn, &prop); 784 785 /* In PPC architecture, there will always be DMA window on bus or one of the 786 * parent bus. During reboot, there will be ibm,dma-window property to 787 * define DMA window. For kdump, there will at least be default window or DDW 788 * or both. 789 * There is an exception to the above. In case the PE goes into frozen 790 * state, firmware may not provide ibm,dma-window property at the time 791 * of LPAR boot up. 792 */ 793 794 if (!pdn) { 795 pr_debug(" no ibm,dma-window property !\n"); 796 return; 797 } 798 799 ppci = PCI_DN(pdn); 800 801 pr_debug(" parent is %pOF, iommu_table: 0x%p\n", 802 pdn, ppci->table_group); 803 804 if (!ppci->table_group) { 805 ppci->table_group = iommu_pseries_alloc_group(ppci->phb->node); 806 tbl = ppci->table_group->tables[0]; 807 808 iommu_table_setparms_common(tbl, ppci->phb->bus->number, 809 be32_to_cpu(prop.liobn), 810 be64_to_cpu(prop.dma_base), 811 1ULL << be32_to_cpu(prop.window_shift), 812 be32_to_cpu(prop.tce_shift), NULL, 813 &iommu_table_lpar_multi_ops); 814 815 /* Only for normal boot with default window. Doesn't matter even 816 * if we set these with DDW which is 64bit during kdump, since 817 * these will not be used during kdump. 818 */ 819 ppci->table_group->tce32_start = be64_to_cpu(prop.dma_base); 820 ppci->table_group->tce32_size = 1 << be32_to_cpu(prop.window_shift); 821 822 if (!iommu_init_table(tbl, ppci->phb->node, 0, 0)) 823 panic("Failed to initialize iommu table"); 824 825 iommu_register_group(ppci->table_group, 826 pci_domain_nr(bus), 0); 827 pr_debug(" created table: %p\n", ppci->table_group); 828 } 829} 830 831 832static void pci_dma_dev_setup_pSeries(struct pci_dev *dev) 833{ 834 struct device_node *dn; 835 struct iommu_table *tbl; 836 837 pr_debug("pci_dma_dev_setup_pSeries: %s\n", pci_name(dev)); 838 839 dn = dev->dev.of_node; 840 841 /* If we're the direct child of a root bus, then we need to allocate 842 * an iommu table ourselves. The bus setup code should have setup 843 * the window sizes already. 844 */ 845 if (!dev->bus->self) { 846 struct pci_controller *phb = PCI_DN(dn)->phb; 847 848 pr_debug(" --> first child, no bridge. Allocating iommu table.\n"); 849 PCI_DN(dn)->table_group = iommu_pseries_alloc_group(phb->node); 850 tbl = PCI_DN(dn)->table_group->tables[0]; 851 iommu_table_setparms(phb, dn, tbl); 852 853 if (!iommu_init_table(tbl, phb->node, 0, 0)) 854 panic("Failed to initialize iommu table"); 855 856 set_iommu_table_base(&dev->dev, tbl); 857 return; 858 } 859 860 /* If this device is further down the bus tree, search upwards until 861 * an already allocated iommu table is found and use that. 862 */ 863 864 while (dn && PCI_DN(dn) && PCI_DN(dn)->table_group == NULL) 865 dn = dn->parent; 866 867 if (dn && PCI_DN(dn)) 868 set_iommu_table_base(&dev->dev, 869 PCI_DN(dn)->table_group->tables[0]); 870 else 871 printk(KERN_WARNING "iommu: Device %s has no iommu table\n", 872 pci_name(dev)); 873} 874 875static int __read_mostly disable_ddw; 876 877static int __init disable_ddw_setup(char *str) 878{ 879 disable_ddw = 1; 880 printk(KERN_INFO "ppc iommu: disabling ddw.\n"); 881 882 return 0; 883} 884 885early_param("disable_ddw", disable_ddw_setup); 886 887static void clean_dma_window(struct device_node *np, struct dynamic_dma_window_prop *dwp) 888{ 889 int ret; 890 891 ret = tce_clearrange_multi_pSeriesLP(0, 892 1ULL << (be32_to_cpu(dwp->window_shift) - PAGE_SHIFT), dwp); 893 if (ret) 894 pr_warn("%pOF failed to clear tces in window.\n", 895 np); 896 else 897 pr_debug("%pOF successfully cleared tces in window.\n", 898 np); 899} 900 901/* 902 * Call only if DMA window is clean. 903 */ 904static void __remove_dma_window(struct device_node *np, u32 *ddw_avail, u64 liobn) 905{ 906 int ret; 907 908 ret = rtas_call(ddw_avail[DDW_REMOVE_PE_DMA_WIN], 1, 1, NULL, liobn); 909 if (ret) 910 pr_warn("%pOF: failed to remove DMA window: rtas returned " 911 "%d to ibm,remove-pe-dma-window(%x) %llx\n", 912 np, ret, ddw_avail[DDW_REMOVE_PE_DMA_WIN], liobn); 913 else 914 pr_debug("%pOF: successfully removed DMA window: rtas returned " 915 "%d to ibm,remove-pe-dma-window(%x) %llx\n", 916 np, ret, ddw_avail[DDW_REMOVE_PE_DMA_WIN], liobn); 917} 918 919static void remove_dma_window(struct device_node *np, u32 *ddw_avail, 920 struct property *win) 921{ 922 struct dynamic_dma_window_prop *dwp; 923 u64 liobn; 924 925 dwp = win->value; 926 liobn = (u64)be32_to_cpu(dwp->liobn); 927 928 clean_dma_window(np, dwp); 929 __remove_dma_window(np, ddw_avail, liobn); 930} 931 932static int remove_ddw(struct device_node *np, bool remove_prop, const char *win_name) 933{ 934 struct property *win; 935 u32 ddw_avail[DDW_APPLICABLE_SIZE]; 936 int ret = 0; 937 938 win = of_find_property(np, win_name, NULL); 939 if (!win) 940 return -EINVAL; 941 942 ret = of_property_read_u32_array(np, "ibm,ddw-applicable", 943 &ddw_avail[0], DDW_APPLICABLE_SIZE); 944 if (ret) 945 return 0; 946 947 948 if (win->length >= sizeof(struct dynamic_dma_window_prop)) 949 remove_dma_window(np, ddw_avail, win); 950 951 if (!remove_prop) 952 return 0; 953 954 ret = of_remove_property(np, win); 955 if (ret) 956 pr_warn("%pOF: failed to remove DMA window property: %d\n", 957 np, ret); 958 return 0; 959} 960 961static bool find_existing_ddw(struct device_node *pdn, u64 *dma_addr, int *window_shift, 962 bool *direct_mapping) 963{ 964 struct dma_win *window; 965 const struct dynamic_dma_window_prop *dma64; 966 bool found = false; 967 968 spin_lock(&dma_win_list_lock); 969 /* check if we already created a window and dupe that config if so */ 970 list_for_each_entry(window, &dma_win_list, list) { 971 if (window->device == pdn) { 972 dma64 = window->prop; 973 *dma_addr = be64_to_cpu(dma64->dma_base); 974 *window_shift = be32_to_cpu(dma64->window_shift); 975 *direct_mapping = window->direct; 976 found = true; 977 break; 978 } 979 } 980 spin_unlock(&dma_win_list_lock); 981 982 return found; 983} 984 985static struct dma_win *ddw_list_new_entry(struct device_node *pdn, 986 const struct dynamic_dma_window_prop *dma64) 987{ 988 struct dma_win *window; 989 990 window = kzalloc(sizeof(*window), GFP_KERNEL); 991 if (!window) 992 return NULL; 993 994 window->device = pdn; 995 window->prop = dma64; 996 window->direct = false; 997 998 return window; 999} 1000 1001static void find_existing_ddw_windows_named(const char *name) 1002{ 1003 int len; 1004 struct device_node *pdn; 1005 struct dma_win *window; 1006 const struct dynamic_dma_window_prop *dma64; 1007 1008 for_each_node_with_property(pdn, name) { 1009 dma64 = of_get_property(pdn, name, &len); 1010 if (!dma64 || len < sizeof(*dma64)) { 1011 remove_ddw(pdn, true, name); 1012 continue; 1013 } 1014 1015 /* If at the time of system initialization, there are DDWs in OF, 1016 * it means this is during kexec. DDW could be direct or dynamic. 1017 * We will just mark DDWs as "dynamic" since this is kdump path, 1018 * no need to worry about perforance. ddw_list_new_entry() will 1019 * set window->direct = false. 1020 */ 1021 window = ddw_list_new_entry(pdn, dma64); 1022 if (!window) { 1023 of_node_put(pdn); 1024 break; 1025 } 1026 1027 spin_lock(&dma_win_list_lock); 1028 list_add(&window->list, &dma_win_list); 1029 spin_unlock(&dma_win_list_lock); 1030 } 1031} 1032 1033static int find_existing_ddw_windows(void) 1034{ 1035 if (!firmware_has_feature(FW_FEATURE_LPAR)) 1036 return 0; 1037 1038 find_existing_ddw_windows_named(DIRECT64_PROPNAME); 1039 find_existing_ddw_windows_named(DMA64_PROPNAME); 1040 1041 return 0; 1042} 1043machine_arch_initcall(pseries, find_existing_ddw_windows); 1044 1045/** 1046 * ddw_read_ext - Get the value of an DDW extension 1047 * @np: device node from which the extension value is to be read. 1048 * @extnum: index number of the extension. 1049 * @value: pointer to return value, modified when extension is available. 1050 * 1051 * Checks if "ibm,ddw-extensions" exists for this node, and get the value 1052 * on index 'extnum'. 1053 * It can be used only to check if a property exists, passing value == NULL. 1054 * 1055 * Returns: 1056 * 0 if extension successfully read 1057 * -EINVAL if the "ibm,ddw-extensions" does not exist, 1058 * -ENODATA if "ibm,ddw-extensions" does not have a value, and 1059 * -EOVERFLOW if "ibm,ddw-extensions" does not contain this extension. 1060 */ 1061static inline int ddw_read_ext(const struct device_node *np, int extnum, 1062 u32 *value) 1063{ 1064 static const char propname[] = "ibm,ddw-extensions"; 1065 u32 count; 1066 int ret; 1067 1068 ret = of_property_read_u32_index(np, propname, DDW_EXT_SIZE, &count); 1069 if (ret) 1070 return ret; 1071 1072 if (count < extnum) 1073 return -EOVERFLOW; 1074 1075 if (!value) 1076 value = &count; 1077 1078 return of_property_read_u32_index(np, propname, extnum, value); 1079} 1080 1081static int query_ddw(struct pci_dev *dev, const u32 *ddw_avail, 1082 struct ddw_query_response *query, 1083 struct device_node *parent) 1084{ 1085 struct device_node *dn; 1086 struct pci_dn *pdn; 1087 u32 cfg_addr, ext_query, query_out[5]; 1088 u64 buid; 1089 int ret, out_sz; 1090 1091 /* 1092 * From LoPAR level 2.8, "ibm,ddw-extensions" index 3 can rule how many 1093 * output parameters ibm,query-pe-dma-windows will have, ranging from 1094 * 5 to 6. 1095 */ 1096 ret = ddw_read_ext(parent, DDW_EXT_QUERY_OUT_SIZE, &ext_query); 1097 if (!ret && ext_query == 1) 1098 out_sz = 6; 1099 else 1100 out_sz = 5; 1101 1102 /* 1103 * Get the config address and phb buid of the PE window. 1104 * Rely on eeh to retrieve this for us. 1105 * Retrieve them from the pci device, not the node with the 1106 * dma-window property 1107 */ 1108 dn = pci_device_to_OF_node(dev); 1109 pdn = PCI_DN(dn); 1110 buid = pdn->phb->buid; 1111 cfg_addr = ((pdn->busno << 16) | (pdn->devfn << 8)); 1112 1113 ret = rtas_call(ddw_avail[DDW_QUERY_PE_DMA_WIN], 3, out_sz, query_out, 1114 cfg_addr, BUID_HI(buid), BUID_LO(buid)); 1115 1116 switch (out_sz) { 1117 case 5: 1118 query->windows_available = query_out[0]; 1119 query->largest_available_block = query_out[1]; 1120 query->page_size = query_out[2]; 1121 query->migration_capable = query_out[3]; 1122 break; 1123 case 6: 1124 query->windows_available = query_out[0]; 1125 query->largest_available_block = ((u64)query_out[1] << 32) | 1126 query_out[2]; 1127 query->page_size = query_out[3]; 1128 query->migration_capable = query_out[4]; 1129 break; 1130 } 1131 1132 dev_info(&dev->dev, "ibm,query-pe-dma-windows(%x) %x %x %x returned %d, lb=%llx ps=%x wn=%d\n", 1133 ddw_avail[DDW_QUERY_PE_DMA_WIN], cfg_addr, BUID_HI(buid), 1134 BUID_LO(buid), ret, query->largest_available_block, 1135 query->page_size, query->windows_available); 1136 1137 return ret; 1138} 1139 1140static int create_ddw(struct pci_dev *dev, const u32 *ddw_avail, 1141 struct ddw_create_response *create, int page_shift, 1142 int window_shift) 1143{ 1144 struct device_node *dn; 1145 struct pci_dn *pdn; 1146 u32 cfg_addr; 1147 u64 buid; 1148 int ret; 1149 1150 /* 1151 * Get the config address and phb buid of the PE window. 1152 * Rely on eeh to retrieve this for us. 1153 * Retrieve them from the pci device, not the node with the 1154 * dma-window property 1155 */ 1156 dn = pci_device_to_OF_node(dev); 1157 pdn = PCI_DN(dn); 1158 buid = pdn->phb->buid; 1159 cfg_addr = ((pdn->busno << 16) | (pdn->devfn << 8)); 1160 1161 do { 1162 /* extra outputs are LIOBN and dma-addr (hi, lo) */ 1163 ret = rtas_call(ddw_avail[DDW_CREATE_PE_DMA_WIN], 5, 4, 1164 (u32 *)create, cfg_addr, BUID_HI(buid), 1165 BUID_LO(buid), page_shift, window_shift); 1166 } while (rtas_busy_delay(ret)); 1167 dev_info(&dev->dev, 1168 "ibm,create-pe-dma-window(%x) %x %x %x %x %x returned %d " 1169 "(liobn = 0x%x starting addr = %x %x)\n", 1170 ddw_avail[DDW_CREATE_PE_DMA_WIN], cfg_addr, BUID_HI(buid), 1171 BUID_LO(buid), page_shift, window_shift, ret, create->liobn, 1172 create->addr_hi, create->addr_lo); 1173 1174 return ret; 1175} 1176 1177struct failed_ddw_pdn { 1178 struct device_node *pdn; 1179 struct list_head list; 1180}; 1181 1182static LIST_HEAD(failed_ddw_pdn_list); 1183 1184static phys_addr_t ddw_memory_hotplug_max(void) 1185{ 1186 resource_size_t max_addr = memory_hotplug_max(); 1187 struct device_node *memory; 1188 1189 for_each_node_by_type(memory, "memory") { 1190 struct resource res; 1191 1192 if (of_address_to_resource(memory, 0, &res)) 1193 continue; 1194 1195 max_addr = max_t(resource_size_t, max_addr, res.end + 1); 1196 } 1197 1198 return max_addr; 1199} 1200 1201/* 1202 * Platforms supporting the DDW option starting with LoPAR level 2.7 implement 1203 * ibm,ddw-extensions, which carries the rtas token for 1204 * ibm,reset-pe-dma-windows. 1205 * That rtas-call can be used to restore the default DMA window for the device. 1206 */ 1207static void reset_dma_window(struct pci_dev *dev, struct device_node *par_dn) 1208{ 1209 int ret; 1210 u32 cfg_addr, reset_dma_win; 1211 u64 buid; 1212 struct device_node *dn; 1213 struct pci_dn *pdn; 1214 1215 ret = ddw_read_ext(par_dn, DDW_EXT_RESET_DMA_WIN, &reset_dma_win); 1216 if (ret) 1217 return; 1218 1219 dn = pci_device_to_OF_node(dev); 1220 pdn = PCI_DN(dn); 1221 buid = pdn->phb->buid; 1222 cfg_addr = (pdn->busno << 16) | (pdn->devfn << 8); 1223 1224 ret = rtas_call(reset_dma_win, 3, 1, NULL, cfg_addr, BUID_HI(buid), 1225 BUID_LO(buid)); 1226 if (ret) 1227 dev_info(&dev->dev, 1228 "ibm,reset-pe-dma-windows(%x) %x %x %x returned %d ", 1229 reset_dma_win, cfg_addr, BUID_HI(buid), BUID_LO(buid), 1230 ret); 1231} 1232 1233/* Return largest page shift based on "IO Page Sizes" output of ibm,query-pe-dma-window. */ 1234static int iommu_get_page_shift(u32 query_page_size) 1235{ 1236 /* Supported IO page-sizes according to LoPAR, note that 2M is out of order */ 1237 const int shift[] = { 1238 __builtin_ctzll(SZ_4K), __builtin_ctzll(SZ_64K), __builtin_ctzll(SZ_16M), 1239 __builtin_ctzll(SZ_32M), __builtin_ctzll(SZ_64M), __builtin_ctzll(SZ_128M), 1240 __builtin_ctzll(SZ_256M), __builtin_ctzll(SZ_16G), __builtin_ctzll(SZ_2M) 1241 }; 1242 1243 int i = ARRAY_SIZE(shift) - 1; 1244 int ret = 0; 1245 1246 /* 1247 * On LoPAR, ibm,query-pe-dma-window outputs "IO Page Sizes" using a bit field: 1248 * - bit 31 means 4k pages are supported, 1249 * - bit 30 means 64k pages are supported, and so on. 1250 * Larger pagesizes map more memory with the same amount of TCEs, so start probing them. 1251 */ 1252 for (; i >= 0 ; i--) { 1253 if (query_page_size & (1 << i)) 1254 ret = max(ret, shift[i]); 1255 } 1256 1257 return ret; 1258} 1259 1260static struct property *ddw_property_create(const char *propname, u32 liobn, u64 dma_addr, 1261 u32 page_shift, u32 window_shift) 1262{ 1263 struct dynamic_dma_window_prop *ddwprop; 1264 struct property *win64; 1265 1266 win64 = kzalloc(sizeof(*win64), GFP_KERNEL); 1267 if (!win64) 1268 return NULL; 1269 1270 win64->name = kstrdup(propname, GFP_KERNEL); 1271 ddwprop = kzalloc(sizeof(*ddwprop), GFP_KERNEL); 1272 win64->value = ddwprop; 1273 win64->length = sizeof(*ddwprop); 1274 if (!win64->name || !win64->value) { 1275 kfree(win64->name); 1276 kfree(win64->value); 1277 kfree(win64); 1278 return NULL; 1279 } 1280 1281 ddwprop->liobn = cpu_to_be32(liobn); 1282 ddwprop->dma_base = cpu_to_be64(dma_addr); 1283 ddwprop->tce_shift = cpu_to_be32(page_shift); 1284 ddwprop->window_shift = cpu_to_be32(window_shift); 1285 1286 return win64; 1287} 1288 1289/* 1290 * If the PE supports dynamic dma windows, and there is space for a table 1291 * that can map all pages in a linear offset, then setup such a table, 1292 * and record the dma-offset in the struct device. 1293 * 1294 * dev: the pci device we are checking 1295 * pdn: the parent pe node with the ibm,dma_window property 1296 * Future: also check if we can remap the base window for our base page size 1297 * 1298 * returns true if can map all pages (direct mapping), false otherwise.. 1299 */ 1300static bool enable_ddw(struct pci_dev *dev, struct device_node *pdn) 1301{ 1302 int len = 0, ret; 1303 int max_ram_len = order_base_2(ddw_memory_hotplug_max()); 1304 struct ddw_query_response query; 1305 struct ddw_create_response create; 1306 int page_shift; 1307 u64 win_addr; 1308 const char *win_name; 1309 struct device_node *dn; 1310 u32 ddw_avail[DDW_APPLICABLE_SIZE]; 1311 struct dma_win *window; 1312 struct property *win64; 1313 struct failed_ddw_pdn *fpdn; 1314 bool default_win_removed = false, direct_mapping = false; 1315 bool pmem_present; 1316 struct pci_dn *pci = PCI_DN(pdn); 1317 struct property *default_win = NULL; 1318 1319 dn = of_find_node_by_type(NULL, "ibm,pmemory"); 1320 pmem_present = dn != NULL; 1321 of_node_put(dn); 1322 1323 mutex_lock(&dma_win_init_mutex); 1324 1325 if (find_existing_ddw(pdn, &dev->dev.archdata.dma_offset, &len, &direct_mapping)) 1326 goto out_unlock; 1327 1328 /* 1329 * If we already went through this for a previous function of 1330 * the same device and failed, we don't want to muck with the 1331 * DMA window again, as it will race with in-flight operations 1332 * and can lead to EEHs. The above mutex protects access to the 1333 * list. 1334 */ 1335 list_for_each_entry(fpdn, &failed_ddw_pdn_list, list) { 1336 if (fpdn->pdn == pdn) 1337 goto out_unlock; 1338 } 1339 1340 /* 1341 * the ibm,ddw-applicable property holds the tokens for: 1342 * ibm,query-pe-dma-window 1343 * ibm,create-pe-dma-window 1344 * ibm,remove-pe-dma-window 1345 * for the given node in that order. 1346 * the property is actually in the parent, not the PE 1347 */ 1348 ret = of_property_read_u32_array(pdn, "ibm,ddw-applicable", 1349 &ddw_avail[0], DDW_APPLICABLE_SIZE); 1350 if (ret) 1351 goto out_failed; 1352 1353 /* 1354 * Query if there is a second window of size to map the 1355 * whole partition. Query returns number of windows, largest 1356 * block assigned to PE (partition endpoint), and two bitmasks 1357 * of page sizes: supported and supported for migrate-dma. 1358 */ 1359 dn = pci_device_to_OF_node(dev); 1360 ret = query_ddw(dev, ddw_avail, &query, pdn); 1361 if (ret != 0) 1362 goto out_failed; 1363 1364 /* 1365 * If there is no window available, remove the default DMA window, 1366 * if it's present. This will make all the resources available to the 1367 * new DDW window. 1368 * If anything fails after this, we need to restore it, so also check 1369 * for extensions presence. 1370 */ 1371 if (query.windows_available == 0) { 1372 int reset_win_ext; 1373 1374 /* DDW + IOMMU on single window may fail if there is any allocation */ 1375 if (iommu_table_in_use(pci->table_group->tables[0])) { 1376 dev_warn(&dev->dev, "current IOMMU table in use, can't be replaced.\n"); 1377 goto out_failed; 1378 } 1379 1380 default_win = of_find_property(pdn, "ibm,dma-window", NULL); 1381 if (!default_win) 1382 goto out_failed; 1383 1384 reset_win_ext = ddw_read_ext(pdn, DDW_EXT_RESET_DMA_WIN, NULL); 1385 if (reset_win_ext) 1386 goto out_failed; 1387 1388 remove_dma_window(pdn, ddw_avail, default_win); 1389 default_win_removed = true; 1390 1391 /* Query again, to check if the window is available */ 1392 ret = query_ddw(dev, ddw_avail, &query, pdn); 1393 if (ret != 0) 1394 goto out_failed; 1395 1396 if (query.windows_available == 0) { 1397 /* no windows are available for this device. */ 1398 dev_dbg(&dev->dev, "no free dynamic windows"); 1399 goto out_failed; 1400 } 1401 } 1402 1403 page_shift = iommu_get_page_shift(query.page_size); 1404 if (!page_shift) { 1405 dev_dbg(&dev->dev, "no supported page size in mask %x", 1406 query.page_size); 1407 goto out_failed; 1408 } 1409 1410 1411 /* 1412 * The "ibm,pmemory" can appear anywhere in the address space. 1413 * Assuming it is still backed by page structs, try MAX_PHYSMEM_BITS 1414 * for the upper limit and fallback to max RAM otherwise but this 1415 * disables device::dma_ops_bypass. 1416 */ 1417 len = max_ram_len; 1418 if (pmem_present) { 1419 if (query.largest_available_block >= 1420 (1ULL << (MAX_PHYSMEM_BITS - page_shift))) 1421 len = MAX_PHYSMEM_BITS; 1422 else 1423 dev_info(&dev->dev, "Skipping ibm,pmemory"); 1424 } 1425 1426 /* check if the available block * number of ptes will map everything */ 1427 if (query.largest_available_block < (1ULL << (len - page_shift))) { 1428 dev_dbg(&dev->dev, 1429 "can't map partition max 0x%llx with %llu %llu-sized pages\n", 1430 1ULL << len, 1431 query.largest_available_block, 1432 1ULL << page_shift); 1433 1434 len = order_base_2(query.largest_available_block << page_shift); 1435 win_name = DMA64_PROPNAME; 1436 } else { 1437 direct_mapping = !default_win_removed || 1438 (len == MAX_PHYSMEM_BITS) || 1439 (!pmem_present && (len == max_ram_len)); 1440 win_name = direct_mapping ? DIRECT64_PROPNAME : DMA64_PROPNAME; 1441 } 1442 1443 ret = create_ddw(dev, ddw_avail, &create, page_shift, len); 1444 if (ret != 0) 1445 goto out_failed; 1446 1447 dev_dbg(&dev->dev, "created tce table LIOBN 0x%x for %pOF\n", 1448 create.liobn, dn); 1449 1450 win_addr = ((u64)create.addr_hi << 32) | create.addr_lo; 1451 win64 = ddw_property_create(win_name, create.liobn, win_addr, page_shift, len); 1452 1453 if (!win64) { 1454 dev_info(&dev->dev, 1455 "couldn't allocate property, property name, or value\n"); 1456 goto out_remove_win; 1457 } 1458 1459 ret = of_add_property(pdn, win64); 1460 if (ret) { 1461 dev_err(&dev->dev, "unable to add DMA window property for %pOF: %d", 1462 pdn, ret); 1463 goto out_free_prop; 1464 } 1465 1466 window = ddw_list_new_entry(pdn, win64->value); 1467 if (!window) 1468 goto out_del_prop; 1469 1470 if (direct_mapping) { 1471 window->direct = true; 1472 1473 /* DDW maps the whole partition, so enable direct DMA mapping */ 1474 ret = walk_system_ram_range(0, memblock_end_of_DRAM() >> PAGE_SHIFT, 1475 win64->value, tce_setrange_multi_pSeriesLP_walk); 1476 if (ret) { 1477 dev_info(&dev->dev, "failed to map DMA window for %pOF: %d\n", 1478 dn, ret); 1479 1480 /* Make sure to clean DDW if any TCE was set*/ 1481 clean_dma_window(pdn, win64->value); 1482 goto out_del_list; 1483 } 1484 } else { 1485 struct iommu_table *newtbl; 1486 int i; 1487 unsigned long start = 0, end = 0; 1488 1489 window->direct = false; 1490 1491 for (i = 0; i < ARRAY_SIZE(pci->phb->mem_resources); i++) { 1492 const unsigned long mask = IORESOURCE_MEM_64 | IORESOURCE_MEM; 1493 1494 /* Look for MMIO32 */ 1495 if ((pci->phb->mem_resources[i].flags & mask) == IORESOURCE_MEM) { 1496 start = pci->phb->mem_resources[i].start; 1497 end = pci->phb->mem_resources[i].end; 1498 break; 1499 } 1500 } 1501 1502 /* New table for using DDW instead of the default DMA window */ 1503 newtbl = iommu_pseries_alloc_table(pci->phb->node); 1504 if (!newtbl) { 1505 dev_dbg(&dev->dev, "couldn't create new IOMMU table\n"); 1506 goto out_del_list; 1507 } 1508 1509 iommu_table_setparms_common(newtbl, pci->phb->bus->number, create.liobn, win_addr, 1510 1UL << len, page_shift, NULL, &iommu_table_lpar_multi_ops); 1511 iommu_init_table(newtbl, pci->phb->node, start, end); 1512 1513 pci->table_group->tables[1] = newtbl; 1514 1515 set_iommu_table_base(&dev->dev, newtbl); 1516 } 1517 1518 if (default_win_removed) { 1519 iommu_tce_table_put(pci->table_group->tables[0]); 1520 pci->table_group->tables[0] = NULL; 1521 1522 /* default_win is valid here because default_win_removed == true */ 1523 of_remove_property(pdn, default_win); 1524 dev_info(&dev->dev, "Removed default DMA window for %pOF\n", pdn); 1525 } 1526 1527 spin_lock(&dma_win_list_lock); 1528 list_add(&window->list, &dma_win_list); 1529 spin_unlock(&dma_win_list_lock); 1530 1531 dev->dev.archdata.dma_offset = win_addr; 1532 goto out_unlock; 1533 1534out_del_list: 1535 kfree(window); 1536 1537out_del_prop: 1538 of_remove_property(pdn, win64); 1539 1540out_free_prop: 1541 kfree(win64->name); 1542 kfree(win64->value); 1543 kfree(win64); 1544 1545out_remove_win: 1546 /* DDW is clean, so it's ok to call this directly. */ 1547 __remove_dma_window(pdn, ddw_avail, create.liobn); 1548 1549out_failed: 1550 if (default_win_removed) 1551 reset_dma_window(dev, pdn); 1552 1553 fpdn = kzalloc(sizeof(*fpdn), GFP_KERNEL); 1554 if (!fpdn) 1555 goto out_unlock; 1556 fpdn->pdn = pdn; 1557 list_add(&fpdn->list, &failed_ddw_pdn_list); 1558 1559out_unlock: 1560 mutex_unlock(&dma_win_init_mutex); 1561 1562 /* 1563 * If we have persistent memory and the window size is only as big 1564 * as RAM, then we failed to create a window to cover persistent 1565 * memory and need to set the DMA limit. 1566 */ 1567 if (pmem_present && direct_mapping && len == max_ram_len) 1568 dev->dev.bus_dma_limit = dev->dev.archdata.dma_offset + (1ULL << len); 1569 1570 return direct_mapping; 1571} 1572 1573static void pci_dma_dev_setup_pSeriesLP(struct pci_dev *dev) 1574{ 1575 struct device_node *pdn, *dn; 1576 struct iommu_table *tbl; 1577 struct pci_dn *pci; 1578 struct dynamic_dma_window_prop prop; 1579 1580 pr_debug("pci_dma_dev_setup_pSeriesLP: %s\n", pci_name(dev)); 1581 1582 /* dev setup for LPAR is a little tricky, since the device tree might 1583 * contain the dma-window properties per-device and not necessarily 1584 * for the bus. So we need to search upwards in the tree until we 1585 * either hit a dma-window property, OR find a parent with a table 1586 * already allocated. 1587 */ 1588 dn = pci_device_to_OF_node(dev); 1589 pr_debug(" node is %pOF\n", dn); 1590 1591 pdn = pci_dma_find(dn, &prop); 1592 if (!pdn || !PCI_DN(pdn)) { 1593 printk(KERN_WARNING "pci_dma_dev_setup_pSeriesLP: " 1594 "no DMA window found for pci dev=%s dn=%pOF\n", 1595 pci_name(dev), dn); 1596 return; 1597 } 1598 pr_debug(" parent is %pOF\n", pdn); 1599 1600 pci = PCI_DN(pdn); 1601 if (!pci->table_group) { 1602 pci->table_group = iommu_pseries_alloc_group(pci->phb->node); 1603 tbl = pci->table_group->tables[0]; 1604 1605 iommu_table_setparms_common(tbl, pci->phb->bus->number, 1606 be32_to_cpu(prop.liobn), 1607 be64_to_cpu(prop.dma_base), 1608 1ULL << be32_to_cpu(prop.window_shift), 1609 be32_to_cpu(prop.tce_shift), NULL, 1610 &iommu_table_lpar_multi_ops); 1611 1612 /* Only for normal boot with default window. Doesn't matter even 1613 * if we set these with DDW which is 64bit during kdump, since 1614 * these will not be used during kdump. 1615 */ 1616 pci->table_group->tce32_start = be64_to_cpu(prop.dma_base); 1617 pci->table_group->tce32_size = 1 << be32_to_cpu(prop.window_shift); 1618 1619 iommu_init_table(tbl, pci->phb->node, 0, 0); 1620 iommu_register_group(pci->table_group, 1621 pci_domain_nr(pci->phb->bus), 0); 1622 pr_debug(" created table: %p\n", pci->table_group); 1623 } else { 1624 pr_debug(" found DMA window, table: %p\n", pci->table_group); 1625 } 1626 1627 set_iommu_table_base(&dev->dev, pci->table_group->tables[0]); 1628 iommu_add_device(pci->table_group, &dev->dev); 1629} 1630 1631static bool iommu_bypass_supported_pSeriesLP(struct pci_dev *pdev, u64 dma_mask) 1632{ 1633 struct device_node *dn = pci_device_to_OF_node(pdev), *pdn; 1634 1635 /* only attempt to use a new window if 64-bit DMA is requested */ 1636 if (dma_mask < DMA_BIT_MASK(64)) 1637 return false; 1638 1639 dev_dbg(&pdev->dev, "node is %pOF\n", dn); 1640 1641 /* 1642 * the device tree might contain the dma-window properties 1643 * per-device and not necessarily for the bus. So we need to 1644 * search upwards in the tree until we either hit a dma-window 1645 * property, OR find a parent with a table already allocated. 1646 */ 1647 pdn = pci_dma_find(dn, NULL); 1648 if (pdn && PCI_DN(pdn)) 1649 return enable_ddw(pdev, pdn); 1650 1651 return false; 1652} 1653 1654static int iommu_mem_notifier(struct notifier_block *nb, unsigned long action, 1655 void *data) 1656{ 1657 struct dma_win *window; 1658 struct memory_notify *arg = data; 1659 int ret = 0; 1660 1661 switch (action) { 1662 case MEM_GOING_ONLINE: 1663 spin_lock(&dma_win_list_lock); 1664 list_for_each_entry(window, &dma_win_list, list) { 1665 if (window->direct) { 1666 ret |= tce_setrange_multi_pSeriesLP(arg->start_pfn, 1667 arg->nr_pages, window->prop); 1668 } 1669 /* XXX log error */ 1670 } 1671 spin_unlock(&dma_win_list_lock); 1672 break; 1673 case MEM_CANCEL_ONLINE: 1674 case MEM_OFFLINE: 1675 spin_lock(&dma_win_list_lock); 1676 list_for_each_entry(window, &dma_win_list, list) { 1677 if (window->direct) { 1678 ret |= tce_clearrange_multi_pSeriesLP(arg->start_pfn, 1679 arg->nr_pages, window->prop); 1680 } 1681 /* XXX log error */ 1682 } 1683 spin_unlock(&dma_win_list_lock); 1684 break; 1685 default: 1686 break; 1687 } 1688 if (ret && action != MEM_CANCEL_ONLINE) 1689 return NOTIFY_BAD; 1690 1691 return NOTIFY_OK; 1692} 1693 1694static struct notifier_block iommu_mem_nb = { 1695 .notifier_call = iommu_mem_notifier, 1696}; 1697 1698static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *data) 1699{ 1700 int err = NOTIFY_OK; 1701 struct of_reconfig_data *rd = data; 1702 struct device_node *np = rd->dn; 1703 struct pci_dn *pci = PCI_DN(np); 1704 struct dma_win *window; 1705 1706 switch (action) { 1707 case OF_RECONFIG_DETACH_NODE: 1708 /* 1709 * Removing the property will invoke the reconfig 1710 * notifier again, which causes dead-lock on the 1711 * read-write semaphore of the notifier chain. So 1712 * we have to remove the property when releasing 1713 * the device node. 1714 */ 1715 if (remove_ddw(np, false, DIRECT64_PROPNAME)) 1716 remove_ddw(np, false, DMA64_PROPNAME); 1717 1718 if (pci && pci->table_group) 1719 iommu_pseries_free_group(pci->table_group, 1720 np->full_name); 1721 1722 spin_lock(&dma_win_list_lock); 1723 list_for_each_entry(window, &dma_win_list, list) { 1724 if (window->device == np) { 1725 list_del(&window->list); 1726 kfree(window); 1727 break; 1728 } 1729 } 1730 spin_unlock(&dma_win_list_lock); 1731 break; 1732 default: 1733 err = NOTIFY_DONE; 1734 break; 1735 } 1736 return err; 1737} 1738 1739static struct notifier_block iommu_reconfig_nb = { 1740 .notifier_call = iommu_reconfig_notifier, 1741}; 1742 1743/* These are called very early. */ 1744void __init iommu_init_early_pSeries(void) 1745{ 1746 if (of_chosen && of_get_property(of_chosen, "linux,iommu-off", NULL)) 1747 return; 1748 1749 if (firmware_has_feature(FW_FEATURE_LPAR)) { 1750 pseries_pci_controller_ops.dma_bus_setup = pci_dma_bus_setup_pSeriesLP; 1751 pseries_pci_controller_ops.dma_dev_setup = pci_dma_dev_setup_pSeriesLP; 1752 if (!disable_ddw) 1753 pseries_pci_controller_ops.iommu_bypass_supported = 1754 iommu_bypass_supported_pSeriesLP; 1755 } else { 1756 pseries_pci_controller_ops.dma_bus_setup = pci_dma_bus_setup_pSeries; 1757 pseries_pci_controller_ops.dma_dev_setup = pci_dma_dev_setup_pSeries; 1758 } 1759 1760 1761 of_reconfig_notifier_register(&iommu_reconfig_nb); 1762 register_memory_notifier(&iommu_mem_nb); 1763 1764 set_pci_dma_ops(&dma_iommu_ops); 1765} 1766 1767static int __init disable_multitce(char *str) 1768{ 1769 if (strcmp(str, "off") == 0 && 1770 firmware_has_feature(FW_FEATURE_LPAR) && 1771 (firmware_has_feature(FW_FEATURE_PUT_TCE_IND) || 1772 firmware_has_feature(FW_FEATURE_STUFF_TCE))) { 1773 printk(KERN_INFO "Disabling MULTITCE firmware feature\n"); 1774 powerpc_firmware_features &= 1775 ~(FW_FEATURE_PUT_TCE_IND | FW_FEATURE_STUFF_TCE); 1776 } 1777 return 1; 1778} 1779 1780__setup("multitce=", disable_multitce); 1781 1782#ifdef CONFIG_SPAPR_TCE_IOMMU 1783struct iommu_group *pSeries_pci_device_group(struct pci_controller *hose, 1784 struct pci_dev *pdev) 1785{ 1786 struct device_node *pdn, *dn = pdev->dev.of_node; 1787 struct iommu_group *grp; 1788 struct pci_dn *pci; 1789 1790 pdn = pci_dma_find(dn, NULL); 1791 if (!pdn || !PCI_DN(pdn)) 1792 return ERR_PTR(-ENODEV); 1793 1794 pci = PCI_DN(pdn); 1795 if (!pci->table_group) 1796 return ERR_PTR(-ENODEV); 1797 1798 grp = pci->table_group->group; 1799 if (!grp) 1800 return ERR_PTR(-ENODEV); 1801 1802 return iommu_group_ref_get(grp); 1803} 1804#endif 1805