1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Contains common pci routines for ALL ppc platform 4 * (based on pci_32.c and pci_64.c) 5 * 6 * Port for PPC64 David Engebretsen, IBM Corp. 7 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands. 8 * 9 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM 10 * Rework, based on alpha PCI code. 11 * 12 * Common pmac/prep/chrp pci routines. -- Cort 13 */ 14 15#include <linux/kernel.h> 16#include <linux/pci.h> 17#include <linux/string.h> 18#include <linux/init.h> 19#include <linux/delay.h> 20#include <linux/export.h> 21#include <linux/of_address.h> 22#include <linux/of_pci.h> 23#include <linux/mm.h> 24#include <linux/shmem_fs.h> 25#include <linux/list.h> 26#include <linux/syscalls.h> 27#include <linux/irq.h> 28#include <linux/vmalloc.h> 29#include <linux/slab.h> 30#include <linux/vgaarb.h> 31#include <linux/numa.h> 32#include <linux/msi.h> 33#include <linux/irqdomain.h> 34 35#include <asm/processor.h> 36#include <asm/io.h> 37#include <asm/pci-bridge.h> 38#include <asm/byteorder.h> 39#include <asm/machdep.h> 40#include <asm/ppc-pci.h> 41#include <asm/eeh.h> 42#include <asm/setup.h> 43 44#include "../../../drivers/pci/pci.h" 45 46/* hose_spinlock protects accesses to the phb_bitmap. */ 47static DEFINE_SPINLOCK(hose_spinlock); 48LIST_HEAD(hose_list); 49 50/* For dynamic PHB numbering on get_phb_number(): max number of PHBs. */ 51#define MAX_PHBS 0x10000 52 53/* 54 * For dynamic PHB numbering: used/free PHBs tracking bitmap. 55 * Accesses to this bitmap should be protected by hose_spinlock. 56 */ 57static DECLARE_BITMAP(phb_bitmap, MAX_PHBS); 58 59/* ISA Memory physical address */ 60resource_size_t isa_mem_base; 61EXPORT_SYMBOL(isa_mem_base); 62 63 64static const struct dma_map_ops *pci_dma_ops; 65 66void __init set_pci_dma_ops(const struct dma_map_ops *dma_ops) 67{ 68 pci_dma_ops = dma_ops; 69} 70 71static int get_phb_number(struct device_node *dn) 72{ 73 int ret, phb_id = -1; 74 u64 prop; 75 76 /* 77 * Try fixed PHB numbering first, by checking archs and reading 78 * the respective device-tree properties. Firstly, try reading 79 * standard "linux,pci-domain", then try reading "ibm,opal-phbid" 80 * (only present in powernv OPAL environment), then try device-tree 81 * alias and as the last try to use lower bits of "reg" property. 82 */ 83 ret = of_get_pci_domain_nr(dn); 84 if (ret >= 0) { 85 prop = ret; 86 ret = 0; 87 } 88 if (ret) 89 ret = of_property_read_u64(dn, "ibm,opal-phbid", &prop); 90 91 if (ret) { 92 ret = of_alias_get_id(dn, "pci"); 93 if (ret >= 0) { 94 prop = ret; 95 ret = 0; 96 } 97 } 98 if (ret) { 99 u32 prop_32; 100 ret = of_property_read_u32_index(dn, "reg", 1, &prop_32); 101 prop = prop_32; 102 } 103 104 if (!ret) 105 phb_id = (int)(prop & (MAX_PHBS - 1)); 106 107 spin_lock(&hose_spinlock); 108 109 /* We need to be sure to not use the same PHB number twice. */ 110 if ((phb_id >= 0) && !test_and_set_bit(phb_id, phb_bitmap)) 111 goto out_unlock; 112 113 /* If everything fails then fallback to dynamic PHB numbering. */ 114 phb_id = find_first_zero_bit(phb_bitmap, MAX_PHBS); 115 BUG_ON(phb_id >= MAX_PHBS); 116 set_bit(phb_id, phb_bitmap); 117 118out_unlock: 119 spin_unlock(&hose_spinlock); 120 121 return phb_id; 122} 123 124struct pci_controller *pcibios_alloc_controller(struct device_node *dev) 125{ 126 struct pci_controller *phb; 127 128 phb = kzalloc(sizeof(struct pci_controller), GFP_KERNEL); 129 if (phb == NULL) 130 return NULL; 131 132 phb->global_number = get_phb_number(dev); 133 134 spin_lock(&hose_spinlock); 135 list_add_tail(&phb->list_node, &hose_list); 136 spin_unlock(&hose_spinlock); 137 138 phb->dn = of_node_get(dev); 139 phb->is_dynamic = slab_is_available(); 140#ifdef CONFIG_PPC64 141 if (dev) { 142 int nid = of_node_to_nid(dev); 143 144 if (nid < 0 || !node_online(nid)) 145 nid = NUMA_NO_NODE; 146 147 PHB_SET_NODE(phb, nid); 148 } 149#endif 150 return phb; 151} 152EXPORT_SYMBOL_GPL(pcibios_alloc_controller); 153 154void pcibios_free_controller(struct pci_controller *phb) 155{ 156 spin_lock(&hose_spinlock); 157 158 /* Clear bit of phb_bitmap to allow reuse of this PHB number. */ 159 if (phb->global_number < MAX_PHBS) 160 clear_bit(phb->global_number, phb_bitmap); 161 of_node_put(phb->dn); 162 list_del(&phb->list_node); 163 spin_unlock(&hose_spinlock); 164 165 if (phb->is_dynamic) 166 kfree(phb); 167} 168EXPORT_SYMBOL_GPL(pcibios_free_controller); 169 170/* 171 * This function is used to call pcibios_free_controller() 172 * in a deferred manner: a callback from the PCI subsystem. 173 * 174 * _*DO NOT*_ call pcibios_free_controller() explicitly if 175 * this is used (or it may access an invalid *phb pointer). 176 * 177 * The callback occurs when all references to the root bus 178 * are dropped (e.g., child buses/devices and their users). 179 * 180 * It's called as .release_fn() of 'struct pci_host_bridge' 181 * which is associated with the 'struct pci_controller.bus' 182 * (root bus) - it expects .release_data to hold a pointer 183 * to 'struct pci_controller'. 184 * 185 * In order to use it, register .release_fn()/release_data 186 * like this: 187 * 188 * pci_set_host_bridge_release(bridge, 189 * pcibios_free_controller_deferred 190 * (void *) phb); 191 * 192 * e.g. in the pcibios_root_bridge_prepare() callback from 193 * pci_create_root_bus(). 194 */ 195void pcibios_free_controller_deferred(struct pci_host_bridge *bridge) 196{ 197 struct pci_controller *phb = (struct pci_controller *) 198 bridge->release_data; 199 200 pr_debug("domain %d, dynamic %d\n", phb->global_number, phb->is_dynamic); 201 202 pcibios_free_controller(phb); 203} 204EXPORT_SYMBOL_GPL(pcibios_free_controller_deferred); 205 206/* 207 * The function is used to return the minimal alignment 208 * for memory or I/O windows of the associated P2P bridge. 209 * By default, 4KiB alignment for I/O windows and 1MiB for 210 * memory windows. 211 */ 212resource_size_t pcibios_window_alignment(struct pci_bus *bus, 213 unsigned long type) 214{ 215 struct pci_controller *phb = pci_bus_to_host(bus); 216 217 if (phb->controller_ops.window_alignment) 218 return phb->controller_ops.window_alignment(bus, type); 219 220 /* 221 * PCI core will figure out the default 222 * alignment: 4KiB for I/O and 1MiB for 223 * memory window. 224 */ 225 return 1; 226} 227 228void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type) 229{ 230 struct pci_controller *hose = pci_bus_to_host(bus); 231 232 if (hose->controller_ops.setup_bridge) 233 hose->controller_ops.setup_bridge(bus, type); 234} 235 236void pcibios_reset_secondary_bus(struct pci_dev *dev) 237{ 238 struct pci_controller *phb = pci_bus_to_host(dev->bus); 239 240 if (phb->controller_ops.reset_secondary_bus) { 241 phb->controller_ops.reset_secondary_bus(dev); 242 return; 243 } 244 245 pci_reset_secondary_bus(dev); 246} 247 248resource_size_t pcibios_default_alignment(void) 249{ 250 if (ppc_md.pcibios_default_alignment) 251 return ppc_md.pcibios_default_alignment(); 252 253 return 0; 254} 255 256#ifdef CONFIG_PCI_IOV 257resource_size_t pcibios_iov_resource_alignment(struct pci_dev *pdev, int resno) 258{ 259 if (ppc_md.pcibios_iov_resource_alignment) 260 return ppc_md.pcibios_iov_resource_alignment(pdev, resno); 261 262 return pci_iov_resource_size(pdev, resno); 263} 264 265int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) 266{ 267 if (ppc_md.pcibios_sriov_enable) 268 return ppc_md.pcibios_sriov_enable(pdev, num_vfs); 269 270 return 0; 271} 272 273int pcibios_sriov_disable(struct pci_dev *pdev) 274{ 275 if (ppc_md.pcibios_sriov_disable) 276 return ppc_md.pcibios_sriov_disable(pdev); 277 278 return 0; 279} 280 281#endif /* CONFIG_PCI_IOV */ 282 283static resource_size_t pcibios_io_size(const struct pci_controller *hose) 284{ 285#ifdef CONFIG_PPC64 286 return hose->pci_io_size; 287#else 288 return resource_size(&hose->io_resource); 289#endif 290} 291 292int pcibios_vaddr_is_ioport(void __iomem *address) 293{ 294 int ret = 0; 295 struct pci_controller *hose; 296 resource_size_t size; 297 298 spin_lock(&hose_spinlock); 299 list_for_each_entry(hose, &hose_list, list_node) { 300 size = pcibios_io_size(hose); 301 if (address >= hose->io_base_virt && 302 address < (hose->io_base_virt + size)) { 303 ret = 1; 304 break; 305 } 306 } 307 spin_unlock(&hose_spinlock); 308 return ret; 309} 310 311unsigned long pci_address_to_pio(phys_addr_t address) 312{ 313 struct pci_controller *hose; 314 resource_size_t size; 315 unsigned long ret = ~0; 316 317 spin_lock(&hose_spinlock); 318 list_for_each_entry(hose, &hose_list, list_node) { 319 size = pcibios_io_size(hose); 320 if (address >= hose->io_base_phys && 321 address < (hose->io_base_phys + size)) { 322 unsigned long base = 323 (unsigned long)hose->io_base_virt - _IO_BASE; 324 ret = base + (address - hose->io_base_phys); 325 break; 326 } 327 } 328 spin_unlock(&hose_spinlock); 329 330 return ret; 331} 332EXPORT_SYMBOL_GPL(pci_address_to_pio); 333 334/* 335 * Return the domain number for this bus. 336 */ 337int pci_domain_nr(struct pci_bus *bus) 338{ 339 struct pci_controller *hose = pci_bus_to_host(bus); 340 341 return hose->global_number; 342} 343EXPORT_SYMBOL(pci_domain_nr); 344 345/* This routine is meant to be used early during boot, when the 346 * PCI bus numbers have not yet been assigned, and you need to 347 * issue PCI config cycles to an OF device. 348 * It could also be used to "fix" RTAS config cycles if you want 349 * to set pci_assign_all_buses to 1 and still use RTAS for PCI 350 * config cycles. 351 */ 352struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node) 353{ 354 while(node) { 355 struct pci_controller *hose, *tmp; 356 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) 357 if (hose->dn == node) 358 return hose; 359 node = node->parent; 360 } 361 return NULL; 362} 363 364struct pci_controller *pci_find_controller_for_domain(int domain_nr) 365{ 366 struct pci_controller *hose; 367 368 list_for_each_entry(hose, &hose_list, list_node) 369 if (hose->global_number == domain_nr) 370 return hose; 371 372 return NULL; 373} 374 375struct pci_intx_virq { 376 int virq; 377 struct kref kref; 378 struct list_head list_node; 379}; 380 381static LIST_HEAD(intx_list); 382static DEFINE_MUTEX(intx_mutex); 383 384static void ppc_pci_intx_release(struct kref *kref) 385{ 386 struct pci_intx_virq *vi = container_of(kref, struct pci_intx_virq, kref); 387 388 list_del(&vi->list_node); 389 irq_dispose_mapping(vi->virq); 390 kfree(vi); 391} 392 393static int ppc_pci_unmap_irq_line(struct notifier_block *nb, 394 unsigned long action, void *data) 395{ 396 struct pci_dev *pdev = to_pci_dev(data); 397 398 if (action == BUS_NOTIFY_DEL_DEVICE) { 399 struct pci_intx_virq *vi; 400 401 mutex_lock(&intx_mutex); 402 list_for_each_entry(vi, &intx_list, list_node) { 403 if (vi->virq == pdev->irq) { 404 kref_put(&vi->kref, ppc_pci_intx_release); 405 break; 406 } 407 } 408 mutex_unlock(&intx_mutex); 409 } 410 411 return NOTIFY_DONE; 412} 413 414static struct notifier_block ppc_pci_unmap_irq_notifier = { 415 .notifier_call = ppc_pci_unmap_irq_line, 416}; 417 418static int ppc_pci_register_irq_notifier(void) 419{ 420 return bus_register_notifier(&pci_bus_type, &ppc_pci_unmap_irq_notifier); 421} 422arch_initcall(ppc_pci_register_irq_notifier); 423 424/* 425 * Reads the interrupt pin to determine if interrupt is use by card. 426 * If the interrupt is used, then gets the interrupt line from the 427 * openfirmware and sets it in the pci_dev and pci_config line. 428 */ 429static int pci_read_irq_line(struct pci_dev *pci_dev) 430{ 431 int virq; 432 struct pci_intx_virq *vi, *vitmp; 433 434 /* Preallocate vi as rewind is complex if this fails after mapping */ 435 vi = kzalloc(sizeof(struct pci_intx_virq), GFP_KERNEL); 436 if (!vi) 437 return -1; 438 439 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev)); 440 441 /* Try to get a mapping from the device-tree */ 442 virq = of_irq_parse_and_map_pci(pci_dev, 0, 0); 443 if (virq <= 0) { 444 u8 line, pin; 445 446 /* If that fails, lets fallback to what is in the config 447 * space and map that through the default controller. We 448 * also set the type to level low since that's what PCI 449 * interrupts are. If your platform does differently, then 450 * either provide a proper interrupt tree or don't use this 451 * function. 452 */ 453 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin)) 454 goto error_exit; 455 if (pin == 0) 456 goto error_exit; 457 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) || 458 line == 0xff || line == 0) { 459 goto error_exit; 460 } 461 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n", 462 line, pin); 463 464 virq = irq_create_mapping(NULL, line); 465 if (virq) 466 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); 467 } 468 469 if (!virq) { 470 pr_debug(" Failed to map !\n"); 471 goto error_exit; 472 } 473 474 pr_debug(" Mapped to linux irq %d\n", virq); 475 476 pci_dev->irq = virq; 477 478 mutex_lock(&intx_mutex); 479 list_for_each_entry(vitmp, &intx_list, list_node) { 480 if (vitmp->virq == virq) { 481 kref_get(&vitmp->kref); 482 kfree(vi); 483 vi = NULL; 484 break; 485 } 486 } 487 if (vi) { 488 vi->virq = virq; 489 kref_init(&vi->kref); 490 list_add_tail(&vi->list_node, &intx_list); 491 } 492 mutex_unlock(&intx_mutex); 493 494 return 0; 495error_exit: 496 kfree(vi); 497 return -1; 498} 499 500/* 501 * Platform support for /proc/bus/pci/X/Y mmap()s. 502 * -- paulus. 503 */ 504int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma) 505{ 506 struct pci_controller *hose = pci_bus_to_host(pdev->bus); 507 resource_size_t ioaddr = pci_resource_start(pdev, bar); 508 509 if (!hose) 510 return -EINVAL; 511 512 /* Convert to an offset within this PCI controller */ 513 ioaddr -= (unsigned long)hose->io_base_virt - _IO_BASE; 514 515 vma->vm_pgoff += (ioaddr + hose->io_base_phys) >> PAGE_SHIFT; 516 return 0; 517} 518 519/* 520 * This one is used by /dev/mem and video who have no clue about the 521 * PCI device, it tries to find the PCI device first and calls the 522 * above routine 523 */ 524pgprot_t pci_phys_mem_access_prot(unsigned long pfn, 525 unsigned long size, 526 pgprot_t prot) 527{ 528 struct pci_dev *pdev = NULL; 529 struct resource *found = NULL; 530 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT; 531 int i; 532 533 if (page_is_ram(pfn)) 534 return prot; 535 536 prot = pgprot_noncached(prot); 537 for_each_pci_dev(pdev) { 538 for (i = 0; i <= PCI_ROM_RESOURCE; i++) { 539 struct resource *rp = &pdev->resource[i]; 540 int flags = rp->flags; 541 542 /* Active and same type? */ 543 if ((flags & IORESOURCE_MEM) == 0) 544 continue; 545 /* In the range of this resource? */ 546 if (offset < (rp->start & PAGE_MASK) || 547 offset > rp->end) 548 continue; 549 found = rp; 550 break; 551 } 552 if (found) 553 break; 554 } 555 if (found) { 556 if (found->flags & IORESOURCE_PREFETCH) 557 prot = pgprot_noncached_wc(prot); 558 pci_dev_put(pdev); 559 } 560 561 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n", 562 (unsigned long long)offset, pgprot_val(prot)); 563 564 return prot; 565} 566 567/* This provides legacy IO read access on a bus */ 568int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size) 569{ 570 unsigned long offset; 571 struct pci_controller *hose = pci_bus_to_host(bus); 572 struct resource *rp = &hose->io_resource; 573 void __iomem *addr; 574 575 /* Check if port can be supported by that bus. We only check 576 * the ranges of the PHB though, not the bus itself as the rules 577 * for forwarding legacy cycles down bridges are not our problem 578 * here. So if the host bridge supports it, we do it. 579 */ 580 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 581 offset += port; 582 583 if (!(rp->flags & IORESOURCE_IO)) 584 return -ENXIO; 585 if (offset < rp->start || (offset + size) > rp->end) 586 return -ENXIO; 587 addr = hose->io_base_virt + port; 588 589 switch(size) { 590 case 1: 591 *((u8 *)val) = in_8(addr); 592 return 1; 593 case 2: 594 if (port & 1) 595 return -EINVAL; 596 *((u16 *)val) = in_le16(addr); 597 return 2; 598 case 4: 599 if (port & 3) 600 return -EINVAL; 601 *((u32 *)val) = in_le32(addr); 602 return 4; 603 } 604 return -EINVAL; 605} 606 607/* This provides legacy IO write access on a bus */ 608int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size) 609{ 610 unsigned long offset; 611 struct pci_controller *hose = pci_bus_to_host(bus); 612 struct resource *rp = &hose->io_resource; 613 void __iomem *addr; 614 615 /* Check if port can be supported by that bus. We only check 616 * the ranges of the PHB though, not the bus itself as the rules 617 * for forwarding legacy cycles down bridges are not our problem 618 * here. So if the host bridge supports it, we do it. 619 */ 620 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 621 offset += port; 622 623 if (!(rp->flags & IORESOURCE_IO)) 624 return -ENXIO; 625 if (offset < rp->start || (offset + size) > rp->end) 626 return -ENXIO; 627 addr = hose->io_base_virt + port; 628 629 /* WARNING: The generic code is idiotic. It gets passed a pointer 630 * to what can be a 1, 2 or 4 byte quantity and always reads that 631 * as a u32, which means that we have to correct the location of 632 * the data read within those 32 bits for size 1 and 2 633 */ 634 switch(size) { 635 case 1: 636 out_8(addr, val >> 24); 637 return 1; 638 case 2: 639 if (port & 1) 640 return -EINVAL; 641 out_le16(addr, val >> 16); 642 return 2; 643 case 4: 644 if (port & 3) 645 return -EINVAL; 646 out_le32(addr, val); 647 return 4; 648 } 649 return -EINVAL; 650} 651 652/* This provides legacy IO or memory mmap access on a bus */ 653int pci_mmap_legacy_page_range(struct pci_bus *bus, 654 struct vm_area_struct *vma, 655 enum pci_mmap_state mmap_state) 656{ 657 struct pci_controller *hose = pci_bus_to_host(bus); 658 resource_size_t offset = 659 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; 660 resource_size_t size = vma->vm_end - vma->vm_start; 661 struct resource *rp; 662 663 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n", 664 pci_domain_nr(bus), bus->number, 665 mmap_state == pci_mmap_mem ? "MEM" : "IO", 666 (unsigned long long)offset, 667 (unsigned long long)(offset + size - 1)); 668 669 if (mmap_state == pci_mmap_mem) { 670 /* Hack alert ! 671 * 672 * Because X is lame and can fail starting if it gets an error trying 673 * to mmap legacy_mem (instead of just moving on without legacy memory 674 * access) we fake it here by giving it anonymous memory, effectively 675 * behaving just like /dev/zero 676 */ 677 if ((offset + size) > hose->isa_mem_size) { 678 printk(KERN_DEBUG 679 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n", 680 current->comm, current->pid, pci_domain_nr(bus), bus->number); 681 if (vma->vm_flags & VM_SHARED) 682 return shmem_zero_setup(vma); 683 return 0; 684 } 685 offset += hose->isa_mem_phys; 686 } else { 687 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; 688 unsigned long roffset = offset + io_offset; 689 rp = &hose->io_resource; 690 if (!(rp->flags & IORESOURCE_IO)) 691 return -ENXIO; 692 if (roffset < rp->start || (roffset + size) > rp->end) 693 return -ENXIO; 694 offset += hose->io_base_phys; 695 } 696 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset); 697 698 vma->vm_pgoff = offset >> PAGE_SHIFT; 699 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 700 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 701 vma->vm_end - vma->vm_start, 702 vma->vm_page_prot); 703} 704 705void pci_resource_to_user(const struct pci_dev *dev, int bar, 706 const struct resource *rsrc, 707 resource_size_t *start, resource_size_t *end) 708{ 709 struct pci_bus_region region; 710 711 if (rsrc->flags & IORESOURCE_IO) { 712 pcibios_resource_to_bus(dev->bus, ®ion, 713 (struct resource *) rsrc); 714 *start = region.start; 715 *end = region.end; 716 return; 717 } 718 719 /* We pass a CPU physical address to userland for MMIO instead of a 720 * BAR value because X is lame and expects to be able to use that 721 * to pass to /dev/mem! 722 * 723 * That means we may have 64-bit values where some apps only expect 724 * 32 (like X itself since it thinks only Sparc has 64-bit MMIO). 725 */ 726 *start = rsrc->start; 727 *end = rsrc->end; 728} 729 730/** 731 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree 732 * @hose: newly allocated pci_controller to be setup 733 * @dev: device node of the host bridge 734 * @primary: set if primary bus (32 bits only, soon to be deprecated) 735 * 736 * This function will parse the "ranges" property of a PCI host bridge device 737 * node and setup the resource mapping of a pci controller based on its 738 * content. 739 * 740 * Life would be boring if it wasn't for a few issues that we have to deal 741 * with here: 742 * 743 * - We can only cope with one IO space range and up to 3 Memory space 744 * ranges. However, some machines (thanks Apple !) tend to split their 745 * space into lots of small contiguous ranges. So we have to coalesce. 746 * 747 * - Some busses have IO space not starting at 0, which causes trouble with 748 * the way we do our IO resource renumbering. The code somewhat deals with 749 * it for 64 bits but I would expect problems on 32 bits. 750 * 751 * - Some 32 bits platforms such as 4xx can have physical space larger than 752 * 32 bits so we need to use 64 bits values for the parsing 753 */ 754void pci_process_bridge_OF_ranges(struct pci_controller *hose, 755 struct device_node *dev, int primary) 756{ 757 int memno = 0; 758 struct resource *res; 759 struct of_pci_range range; 760 struct of_pci_range_parser parser; 761 762 printk(KERN_INFO "PCI host bridge %pOF %s ranges:\n", 763 dev, primary ? "(primary)" : ""); 764 765 /* Check for ranges property */ 766 if (of_pci_range_parser_init(&parser, dev)) 767 return; 768 769 /* Parse it */ 770 for_each_of_pci_range(&parser, &range) { 771 /* If we failed translation or got a zero-sized region 772 * (some FW try to feed us with non sensical zero sized regions 773 * such as power3 which look like some kind of attempt at exposing 774 * the VGA memory hole) 775 */ 776 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0) 777 continue; 778 779 /* Act based on address space type */ 780 res = NULL; 781 switch (range.flags & IORESOURCE_TYPE_BITS) { 782 case IORESOURCE_IO: 783 printk(KERN_INFO 784 " IO 0x%016llx..0x%016llx -> 0x%016llx\n", 785 range.cpu_addr, range.cpu_addr + range.size - 1, 786 range.pci_addr); 787 788 /* We support only one IO range */ 789 if (hose->pci_io_size) { 790 printk(KERN_INFO 791 " \\--> Skipped (too many) !\n"); 792 continue; 793 } 794#ifdef CONFIG_PPC32 795 /* On 32 bits, limit I/O space to 16MB */ 796 if (range.size > 0x01000000) 797 range.size = 0x01000000; 798 799 /* 32 bits needs to map IOs here */ 800 hose->io_base_virt = ioremap(range.cpu_addr, 801 range.size); 802 803 /* Expect trouble if pci_addr is not 0 */ 804 if (primary) 805 isa_io_base = 806 (unsigned long)hose->io_base_virt; 807#endif /* CONFIG_PPC32 */ 808 /* pci_io_size and io_base_phys always represent IO 809 * space starting at 0 so we factor in pci_addr 810 */ 811 hose->pci_io_size = range.pci_addr + range.size; 812 hose->io_base_phys = range.cpu_addr - range.pci_addr; 813 814 /* Build resource */ 815 res = &hose->io_resource; 816 range.cpu_addr = range.pci_addr; 817 break; 818 case IORESOURCE_MEM: 819 printk(KERN_INFO 820 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n", 821 range.cpu_addr, range.cpu_addr + range.size - 1, 822 range.pci_addr, 823 (range.flags & IORESOURCE_PREFETCH) ? 824 "Prefetch" : ""); 825 826 /* We support only 3 memory ranges */ 827 if (memno >= 3) { 828 printk(KERN_INFO 829 " \\--> Skipped (too many) !\n"); 830 continue; 831 } 832 /* Handles ISA memory hole space here */ 833 if (range.pci_addr == 0) { 834 if (primary || isa_mem_base == 0) 835 isa_mem_base = range.cpu_addr; 836 hose->isa_mem_phys = range.cpu_addr; 837 hose->isa_mem_size = range.size; 838 } 839 840 /* Build resource */ 841 hose->mem_offset[memno] = range.cpu_addr - 842 range.pci_addr; 843 res = &hose->mem_resources[memno++]; 844 break; 845 } 846 if (res != NULL) { 847 res->name = dev->full_name; 848 res->flags = range.flags; 849 res->start = range.cpu_addr; 850 res->end = range.cpu_addr + range.size - 1; 851 res->parent = res->child = res->sibling = NULL; 852 } 853 } 854} 855 856/* Decide whether to display the domain number in /proc */ 857int pci_proc_domain(struct pci_bus *bus) 858{ 859 struct pci_controller *hose = pci_bus_to_host(bus); 860 861 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS)) 862 return 0; 863 if (pci_has_flag(PCI_COMPAT_DOMAIN_0)) 864 return hose->global_number != 0; 865 return 1; 866} 867 868int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) 869{ 870 if (ppc_md.pcibios_root_bridge_prepare) 871 return ppc_md.pcibios_root_bridge_prepare(bridge); 872 873 return 0; 874} 875 876/* This header fixup will do the resource fixup for all devices as they are 877 * probed, but not for bridge ranges 878 */ 879static void pcibios_fixup_resources(struct pci_dev *dev) 880{ 881 struct pci_controller *hose = pci_bus_to_host(dev->bus); 882 struct resource *res; 883 int i; 884 885 if (!hose) { 886 printk(KERN_ERR "No host bridge for PCI dev %s !\n", 887 pci_name(dev)); 888 return; 889 } 890 891 if (dev->is_virtfn) 892 return; 893 894 pci_dev_for_each_resource(dev, res, i) { 895 struct pci_bus_region reg; 896 897 if (!res->flags) 898 continue; 899 900 /* If we're going to re-assign everything, we mark all resources 901 * as unset (and 0-base them). In addition, we mark BARs starting 902 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set 903 * since in that case, we don't want to re-assign anything 904 */ 905 pcibios_resource_to_bus(dev->bus, ®, res); 906 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) || 907 (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) { 908 /* Only print message if not re-assigning */ 909 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) 910 pr_debug("PCI:%s Resource %d %pR is unassigned\n", 911 pci_name(dev), i, res); 912 res->end -= res->start; 913 res->start = 0; 914 res->flags |= IORESOURCE_UNSET; 915 continue; 916 } 917 918 pr_debug("PCI:%s Resource %d %pR\n", pci_name(dev), i, res); 919 } 920 921 /* Call machine specific resource fixup */ 922 if (ppc_md.pcibios_fixup_resources) 923 ppc_md.pcibios_fixup_resources(dev); 924} 925DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources); 926 927/* This function tries to figure out if a bridge resource has been initialized 928 * by the firmware or not. It doesn't have to be absolutely bullet proof, but 929 * things go more smoothly when it gets it right. It should covers cases such 930 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges 931 */ 932static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus, 933 struct resource *res) 934{ 935 struct pci_controller *hose = pci_bus_to_host(bus); 936 struct pci_dev *dev = bus->self; 937 resource_size_t offset; 938 struct pci_bus_region region; 939 u16 command; 940 int i; 941 942 /* We don't do anything if PCI_PROBE_ONLY is set */ 943 if (pci_has_flag(PCI_PROBE_ONLY)) 944 return 0; 945 946 /* Job is a bit different between memory and IO */ 947 if (res->flags & IORESOURCE_MEM) { 948 pcibios_resource_to_bus(dev->bus, ®ion, res); 949 950 /* If the BAR is non-0 then it's probably been initialized */ 951 if (region.start != 0) 952 return 0; 953 954 /* The BAR is 0, let's check if memory decoding is enabled on 955 * the bridge. If not, we consider it unassigned 956 */ 957 pci_read_config_word(dev, PCI_COMMAND, &command); 958 if ((command & PCI_COMMAND_MEMORY) == 0) 959 return 1; 960 961 /* Memory decoding is enabled and the BAR is 0. If any of the bridge 962 * resources covers that starting address (0 then it's good enough for 963 * us for memory space) 964 */ 965 for (i = 0; i < 3; i++) { 966 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) && 967 hose->mem_resources[i].start == hose->mem_offset[i]) 968 return 0; 969 } 970 971 /* Well, it starts at 0 and we know it will collide so we may as 972 * well consider it as unassigned. That covers the Apple case. 973 */ 974 return 1; 975 } else { 976 /* If the BAR is non-0, then we consider it assigned */ 977 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 978 if (((res->start - offset) & 0xfffffffful) != 0) 979 return 0; 980 981 /* Here, we are a bit different than memory as typically IO space 982 * starting at low addresses -is- valid. What we do instead if that 983 * we consider as unassigned anything that doesn't have IO enabled 984 * in the PCI command register, and that's it. 985 */ 986 pci_read_config_word(dev, PCI_COMMAND, &command); 987 if (command & PCI_COMMAND_IO) 988 return 0; 989 990 /* It's starting at 0 and IO is disabled in the bridge, consider 991 * it unassigned 992 */ 993 return 1; 994 } 995} 996 997/* Fixup resources of a PCI<->PCI bridge */ 998static void pcibios_fixup_bridge(struct pci_bus *bus) 999{ 1000 struct resource *res; 1001 int i; 1002 1003 struct pci_dev *dev = bus->self; 1004 1005 pci_bus_for_each_resource(bus, res, i) { 1006 if (!res || !res->flags) 1007 continue; 1008 if (i >= 3 && bus->self->transparent) 1009 continue; 1010 1011 /* If we're going to reassign everything, we can 1012 * shrink the P2P resource to have size as being 1013 * of 0 in order to save space. 1014 */ 1015 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) { 1016 res->flags |= IORESOURCE_UNSET; 1017 res->start = 0; 1018 res->end = -1; 1019 continue; 1020 } 1021 1022 pr_debug("PCI:%s Bus rsrc %d %pR\n", pci_name(dev), i, res); 1023 1024 /* Try to detect uninitialized P2P bridge resources, 1025 * and clear them out so they get re-assigned later 1026 */ 1027 if (pcibios_uninitialized_bridge_resource(bus, res)) { 1028 res->flags = 0; 1029 pr_debug("PCI:%s (unassigned)\n", pci_name(dev)); 1030 } 1031 } 1032} 1033 1034void pcibios_setup_bus_self(struct pci_bus *bus) 1035{ 1036 struct pci_controller *phb; 1037 1038 /* Fix up the bus resources for P2P bridges */ 1039 if (bus->self != NULL) 1040 pcibios_fixup_bridge(bus); 1041 1042 /* Platform specific bus fixups. This is currently only used 1043 * by fsl_pci and I'm hoping to get rid of it at some point 1044 */ 1045 if (ppc_md.pcibios_fixup_bus) 1046 ppc_md.pcibios_fixup_bus(bus); 1047 1048 /* Setup bus DMA mappings */ 1049 phb = pci_bus_to_host(bus); 1050 if (phb->controller_ops.dma_bus_setup) 1051 phb->controller_ops.dma_bus_setup(bus); 1052} 1053 1054void pcibios_bus_add_device(struct pci_dev *dev) 1055{ 1056 struct pci_controller *phb; 1057 /* Fixup NUMA node as it may not be setup yet by the generic 1058 * code and is needed by the DMA init 1059 */ 1060 set_dev_node(&dev->dev, pcibus_to_node(dev->bus)); 1061 1062 /* Hook up default DMA ops */ 1063 set_dma_ops(&dev->dev, pci_dma_ops); 1064 dev->dev.archdata.dma_offset = PCI_DRAM_OFFSET; 1065 1066 /* Additional platform DMA/iommu setup */ 1067 phb = pci_bus_to_host(dev->bus); 1068 if (phb->controller_ops.dma_dev_setup) 1069 phb->controller_ops.dma_dev_setup(dev); 1070 1071 /* Read default IRQs and fixup if necessary */ 1072 pci_read_irq_line(dev); 1073 if (ppc_md.pci_irq_fixup) 1074 ppc_md.pci_irq_fixup(dev); 1075 1076 if (ppc_md.pcibios_bus_add_device) 1077 ppc_md.pcibios_bus_add_device(dev); 1078} 1079 1080int pcibios_device_add(struct pci_dev *dev) 1081{ 1082 struct irq_domain *d; 1083 1084#ifdef CONFIG_PCI_IOV 1085 if (ppc_md.pcibios_fixup_sriov) 1086 ppc_md.pcibios_fixup_sriov(dev); 1087#endif /* CONFIG_PCI_IOV */ 1088 1089 d = dev_get_msi_domain(&dev->bus->dev); 1090 if (d) 1091 dev_set_msi_domain(&dev->dev, d); 1092 return 0; 1093} 1094 1095void pcibios_set_master(struct pci_dev *dev) 1096{ 1097 /* No special bus mastering setup handling */ 1098} 1099 1100void pcibios_fixup_bus(struct pci_bus *bus) 1101{ 1102 /* When called from the generic PCI probe, read PCI<->PCI bridge 1103 * bases. This is -not- called when generating the PCI tree from 1104 * the OF device-tree. 1105 */ 1106 pci_read_bridge_bases(bus); 1107 1108 /* Now fixup the bus */ 1109 pcibios_setup_bus_self(bus); 1110} 1111EXPORT_SYMBOL(pcibios_fixup_bus); 1112 1113static int skip_isa_ioresource_align(struct pci_dev *dev) 1114{ 1115 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) && 1116 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA)) 1117 return 1; 1118 return 0; 1119} 1120 1121/* 1122 * We need to avoid collisions with `mirrored' VGA ports 1123 * and other strange ISA hardware, so we always want the 1124 * addresses to be allocated in the 0x000-0x0ff region 1125 * modulo 0x400. 1126 * 1127 * Why? Because some silly external IO cards only decode 1128 * the low 10 bits of the IO address. The 0x00-0xff region 1129 * is reserved for motherboard devices that decode all 16 1130 * bits, so it's ok to allocate at, say, 0x2800-0x28ff, 1131 * but we want to try to avoid allocating at 0x2900-0x2bff 1132 * which might have be mirrored at 0x0100-0x03ff.. 1133 */ 1134resource_size_t pcibios_align_resource(void *data, const struct resource *res, 1135 resource_size_t size, resource_size_t align) 1136{ 1137 struct pci_dev *dev = data; 1138 resource_size_t start = res->start; 1139 1140 if (res->flags & IORESOURCE_IO) { 1141 if (skip_isa_ioresource_align(dev)) 1142 return start; 1143 if (start & 0x300) 1144 start = (start + 0x3ff) & ~0x3ff; 1145 } 1146 1147 return start; 1148} 1149EXPORT_SYMBOL(pcibios_align_resource); 1150 1151/* 1152 * Reparent resource children of pr that conflict with res 1153 * under res, and make res replace those children. 1154 */ 1155static int reparent_resources(struct resource *parent, 1156 struct resource *res) 1157{ 1158 struct resource *p, **pp; 1159 struct resource **firstpp = NULL; 1160 1161 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { 1162 if (p->end < res->start) 1163 continue; 1164 if (res->end < p->start) 1165 break; 1166 if (p->start < res->start || p->end > res->end) 1167 return -1; /* not completely contained */ 1168 if (firstpp == NULL) 1169 firstpp = pp; 1170 } 1171 if (firstpp == NULL) 1172 return -1; /* didn't find any conflicting entries? */ 1173 res->parent = parent; 1174 res->child = *firstpp; 1175 res->sibling = *pp; 1176 *firstpp = res; 1177 *pp = NULL; 1178 for (p = res->child; p != NULL; p = p->sibling) { 1179 p->parent = res; 1180 pr_debug("PCI: Reparented %s %pR under %s\n", 1181 p->name, p, res->name); 1182 } 1183 return 0; 1184} 1185 1186/* 1187 * Handle resources of PCI devices. If the world were perfect, we could 1188 * just allocate all the resource regions and do nothing more. It isn't. 1189 * On the other hand, we cannot just re-allocate all devices, as it would 1190 * require us to know lots of host bridge internals. So we attempt to 1191 * keep as much of the original configuration as possible, but tweak it 1192 * when it's found to be wrong. 1193 * 1194 * Known BIOS problems we have to work around: 1195 * - I/O or memory regions not configured 1196 * - regions configured, but not enabled in the command register 1197 * - bogus I/O addresses above 64K used 1198 * - expansion ROMs left enabled (this may sound harmless, but given 1199 * the fact the PCI specs explicitly allow address decoders to be 1200 * shared between expansion ROMs and other resource regions, it's 1201 * at least dangerous) 1202 * 1203 * Our solution: 1204 * (1) Allocate resources for all buses behind PCI-to-PCI bridges. 1205 * This gives us fixed barriers on where we can allocate. 1206 * (2) Allocate resources for all enabled devices. If there is 1207 * a collision, just mark the resource as unallocated. Also 1208 * disable expansion ROMs during this step. 1209 * (3) Try to allocate resources for disabled devices. If the 1210 * resources were assigned correctly, everything goes well, 1211 * if they weren't, they won't disturb allocation of other 1212 * resources. 1213 * (4) Assign new addresses to resources which were either 1214 * not configured at all or misconfigured. If explicitly 1215 * requested by the user, configure expansion ROM address 1216 * as well. 1217 */ 1218 1219static void pcibios_allocate_bus_resources(struct pci_bus *bus) 1220{ 1221 struct pci_bus *b; 1222 int i; 1223 struct resource *res, *pr; 1224 1225 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n", 1226 pci_domain_nr(bus), bus->number); 1227 1228 pci_bus_for_each_resource(bus, res, i) { 1229 if (!res || !res->flags || res->start > res->end || res->parent) 1230 continue; 1231 1232 /* If the resource was left unset at this point, we clear it */ 1233 if (res->flags & IORESOURCE_UNSET) 1234 goto clear_resource; 1235 1236 if (bus->parent == NULL) 1237 pr = (res->flags & IORESOURCE_IO) ? 1238 &ioport_resource : &iomem_resource; 1239 else { 1240 pr = pci_find_parent_resource(bus->self, res); 1241 if (pr == res) { 1242 /* this happens when the generic PCI 1243 * code (wrongly) decides that this 1244 * bridge is transparent -- paulus 1245 */ 1246 continue; 1247 } 1248 } 1249 1250 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %pR, parent %p (%s)\n", 1251 bus->self ? pci_name(bus->self) : "PHB", bus->number, 1252 i, res, pr, (pr && pr->name) ? pr->name : "nil"); 1253 1254 if (pr && !(pr->flags & IORESOURCE_UNSET)) { 1255 struct pci_dev *dev = bus->self; 1256 1257 if (request_resource(pr, res) == 0) 1258 continue; 1259 /* 1260 * Must be a conflict with an existing entry. 1261 * Move that entry (or entries) under the 1262 * bridge resource and try again. 1263 */ 1264 if (reparent_resources(pr, res) == 0) 1265 continue; 1266 1267 if (dev && i < PCI_BRIDGE_RESOURCE_NUM && 1268 pci_claim_bridge_resource(dev, 1269 i + PCI_BRIDGE_RESOURCES) == 0) 1270 continue; 1271 } 1272 pr_warn("PCI: Cannot allocate resource region %d of PCI bridge %d, will remap\n", 1273 i, bus->number); 1274 clear_resource: 1275 /* The resource might be figured out when doing 1276 * reassignment based on the resources required 1277 * by the downstream PCI devices. Here we set 1278 * the size of the resource to be 0 in order to 1279 * save more space. 1280 */ 1281 res->start = 0; 1282 res->end = -1; 1283 res->flags = 0; 1284 } 1285 1286 list_for_each_entry(b, &bus->children, node) 1287 pcibios_allocate_bus_resources(b); 1288} 1289 1290static inline void alloc_resource(struct pci_dev *dev, int idx) 1291{ 1292 struct resource *pr, *r = &dev->resource[idx]; 1293 1294 pr_debug("PCI: Allocating %s: Resource %d: %pR\n", 1295 pci_name(dev), idx, r); 1296 1297 pr = pci_find_parent_resource(dev, r); 1298 if (!pr || (pr->flags & IORESOURCE_UNSET) || 1299 request_resource(pr, r) < 0) { 1300 printk(KERN_WARNING "PCI: Cannot allocate resource region %d" 1301 " of device %s, will remap\n", idx, pci_name(dev)); 1302 if (pr) 1303 pr_debug("PCI: parent is %p: %pR\n", pr, pr); 1304 /* We'll assign a new address later */ 1305 r->flags |= IORESOURCE_UNSET; 1306 r->end -= r->start; 1307 r->start = 0; 1308 } 1309} 1310 1311static void __init pcibios_allocate_resources(int pass) 1312{ 1313 struct pci_dev *dev = NULL; 1314 int idx, disabled; 1315 u16 command; 1316 struct resource *r; 1317 1318 for_each_pci_dev(dev) { 1319 pci_read_config_word(dev, PCI_COMMAND, &command); 1320 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) { 1321 r = &dev->resource[idx]; 1322 if (r->parent) /* Already allocated */ 1323 continue; 1324 if (!r->flags || (r->flags & IORESOURCE_UNSET)) 1325 continue; /* Not assigned at all */ 1326 /* We only allocate ROMs on pass 1 just in case they 1327 * have been screwed up by firmware 1328 */ 1329 if (idx == PCI_ROM_RESOURCE ) 1330 disabled = 1; 1331 if (r->flags & IORESOURCE_IO) 1332 disabled = !(command & PCI_COMMAND_IO); 1333 else 1334 disabled = !(command & PCI_COMMAND_MEMORY); 1335 if (pass == disabled) 1336 alloc_resource(dev, idx); 1337 } 1338 if (pass) 1339 continue; 1340 r = &dev->resource[PCI_ROM_RESOURCE]; 1341 if (r->flags) { 1342 /* Turn the ROM off, leave the resource region, 1343 * but keep it unregistered. 1344 */ 1345 u32 reg; 1346 pci_read_config_dword(dev, dev->rom_base_reg, ®); 1347 if (reg & PCI_ROM_ADDRESS_ENABLE) { 1348 pr_debug("PCI: Switching off ROM of %s\n", 1349 pci_name(dev)); 1350 r->flags &= ~IORESOURCE_ROM_ENABLE; 1351 pci_write_config_dword(dev, dev->rom_base_reg, 1352 reg & ~PCI_ROM_ADDRESS_ENABLE); 1353 } 1354 } 1355 } 1356} 1357 1358static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus) 1359{ 1360 struct pci_controller *hose = pci_bus_to_host(bus); 1361 resource_size_t offset; 1362 struct resource *res, *pres; 1363 int i; 1364 1365 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus)); 1366 1367 /* Check for IO */ 1368 if (!(hose->io_resource.flags & IORESOURCE_IO)) 1369 goto no_io; 1370 offset = (unsigned long)hose->io_base_virt - _IO_BASE; 1371 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 1372 BUG_ON(res == NULL); 1373 res->name = "Legacy IO"; 1374 res->flags = IORESOURCE_IO; 1375 res->start = offset; 1376 res->end = (offset + 0xfff) & 0xfffffffful; 1377 pr_debug("Candidate legacy IO: %pR\n", res); 1378 if (request_resource(&hose->io_resource, res)) { 1379 printk(KERN_DEBUG 1380 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n", 1381 pci_domain_nr(bus), bus->number, res); 1382 kfree(res); 1383 } 1384 1385 no_io: 1386 /* Check for memory */ 1387 for (i = 0; i < 3; i++) { 1388 pres = &hose->mem_resources[i]; 1389 offset = hose->mem_offset[i]; 1390 if (!(pres->flags & IORESOURCE_MEM)) 1391 continue; 1392 pr_debug("hose mem res: %pR\n", pres); 1393 if ((pres->start - offset) <= 0xa0000 && 1394 (pres->end - offset) >= 0xbffff) 1395 break; 1396 } 1397 if (i >= 3) 1398 return; 1399 res = kzalloc(sizeof(struct resource), GFP_KERNEL); 1400 BUG_ON(res == NULL); 1401 res->name = "Legacy VGA memory"; 1402 res->flags = IORESOURCE_MEM; 1403 res->start = 0xa0000 + offset; 1404 res->end = 0xbffff + offset; 1405 pr_debug("Candidate VGA memory: %pR\n", res); 1406 if (request_resource(pres, res)) { 1407 printk(KERN_DEBUG 1408 "PCI %04x:%02x Cannot reserve VGA memory %pR\n", 1409 pci_domain_nr(bus), bus->number, res); 1410 kfree(res); 1411 } 1412} 1413 1414void __init pcibios_resource_survey(void) 1415{ 1416 struct pci_bus *b; 1417 1418 /* Allocate and assign resources */ 1419 list_for_each_entry(b, &pci_root_buses, node) 1420 pcibios_allocate_bus_resources(b); 1421 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) { 1422 pcibios_allocate_resources(0); 1423 pcibios_allocate_resources(1); 1424 } 1425 1426 /* Before we start assigning unassigned resource, we try to reserve 1427 * the low IO area and the VGA memory area if they intersect the 1428 * bus available resources to avoid allocating things on top of them 1429 */ 1430 if (!pci_has_flag(PCI_PROBE_ONLY)) { 1431 list_for_each_entry(b, &pci_root_buses, node) 1432 pcibios_reserve_legacy_regions(b); 1433 } 1434 1435 /* Now, if the platform didn't decide to blindly trust the firmware, 1436 * we proceed to assigning things that were left unassigned 1437 */ 1438 if (!pci_has_flag(PCI_PROBE_ONLY)) { 1439 pr_debug("PCI: Assigning unassigned resources...\n"); 1440 pci_assign_unassigned_resources(); 1441 } 1442} 1443 1444/* This is used by the PCI hotplug driver to allocate resource 1445 * of newly plugged busses. We can try to consolidate with the 1446 * rest of the code later, for now, keep it as-is as our main 1447 * resource allocation function doesn't deal with sub-trees yet. 1448 */ 1449void pcibios_claim_one_bus(struct pci_bus *bus) 1450{ 1451 struct pci_dev *dev; 1452 struct pci_bus *child_bus; 1453 1454 list_for_each_entry(dev, &bus->devices, bus_list) { 1455 struct resource *r; 1456 int i; 1457 1458 pci_dev_for_each_resource(dev, r, i) { 1459 if (r->parent || !r->start || !r->flags) 1460 continue; 1461 1462 pr_debug("PCI: Claiming %s: Resource %d: %pR\n", 1463 pci_name(dev), i, r); 1464 1465 if (pci_claim_resource(dev, i) == 0) 1466 continue; 1467 1468 pci_claim_bridge_resource(dev, i); 1469 } 1470 } 1471 1472 list_for_each_entry(child_bus, &bus->children, node) 1473 pcibios_claim_one_bus(child_bus); 1474} 1475EXPORT_SYMBOL_GPL(pcibios_claim_one_bus); 1476 1477 1478/* pcibios_finish_adding_to_bus 1479 * 1480 * This is to be called by the hotplug code after devices have been 1481 * added to a bus, this include calling it for a PHB that is just 1482 * being added 1483 */ 1484void pcibios_finish_adding_to_bus(struct pci_bus *bus) 1485{ 1486 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n", 1487 pci_domain_nr(bus), bus->number); 1488 1489 /* Allocate bus and devices resources */ 1490 pcibios_allocate_bus_resources(bus); 1491 pcibios_claim_one_bus(bus); 1492 if (!pci_has_flag(PCI_PROBE_ONLY)) { 1493 if (bus->self) 1494 pci_assign_unassigned_bridge_resources(bus->self); 1495 else 1496 pci_assign_unassigned_bus_resources(bus); 1497 } 1498 1499 /* Add new devices to global lists. Register in proc, sysfs. */ 1500 pci_bus_add_devices(bus); 1501} 1502EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus); 1503 1504int pcibios_enable_device(struct pci_dev *dev, int mask) 1505{ 1506 struct pci_controller *phb = pci_bus_to_host(dev->bus); 1507 1508 if (phb->controller_ops.enable_device_hook) 1509 if (!phb->controller_ops.enable_device_hook(dev)) 1510 return -EINVAL; 1511 1512 return pci_enable_resources(dev, mask); 1513} 1514 1515void pcibios_disable_device(struct pci_dev *dev) 1516{ 1517 struct pci_controller *phb = pci_bus_to_host(dev->bus); 1518 1519 if (phb->controller_ops.disable_device) 1520 phb->controller_ops.disable_device(dev); 1521} 1522 1523resource_size_t pcibios_io_space_offset(struct pci_controller *hose) 1524{ 1525 return (unsigned long) hose->io_base_virt - _IO_BASE; 1526} 1527 1528static void pcibios_setup_phb_resources(struct pci_controller *hose, 1529 struct list_head *resources) 1530{ 1531 struct resource *res; 1532 resource_size_t offset; 1533 int i; 1534 1535 /* Hookup PHB IO resource */ 1536 res = &hose->io_resource; 1537 1538 if (!res->flags) { 1539 pr_debug("PCI: I/O resource not set for host" 1540 " bridge %pOF (domain %d)\n", 1541 hose->dn, hose->global_number); 1542 } else { 1543 offset = pcibios_io_space_offset(hose); 1544 1545 pr_debug("PCI: PHB IO resource = %pR off 0x%08llx\n", 1546 res, (unsigned long long)offset); 1547 pci_add_resource_offset(resources, res, offset); 1548 } 1549 1550 /* Hookup PHB Memory resources */ 1551 for (i = 0; i < 3; ++i) { 1552 res = &hose->mem_resources[i]; 1553 if (!res->flags) 1554 continue; 1555 1556 offset = hose->mem_offset[i]; 1557 pr_debug("PCI: PHB MEM resource %d = %pR off 0x%08llx\n", i, 1558 res, (unsigned long long)offset); 1559 1560 pci_add_resource_offset(resources, res, offset); 1561 } 1562} 1563 1564/* 1565 * Null PCI config access functions, for the case when we can't 1566 * find a hose. 1567 */ 1568#define NULL_PCI_OP(rw, size, type) \ 1569static int \ 1570null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \ 1571{ \ 1572 return PCIBIOS_DEVICE_NOT_FOUND; \ 1573} 1574 1575static int 1576null_read_config(struct pci_bus *bus, unsigned int devfn, int offset, 1577 int len, u32 *val) 1578{ 1579 return PCIBIOS_DEVICE_NOT_FOUND; 1580} 1581 1582static int 1583null_write_config(struct pci_bus *bus, unsigned int devfn, int offset, 1584 int len, u32 val) 1585{ 1586 return PCIBIOS_DEVICE_NOT_FOUND; 1587} 1588 1589static struct pci_ops null_pci_ops = 1590{ 1591 .read = null_read_config, 1592 .write = null_write_config, 1593}; 1594 1595/* 1596 * These functions are used early on before PCI scanning is done 1597 * and all of the pci_dev and pci_bus structures have been created. 1598 */ 1599static struct pci_bus * 1600fake_pci_bus(struct pci_controller *hose, int busnr) 1601{ 1602 static struct pci_bus bus; 1603 1604 if (hose == NULL) { 1605 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr); 1606 } 1607 bus.number = busnr; 1608 bus.sysdata = hose; 1609 bus.ops = hose? hose->ops: &null_pci_ops; 1610 return &bus; 1611} 1612 1613#define EARLY_PCI_OP(rw, size, type) \ 1614int early_##rw##_config_##size(struct pci_controller *hose, int bus, \ 1615 int devfn, int offset, type value) \ 1616{ \ 1617 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \ 1618 devfn, offset, value); \ 1619} 1620 1621EARLY_PCI_OP(read, byte, u8 *) 1622EARLY_PCI_OP(read, word, u16 *) 1623EARLY_PCI_OP(read, dword, u32 *) 1624EARLY_PCI_OP(write, byte, u8) 1625EARLY_PCI_OP(write, word, u16) 1626EARLY_PCI_OP(write, dword, u32) 1627 1628int early_find_capability(struct pci_controller *hose, int bus, int devfn, 1629 int cap) 1630{ 1631 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap); 1632} 1633 1634struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus) 1635{ 1636 struct pci_controller *hose = bus->sysdata; 1637 1638 return of_node_get(hose->dn); 1639} 1640 1641/** 1642 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus 1643 * @hose: Pointer to the PCI host controller instance structure 1644 */ 1645void pcibios_scan_phb(struct pci_controller *hose) 1646{ 1647 LIST_HEAD(resources); 1648 struct pci_bus *bus; 1649 struct device_node *node = hose->dn; 1650 int mode; 1651 1652 pr_debug("PCI: Scanning PHB %pOF\n", node); 1653 1654 /* Get some IO space for the new PHB */ 1655 pcibios_setup_phb_io_space(hose); 1656 1657 /* Wire up PHB bus resources */ 1658 pcibios_setup_phb_resources(hose, &resources); 1659 1660 hose->busn.start = hose->first_busno; 1661 hose->busn.end = hose->last_busno; 1662 hose->busn.flags = IORESOURCE_BUS; 1663 pci_add_resource(&resources, &hose->busn); 1664 1665 /* Create an empty bus for the toplevel */ 1666 bus = pci_create_root_bus(hose->parent, hose->first_busno, 1667 hose->ops, hose, &resources); 1668 if (bus == NULL) { 1669 pr_err("Failed to create bus for PCI domain %04x\n", 1670 hose->global_number); 1671 pci_free_resource_list(&resources); 1672 return; 1673 } 1674 hose->bus = bus; 1675 1676 /* Get probe mode and perform scan */ 1677 mode = PCI_PROBE_NORMAL; 1678 if (node && hose->controller_ops.probe_mode) 1679 mode = hose->controller_ops.probe_mode(bus); 1680 pr_debug(" probe mode: %d\n", mode); 1681 if (mode == PCI_PROBE_DEVTREE) 1682 of_scan_bus(node, bus); 1683 1684 if (mode == PCI_PROBE_NORMAL) { 1685 pci_bus_update_busn_res_end(bus, 255); 1686 hose->last_busno = pci_scan_child_bus(bus); 1687 pci_bus_update_busn_res_end(bus, hose->last_busno); 1688 } 1689 1690 /* Platform gets a chance to do some global fixups before 1691 * we proceed to resource allocation 1692 */ 1693 if (ppc_md.pcibios_fixup_phb) 1694 ppc_md.pcibios_fixup_phb(hose); 1695 1696 /* Configure PCI Express settings */ 1697 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) { 1698 struct pci_bus *child; 1699 list_for_each_entry(child, &bus->children, node) 1700 pcie_bus_configure_settings(child); 1701 } 1702} 1703EXPORT_SYMBOL_GPL(pcibios_scan_phb); 1704 1705static void fixup_hide_host_resource_fsl(struct pci_dev *dev) 1706{ 1707 int class = dev->class >> 8; 1708 /* When configured as agent, programming interface = 1 */ 1709 int prog_if = dev->class & 0xf; 1710 struct resource *r; 1711 1712 if ((class == PCI_CLASS_PROCESSOR_POWERPC || 1713 class == PCI_CLASS_BRIDGE_OTHER) && 1714 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) && 1715 (prog_if == 0) && 1716 (dev->bus->parent == NULL)) { 1717 pci_dev_for_each_resource(dev, r) { 1718 r->start = 0; 1719 r->end = 0; 1720 r->flags = 0; 1721 } 1722 } 1723} 1724DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl); 1725DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl); 1726 1727 1728static int __init discover_phbs(void) 1729{ 1730 if (ppc_md.discover_phbs) 1731 ppc_md.discover_phbs(); 1732 1733 return 0; 1734} 1735core_initcall(discover_phbs); 1736