1/* 2 * Copyright 2007, Fran��ois Revol, revol@free.fr. 3 * Distributed under the terms of the MIT License. 4 * 5 * Copyright 2003-2005, Axel D��rfler, axeld@pinc-software.de. 6 * Distributed under the terms of the MIT License. 7 * 8 * Copyright 2001, Travis Geiselbrecht. All rights reserved. 9 * Distributed under the terms of the NewOS License. 10 */ 11 12 13#include <KernelExport.h> 14 15#include <arch/cpu.h> 16#include <boot/kernel_args.h> 17 18 19status_t 20arch_cpu_preboot_init_percpu(kernel_args *args, int curr_cpu) 21{ 22 return B_OK; 23} 24 25 26status_t 27arch_cpu_init_percpu(kernel_args *args, int curr_cpu) 28{ 29 if (curr_cpu != 0) 30 panic("No SMP support on ARM yet!\n"); 31 32 return 0; 33} 34 35 36status_t 37arch_cpu_init(kernel_args *args) 38{ 39 return B_OK; 40} 41 42 43status_t 44arch_cpu_init_post_vm(kernel_args *args) 45{ 46 return B_OK; 47} 48 49 50status_t 51arch_cpu_init_post_modules(kernel_args *args) 52{ 53 return B_OK; 54} 55 56 57status_t 58arch_cpu_shutdown(bool reboot) 59{ 60 while(1) 61 arch_cpu_idle(); 62 63 // never reached 64 return B_ERROR; 65} 66 67 68void 69arch_cpu_sync_icache(void *address, size_t len) 70{ 71 uint32 Rd = 0; 72 asm volatile ("mcr p15, 0, %[c7format], c7, c5, 0" 73 : : [c7format] "r" (Rd) ); 74} 75 76 77void 78arch_cpu_invalidate_TLB_page(addr_t page) 79{ 80 // ensure visibility of the update to translation table walks 81 dsb(); 82 83 // TLBIMVAIS(page) 84 asm volatile ("mcr p15, 0, %0, c8, c3, 1" 85 : : "r" (page)); 86 87 // ensure completion of TLB invalidation 88 dsb(); 89 isb(); 90} 91 92void 93arch_cpu_invalidate_TLB_range(addr_t start, addr_t end) 94{ 95 // ensure visibility of the update to translation table walks 96 dsb(); 97 98 int32 num_pages = end / B_PAGE_SIZE - start / B_PAGE_SIZE; 99 while (num_pages-- >= 0) { 100 asm volatile ("mcr p15, 0, %[c8format], c8, c6, 1" 101 : : [c8format] "r" (start) ); 102 start += B_PAGE_SIZE; 103 } 104 105 // ensure completion of TLB invalidation 106 dsb(); 107 isb(); 108} 109 110 111void 112arch_cpu_invalidate_TLB_list(addr_t pages[], int num_pages) 113{ 114 // ensure visibility of the update to translation table walks 115 dsb(); 116 117 for (int i = 0; i < num_pages; i++) { 118 asm volatile ("mcr p15, 0, %[c8format], c8, c6, 1": 119 : [c8format] "r" (pages[i]) ); 120 } 121 122 // ensure completion of TLB invalidation 123 dsb(); 124 isb(); 125} 126 127 128void 129arch_cpu_global_TLB_invalidate(void) 130{ 131 // ensure visibility of the update to translation table walks 132 dsb(); 133 134 uint32 Rd = 0; 135 asm volatile ("mcr p15, 0, %[c8format], c8, c7, 0" 136 : : [c8format] "r" (Rd) ); 137 138 // ensure completion of TLB invalidation 139 dsb(); 140 isb(); 141} 142 143 144void 145arch_cpu_user_TLB_invalidate(void) 146{/* 147 cpu_ops.flush_insn_pipeline(); 148 cpu_ops.flush_atc_user(); 149 cpu_ops.flush_insn_pipeline(); 150*/ 151#warning WRITEME 152} 153