1/*- 2 * Copyright (c) 2000 Tsubai Masanari. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. The name of the author may not be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 24 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * from NetBSD: openpicreg.h,v 1.3 2001/08/30 03:08:52 briggs Exp 27 * $FreeBSD$ 28 */ 29 30#ifndef OPENPIC_H 31#define OPENPIC_H 32 33/* 34 * Size of OpenPIC register space 35 */ 36#define OPENPIC_SIZE 0x40000 37 38/* 39 * GLOBAL/TIMER register (IDU base + 0x1000) 40 */ 41 42/* feature reporting reg 0 */ 43#define OPENPIC_FEATURE 0x1000 44#define OPENPIC_FEATURE_VERSION_MASK 0x000000ff 45#define OPENPIC_FEATURE_LAST_CPU_MASK 0x00001f00 46#define OPENPIC_FEATURE_LAST_CPU_SHIFT 8 47#define OPENPIC_FEATURE_LAST_IRQ_MASK 0x07ff0000 48#define OPENPIC_FEATURE_LAST_IRQ_SHIFT 16 49 50/* global config reg 0 */ 51#define OPENPIC_CONFIG 0x1020 52#define OPENPIC_CONFIG_RESET 0x80000000 53#define OPENPIC_CONFIG_8259_PASSTHRU_DISABLE 0x20000000 54 55/* interrupt configuration mode (direct or serial) */ 56#define OPENPIC_ICR 0x1030 57#define OPENPIC_ICR_SERIAL_MODE (1 << 27) 58#define OPENPIC_ICR_SERIAL_RATIO_MASK (0x7 << 28) 59#define OPENPIC_ICR_SERIAL_RATIO_SHIFT 28 60 61/* processor initialization reg */ 62#define OPENPIC_PROC_INIT 0x1090 63 64/* IPI vector/priority reg */ 65#define OPENPIC_IPI_VECTOR(ipi) (0x10a0 + (ipi) * 0x10) 66 67/* spurious intr. vector */ 68#define OPENPIC_SPURIOUS_VECTOR 0x10e0 69 70 71/* 72 * INTERRUPT SOURCE register (IDU base + 0x10000) 73 */ 74 75/* interrupt vector/priority reg */ 76#ifndef OPENPIC_SRC_VECTOR 77#define OPENPIC_SRC_VECTOR(irq) (0x10000 + (irq) * 0x20) 78#endif 79#define OPENPIC_SENSE_LEVEL 0x00400000 80#define OPENPIC_SENSE_EDGE 0x00000000 81#define OPENPIC_POLARITY_POSITIVE 0x00800000 82#define OPENPIC_POLARITY_NEGATIVE 0x00000000 83#define OPENPIC_IMASK 0x80000000 84#define OPENPIC_ACTIVITY 0x40000000 85#define OPENPIC_PRIORITY_MASK 0x000f0000 86#define OPENPIC_PRIORITY_SHIFT 16 87#define OPENPIC_VECTOR_MASK 0x000000ff 88 89/* interrupt destination cpu */ 90#ifndef OPENPIC_IDEST 91#define OPENPIC_IDEST(irq) (0x10010 + (irq) * 0x20) 92#endif 93 94/* 95 * PROCESSOR register (IDU base + 0x20000) 96 */ 97 98/* IPI command reg */ 99#define OPENPIC_IPI(cpu, ipi) (0x20040 + (cpu) * 0x1000 + (ipi)) 100 101/* current task priority reg */ 102#define OPENPIC_CPU_PRIORITY(cpu) (0x20080 + (cpu) * 0x1000) 103#define OPENPIC_CPU_PRIORITY_MASK 0x0000000f 104 105/* interrupt acknowledge reg */ 106#define OPENPIC_IACK(cpu) (0x200a0 + (cpu) * 0x1000) 107 108/* end of interrupt reg */ 109#define OPENPIC_EOI(cpu) (0x200b0 + (cpu) * 0x1000) 110 111#endif // OPENPIC_H 112