1/*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 5 * Copyright (c) 2002-2008 Atheros Communications, Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 * 19 * $FreeBSD: releng/12.0/sys/dev/ath/ath_hal/ar5416/ar5416desc.h 326695 2017-12-08 15:57:29Z pfg $ 20 */ 21#ifndef _ATH_AR5416_DESC_H_ 22#define _ATH_AR5416_DESC_H_ 23 24/* 25 * Hardware-specific descriptor structures. 26 */ 27 28/* XXX Need to replace this with a dynamic 29 * method of determining Owl2 if possible 30 */ 31#define _get_index(_ah) ( IS_5416V1(_ah) ? -4 : 0 ) 32#define AR5416_DS_TXSTATUS(_ah, _ads) \ 33 ((uint32_t*)(&(_ads)->u.tx.status[_get_index(_ah)])) 34#define AR5416_DS_TXSTATUS_CONST(_ah, _ads) \ 35 ((const uint32_t*)(&(_ads)->u.tx.status[_get_index(_ah)])) 36 37#define AR5416_NUM_TX_STATUS 10 /* Number of TX status words */ 38/* Clear the whole descriptor */ 39#define AR5416_DESC_TX_CTL_SZ sizeof(struct ar5416_tx_desc) 40 41struct ar5416_tx_desc { /* tx desc has 12 control words + 10 status words */ 42 uint32_t ctl2; 43 uint32_t ctl3; 44 uint32_t ctl4; 45 uint32_t ctl5; 46 uint32_t ctl6; 47 uint32_t ctl7; 48 uint32_t ctl8; 49 uint32_t ctl9; 50 uint32_t ctl10; 51 uint32_t ctl11; 52 uint32_t status[AR5416_NUM_TX_STATUS]; 53}; 54 55struct ar5416_rx_desc { /* rx desc has 2 control words + 9 status words */ 56 uint32_t status0; 57 uint32_t status1; 58 uint32_t status2; 59 uint32_t status3; 60 uint32_t status4; 61 uint32_t status5; 62 uint32_t status6; 63 uint32_t status7; 64 uint32_t status8; 65}; 66 67struct ar5416_desc { 68 uint32_t ds_link; /* link pointer */ 69 uint32_t ds_data; /* data buffer pointer */ 70 uint32_t ds_ctl0; /* DMA control 0 */ 71 uint32_t ds_ctl1; /* DMA control 1 */ 72 union { 73 struct ar5416_tx_desc tx; 74 struct ar5416_rx_desc rx; 75 } u; 76} __packed; 77#define AR5416DESC(_ds) ((struct ar5416_desc *)(_ds)) 78#define AR5416DESC_CONST(_ds) ((const struct ar5416_desc *)(_ds)) 79 80#define ds_ctl2 u.tx.ctl2 81#define ds_ctl3 u.tx.ctl3 82#define ds_ctl4 u.tx.ctl4 83#define ds_ctl5 u.tx.ctl5 84#define ds_ctl6 u.tx.ctl6 85#define ds_ctl7 u.tx.ctl7 86#define ds_ctl8 u.tx.ctl8 87#define ds_ctl9 u.tx.ctl9 88#define ds_ctl10 u.tx.ctl10 89#define ds_ctl11 u.tx.ctl11 90 91#define ds_rxstatus0 u.rx.status0 92#define ds_rxstatus1 u.rx.status1 93#define ds_rxstatus2 u.rx.status2 94#define ds_rxstatus3 u.rx.status3 95#define ds_rxstatus4 u.rx.status4 96#define ds_rxstatus5 u.rx.status5 97#define ds_rxstatus6 u.rx.status6 98#define ds_rxstatus7 u.rx.status7 99#define ds_rxstatus8 u.rx.status8 100 101/*********** 102 * TX Desc * 103 ***********/ 104 105/* ds_ctl0 */ 106#define AR_FrameLen 0x00000fff 107#define AR_VirtMoreFrag 0x00001000 108#define AR_TxCtlRsvd00 0x0000e000 109#define AR_XmitPower 0x003f0000 110#define AR_XmitPower_S 16 111#define AR_RTSEnable 0x00400000 112#define AR_VEOL 0x00800000 113#define AR_ClrDestMask 0x01000000 114#define AR_TxCtlRsvd01 0x1e000000 115#define AR_TxIntrReq 0x20000000 116#define AR_DestIdxValid 0x40000000 117#define AR_CTSEnable 0x80000000 118 119/* ds_ctl1 */ 120#define AR_BufLen 0x00000fff 121#define AR_TxMore 0x00001000 122#define AR_DestIdx 0x000fe000 123#define AR_DestIdx_S 13 124#define AR_FrameType 0x00f00000 125#define AR_FrameType_S 20 126#define AR_NoAck 0x01000000 127#define AR_InsertTS 0x02000000 128#define AR_CorruptFCS 0x04000000 129#define AR_ExtOnly 0x08000000 130#define AR_ExtAndCtl 0x10000000 131#define AR_MoreAggr 0x20000000 132#define AR_IsAggr 0x40000000 133#define AR_MoreRifs 0x80000000 134 135/* ds_ctl2 */ 136#define AR_BurstDur 0x00007fff 137#define AR_BurstDur_S 0 138#define AR_DurUpdateEn 0x00008000 139#define AR_XmitDataTries0 0x000f0000 140#define AR_XmitDataTries0_S 16 141#define AR_XmitDataTries1 0x00f00000 142#define AR_XmitDataTries1_S 20 143#define AR_XmitDataTries2 0x0f000000 144#define AR_XmitDataTries2_S 24 145#define AR_XmitDataTries3 0xf0000000 146#define AR_XmitDataTries3_S 28 147 148/* ds_ctl3 */ 149#define AR_XmitRate0 0x000000ff 150#define AR_XmitRate0_S 0 151#define AR_XmitRate1 0x0000ff00 152#define AR_XmitRate1_S 8 153#define AR_XmitRate2 0x00ff0000 154#define AR_XmitRate2_S 16 155#define AR_XmitRate3 0xff000000 156#define AR_XmitRate3_S 24 157 158/* ds_ctl4 */ 159#define AR_PacketDur0 0x00007fff 160#define AR_PacketDur0_S 0 161#define AR_RTSCTSQual0 0x00008000 162#define AR_PacketDur1 0x7fff0000 163#define AR_PacketDur1_S 16 164#define AR_RTSCTSQual1 0x80000000 165 166/* ds_ctl5 */ 167#define AR_PacketDur2 0x00007fff 168#define AR_PacketDur2_S 0 169#define AR_RTSCTSQual2 0x00008000 170#define AR_PacketDur3 0x7fff0000 171#define AR_PacketDur3_S 16 172#define AR_RTSCTSQual3 0x80000000 173 174/* ds_ctl6 */ 175#define AR_AggrLen 0x0000ffff 176#define AR_AggrLen_S 0 177#define AR_TxCtlRsvd60 0x00030000 178#define AR_PadDelim 0x03fc0000 179#define AR_PadDelim_S 18 180#define AR_EncrType 0x0c000000 181#define AR_EncrType_S 26 182#define AR_TxCtlRsvd61 0xf0000000 183 184/* ds_ctl7 */ 185#define AR_2040_0 0x00000001 186#define AR_GI0 0x00000002 187#define AR_ChainSel0 0x0000001c 188#define AR_ChainSel0_S 2 189#define AR_2040_1 0x00000020 190#define AR_GI1 0x00000040 191#define AR_ChainSel1 0x00000380 192#define AR_ChainSel1_S 7 193#define AR_2040_2 0x00000400 194#define AR_GI2 0x00000800 195#define AR_ChainSel2 0x00007000 196#define AR_ChainSel2_S 12 197#define AR_2040_3 0x00008000 198#define AR_GI3 0x00010000 199#define AR_ChainSel3 0x000e0000 200#define AR_ChainSel3_S 17 201#define AR_RTSCTSRate 0x0ff00000 202#define AR_RTSCTSRate_S 20 203#define AR_STBC0 0x10000000 204#define AR_STBC1 0x20000000 205#define AR_STBC2 0x40000000 206#define AR_STBC3 0x80000000 207 208/* ds_ctl8 */ 209#define AR_AntCtl0 0x00ffffff 210#define AR_AntCtl0_S 0 211/* Xmit 0 TPC is AR_XmitPower in ctl0 */ 212 213/* ds_ctl9 */ 214#define AR_AntCtl1 0x00ffffff 215#define AR_AntCtl1_S 0 216#define AR_XmitPower1 0xff000000 217#define AR_XmitPower1_S 24 218 219/* ds_ctl10 */ 220#define AR_AntCtl2 0x00ffffff 221#define AR_AntCtl2_S 0 222#define AR_XmitPower2 0xff000000 223#define AR_XmitPower2_S 24 224 225/* ds_ctl11 */ 226#define AR_AntCtl3 0x00ffffff 227#define AR_AntCtl3_S 0 228#define AR_XmitPower3 0xff000000 229#define AR_XmitPower3_S 24 230 231/************* 232 * TX Status * 233 *************/ 234 235/* ds_status0 */ 236#define AR_TxRSSIAnt00 0x000000ff 237#define AR_TxRSSIAnt00_S 0 238#define AR_TxRSSIAnt01 0x0000ff00 239#define AR_TxRSSIAnt01_S 8 240#define AR_TxRSSIAnt02 0x00ff0000 241#define AR_TxRSSIAnt02_S 16 242#define AR_TxStatusRsvd00 0x3f000000 243#define AR_TxBaStatus 0x40000000 244#define AR_TxStatusRsvd01 0x80000000 245 246/* ds_status1 */ 247#define AR_FrmXmitOK 0x00000001 248#define AR_ExcessiveRetries 0x00000002 249#define AR_FIFOUnderrun 0x00000004 250#define AR_Filtered 0x00000008 251#define AR_RTSFailCnt 0x000000f0 252#define AR_RTSFailCnt_S 4 253#define AR_DataFailCnt 0x00000f00 254#define AR_DataFailCnt_S 8 255#define AR_VirtRetryCnt 0x0000f000 256#define AR_VirtRetryCnt_S 12 257#define AR_TxDelimUnderrun 0x00010000 258#define AR_TxDelimUnderrun_S 13 259#define AR_TxDataUnderrun 0x00020000 260#define AR_TxDataUnderrun_S 14 261#define AR_DescCfgErr 0x00040000 262#define AR_DescCfgErr_S 15 263#define AR_TxTimerExpired 0x00080000 264#define AR_TxStatusRsvd10 0xfff00000 265 266/* ds_status2 */ 267#define AR_SendTimestamp(_ptr) (_ptr)[2] 268 269/* ds_status3 */ 270#define AR_BaBitmapLow(_ptr) (_ptr)[3] 271 272/* ds_status4 */ 273#define AR_BaBitmapHigh(_ptr) (_ptr)[4] 274 275/* ds_status5 */ 276#define AR_TxRSSIAnt10 0x000000ff 277#define AR_TxRSSIAnt10_S 0 278#define AR_TxRSSIAnt11 0x0000ff00 279#define AR_TxRSSIAnt11_S 8 280#define AR_TxRSSIAnt12 0x00ff0000 281#define AR_TxRSSIAnt12_S 16 282#define AR_TxRSSICombined 0xff000000 283#define AR_TxRSSICombined_S 24 284 285/* ds_status6 */ 286#define AR_TxEVM0(_ptr) (_ptr)[6] 287 288/* ds_status7 */ 289#define AR_TxEVM1(_ptr) (_ptr)[7] 290 291/* ds_status8 */ 292#define AR_TxEVM2(_ptr) (_ptr)[8] 293 294/* ds_status9 */ 295#define AR_TxDone 0x00000001 296#define AR_SeqNum 0x00001ffe 297#define AR_SeqNum_S 1 298#define AR_TxStatusRsvd80 0x0001e000 299#define AR_TxOpExceeded 0x00020000 300#define AR_TxStatusRsvd81 0x001c0000 301#define AR_FinalTxIdx 0x00600000 302#define AR_FinalTxIdx_S 21 303#define AR_TxStatusRsvd82 0x01800000 304#define AR_PowerMgmt 0x02000000 305#define AR_TxTid 0xf0000000 306#define AR_TxTid_S 28 307#define AR_TxStatusRsvd83 0xfc000000 308 309/*********** 310 * RX Desc * 311 ***********/ 312 313/* ds_ctl0 */ 314#define AR_RxCTLRsvd00 0xffffffff 315 316/* ds_ctl1 */ 317#define AR_BufLen 0x00000fff 318#define AR_RxCtlRsvd00 0x00001000 319#define AR_RxIntrReq 0x00002000 320#define AR_RxCtlRsvd01 0xffffc000 321 322/************* 323 * Rx Status * 324 *************/ 325 326/* ds_status0 */ 327#define AR_RxRSSIAnt00 0x000000ff 328#define AR_RxRSSIAnt00_S 0 329#define AR_RxRSSIAnt01 0x0000ff00 330#define AR_RxRSSIAnt01_S 8 331#define AR_RxRSSIAnt02 0x00ff0000 332#define AR_RxRSSIAnt02_S 16 333/* Rev specific */ 334/* Owl 1.x only */ 335#define AR_RxStatusRsvd00 0xff000000 336/* Owl 2.x only */ 337#define AR_RxRate 0xff000000 338#define AR_RxRate_S 24 339 340/* ds_status1 */ 341#define AR_DataLen 0x00000fff 342#define AR_RxMore 0x00001000 343#define AR_NumDelim 0x003fc000 344#define AR_NumDelim_S 14 345#define AR_RxStatusRsvd10 0xff800000 346 347/* ds_status2 */ 348#define AR_RcvTimestamp ds_rxstatus2 349 350/* ds_status3 */ 351#define AR_GI 0x00000001 352#define AR_2040 0x00000002 353/* Rev specific */ 354/* Owl 1.x only */ 355#define AR_RxRateV1 0x000003fc 356#define AR_RxRateV1_S 2 357#define AR_Parallel40 0x00000400 358#define AR_RxStatusRsvd30 0xfffff800 359/* Owl 2.x only */ 360#define AR_DupFrame 0x00000004 361#define AR_STBCFrame 0x00000008 362#define AR_RxAntenna 0xffffff00 363#define AR_RxAntenna_S 8 364 365/* ds_status4 */ 366#define AR_RxRSSIAnt10 0x000000ff 367#define AR_RxRSSIAnt10_S 0 368#define AR_RxRSSIAnt11 0x0000ff00 369#define AR_RxRSSIAnt11_S 8 370#define AR_RxRSSIAnt12 0x00ff0000 371#define AR_RxRSSIAnt12_S 16 372#define AR_RxRSSICombined 0xff000000 373#define AR_RxRSSICombined_S 24 374 375/* ds_status5 */ 376#define AR_RxEVM0 ds_rxstatus5 377 378/* ds_status6 */ 379#define AR_RxEVM1 ds_rxstatus6 380 381/* ds_status7 */ 382#define AR_RxEVM2 ds_rxstatus7 383 384/* ds_status8 */ 385#define AR_RxDone 0x00000001 386#define AR_RxFrameOK 0x00000002 387#define AR_CRCErr 0x00000004 388#define AR_DecryptCRCErr 0x00000008 389#define AR_PHYErr 0x00000010 390#define AR_MichaelErr 0x00000020 391#define AR_PreDelimCRCErr 0x00000040 392#define AR_RxStatusRsvd70 0x00000080 393#define AR_RxKeyIdxValid 0x00000100 394#define AR_KeyIdx 0x0000fe00 395#define AR_KeyIdx_S 9 396#define AR_PHYErrCode 0x0000ff00 397#define AR_PHYErrCode_S 8 398#define AR_RxMoreAggr 0x00010000 399#define AR_RxAggr 0x00020000 400#define AR_PostDelimCRCErr 0x00040000 401#define AR_RxStatusRsvd71 0x2ff80000 402#define AR_HiRxChain 0x10000000 403#define AR_DecryptBusyErr 0x40000000 404#define AR_KeyMiss 0x80000000 405 406#define TXCTL_OFFSET(ah) 2 407#define TXCTL_NUMWORDS(ah) (AR_SREV_5416_V20_OR_LATER(ah) ? 12 : 8) 408#define TXSTATUS_OFFSET(ah) (AR_SREV_5416_V20_OR_LATER(ah) ? 14 : 10) 409#define TXSTATUS_NUMWORDS(ah) 10 410 411#define RXCTL_OFFSET(ah) 3 412#define RXCTL_NUMWORDS(ah) 1 413#define RXSTATUS_OFFSET(ah) 4 414#define RXSTATUS_NUMWORDS(ah) 9 415#define RXSTATUS_RATE(ah, ads) \ 416 (AR_SREV_5416_V20_OR_LATER(ah) ? \ 417 MS((ads)->ds_rxstatus0, AR_RxRate) : \ 418 ((ads)->ds_rxstatus3 >> 2) & 0xFF) 419#define RXSTATUS_DUPLICATE(ah, ads) \ 420 (AR_SREV_5416_V20_OR_LATER(ah) ? \ 421 MS((ads)->ds_rxstatus3, AR_Parallel40) : \ 422 ((ads)->ds_rxstatus3 >> 10) & 0x1) 423#endif /* _ATH_AR5416_DESC_H_ */ 424