1/*-
2 * SPDX-License-Identifier: ISC
3 *
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 * $FreeBSD: releng/12.0/sys/dev/ath/ath_hal/ar5312/ar5312_misc.c 326695 2017-12-08 15:57:29Z pfg $
20 */
21#include "opt_ah.h"
22
23#ifdef AH_SUPPORT_AR5312
24
25#include "ah.h"
26#include "ah_internal.h"
27#include "ah_devid.h"
28
29#include "ar5312/ar5312.h"
30#include "ar5312/ar5312reg.h"
31#include "ar5312/ar5312phy.h"
32
33#define	AR_NUM_GPIO	6		/* 6 GPIO pins */
34#define	AR_GPIOD_MASK	0x0000002F	/* GPIO data reg r/w mask */
35
36/*
37 * Change the LED blinking pattern to correspond to the connectivity
38 */
39void
40ar5312SetLedState(struct ath_hal *ah, HAL_LED_STATE state)
41{
42	uint32_t val;
43	uint32_t resOffset = (AR5312_RSTIMER_BASE - ((uint32_t) ah->ah_sh));
44    if(IS_2316(ah)) return; /* not yet */
45	val = SM(AR5312_PCICFG_LEDSEL0, AR5312_PCICFG_LEDSEL) |
46		SM(AR5312_PCICFG_LEDMOD0, AR5312_PCICFG_LEDMODE) |
47		2;
48	OS_REG_WRITE(ah, resOffset+AR5312_PCICFG,
49		(OS_REG_READ(ah, AR5312_PCICFG) &~
50		 (AR5312_PCICFG_LEDSEL | AR5312_PCICFG_LEDMODE |
51		  AR5312_PCICFG_LEDSBR))
52		     | val);
53}
54
55/*
56 * Detect if our wireless mac is present.
57 */
58HAL_BOOL
59ar5312DetectCardPresent(struct ath_hal *ah)
60{
61	uint16_t macVersion, macRev;
62	uint32_t v;
63
64	/*
65	 * Read the Silicon Revision register and compare that
66	 * to what we read at attach time.  If the same, we say
67	 * a card/device is present.
68	 */
69#if (AH_SUPPORT_2316 || AH_SUPPORT_2317)
70    if(IS_5315(ah))
71    {
72		v = (OS_REG_READ(ah,
73                         (AR5315_RSTIMER_BASE-((uint32_t) ah->ah_sh)) + AR5315_WREV))
74			& AR_SREV_ID;
75		macVersion = v >> AR_SREV_ID_S;
76		macRev = v & AR_SREV_REVISION;
77		return (AH_PRIVATE(ah)->ah_macVersion == macVersion &&
78				AH_PRIVATE(ah)->ah_macRev == macRev);
79    }
80    else
81#endif
82    {
83		v = (OS_REG_READ(ah,
84                         (AR5312_RSTIMER_BASE-((uint32_t) ah->ah_sh)) + AR5312_WREV))
85			& AR_SREV_ID;
86		macVersion = v >> AR_SREV_ID_S;
87		macRev = v & AR_SREV_REVISION;
88		return (AH_PRIVATE(ah)->ah_macVersion == macVersion &&
89				AH_PRIVATE(ah)->ah_macRev == macRev);
90    }
91}
92
93/*
94 * If 32KHz clock exists, use it to lower power consumption during sleep
95 *
96 * Note: If clock is set to 32 KHz, delays on accessing certain
97 *       baseband registers (27-31, 124-127) are required.
98 */
99void
100ar5312SetupClock(struct ath_hal *ah, HAL_OPMODE opmode)
101{
102	if (ar5212Use32KHzclock(ah, opmode)) {
103		/*
104		 * Enable clocks to be turned OFF in BB during sleep
105		 * and also enable turning OFF 32MHz/40MHz Refclk
106		 * from A2.
107		 */
108		OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);
109		OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT,   0x0d);
110		OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL,        0x0c);
111		OS_REG_WRITE(ah, AR_PHY_M_SLEEP,           0x03);
112		OS_REG_WRITE(ah, AR_PHY_REFCLKDLY,         0x05);
113		OS_REG_WRITE(ah, AR_PHY_REFCLKPD,
114		    IS_RAD5112_ANY(ah) ? 0x14 : 0x18);
115
116		OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32, 1);
117		OS_REG_WRITE(ah, AR_TSF_PARM, 61);	/* 32 KHz TSF incr */
118
119	} else {
120		OS_REG_WRITE(ah, AR_TSF_PARM, 1);	/* 32 MHz TSF incr */
121		OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32,
122		    IS_RAD5112_ANY(ah) ? 39 : 31);
123
124		OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);
125		OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT,   0x7f);
126
127		if (IS_5312_2_X(ah)) {
128			/* Set ADC/DAC select values */
129			OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL,        0x04);
130		} else {
131			OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL,        0x0e);
132			OS_REG_WRITE(ah, AR_PHY_M_SLEEP,           0x0c);
133			OS_REG_WRITE(ah, AR_PHY_REFCLKDLY,         0xff);
134			OS_REG_WRITE(ah, AR_PHY_REFCLKPD,
135			    IS_RAD5112_ANY(ah) ? 0x14 : 0x18);
136		}
137	}
138}
139
140/*
141 * If 32KHz clock exists, turn it off and turn back on the 32Mhz
142 */
143void
144ar5312RestoreClock(struct ath_hal *ah, HAL_OPMODE opmode)
145{
146	if (ar5212Use32KHzclock(ah, opmode)) {
147		/* # Set sleep clock rate back to 32 MHz. */
148		OS_REG_WRITE(ah, AR_TSF_PARM, 1);	/* 32 MHz TSF incr */
149		OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32,
150		    IS_RAD5112_ANY(ah) ? 39 : 31);
151
152		/*
153		 * Restore BB registers to power-on defaults
154		 */
155		OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);
156		OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT,   0x7f);
157		if (IS_5312_2_X(ah)) {
158			/* Set ADC/DAC select values */
159			OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL,        0x04);
160		} else {
161			OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL,        0x0e);
162			OS_REG_WRITE(ah, AR_PHY_M_SLEEP,           0x0c);
163			OS_REG_WRITE(ah, AR_PHY_REFCLKDLY,         0xff);
164			OS_REG_WRITE(ah, AR_PHY_REFCLKPD,
165			    IS_RAD5112_ANY(ah) ? 0x14 : 0x18);
166		}
167	}
168}
169
170#endif /* AH_SUPPORT_AR5312 */
171