1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016 Nicole Graziano <nicole@nextbsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/*$FreeBSD$*/ 30 31#ifndef _EM_H_DEFINED_ 32#define _EM_H_DEFINED_ 33 34#ifndef __HAIKU__ 35#include "opt_ddb.h" 36#include "opt_inet.h" 37#include "opt_inet6.h" 38#include "opt_rss.h" 39#endif 40 41#ifdef HAVE_KERNEL_OPTION_HEADERS 42#include "opt_device_polling.h" 43#endif 44 45#include <sys/param.h> 46#include <sys/systm.h> 47#ifdef DDB 48#include <sys/types.h> 49#include <ddb/ddb.h> 50#endif 51#include <sys/buf_ring.h> 52#include <sys/bus.h> 53#include <sys/endian.h> 54#include <sys/kernel.h> 55#include <sys/kthread.h> 56#include <sys/malloc.h> 57#include <sys/mbuf.h> 58#include <sys/module.h> 59#include <sys/rman.h> 60#include <sys/smp.h> 61#include <sys/socket.h> 62#include <sys/sockio.h> 63#include <sys/sysctl.h> 64#include <sys/taskqueue.h> 65#include <sys/eventhandler.h> 66#include <machine/bus.h> 67#include <machine/resource.h> 68 69#include <net/bpf.h> 70#include <net/ethernet.h> 71#include <net/if.h> 72#include <net/if_var.h> 73#include <net/if_arp.h> 74#include <net/if_dl.h> 75#include <net/if_media.h> 76#include <net/iflib.h> 77#ifdef RSS 78#include <net/rss_config.h> 79#include <netinet/in_rss.h> 80#endif 81 82#include <net/if_types.h> 83#include <net/if_vlan_var.h> 84 85#include <netinet/in_systm.h> 86#include <netinet/in.h> 87#include <netinet/if_ether.h> 88#include <netinet/ip.h> 89#include <netinet/ip6.h> 90#include <netinet/tcp.h> 91#include <netinet/udp.h> 92 93#include <machine/in_cksum.h> 94#include <dev/led/led.h> 95#include <dev/pci/pcivar.h> 96#include <dev/pci/pcireg.h> 97 98#include "e1000_api.h" 99#include "e1000_82571.h" 100#include "ifdi_if.h" 101 102/* Tunables */ 103 104/* 105 * EM_MAX_TXD: Maximum number of Transmit Descriptors 106 * Valid Range: 80-256 for 82542 and 82543-based adapters 107 * 80-4096 for others 108 * Default Value: 1024 109 * This value is the number of transmit descriptors allocated by the driver. 110 * Increasing this value allows the driver to queue more transmits. Each 111 * descriptor is 16 bytes. 112 * Since TDLEN should be multiple of 128bytes, the number of transmit 113 * desscriptors should meet the following condition. 114 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 115 */ 116#define EM_MIN_TXD 128 117#define EM_MAX_TXD 4096 118#define EM_DEFAULT_TXD 1024 119#define EM_DEFAULT_MULTI_TXD 4096 120#define IGB_MAX_TXD 4096 121 122/* 123 * EM_MAX_RXD - Maximum number of receive Descriptors 124 * Valid Range: 80-256 for 82542 and 82543-based adapters 125 * 80-4096 for others 126 * Default Value: 1024 127 * This value is the number of receive descriptors allocated by the driver. 128 * Increasing this value allows the driver to buffer more incoming packets. 129 * Each descriptor is 16 bytes. A receive buffer is also allocated for each 130 * descriptor. The maximum MTU size is 16110. 131 * Since TDLEN should be multiple of 128bytes, the number of transmit 132 * desscriptors should meet the following condition. 133 * (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0 134 */ 135#define EM_MIN_RXD 128 136#define EM_MAX_RXD 4096 137#define EM_DEFAULT_RXD 1024 138#define EM_DEFAULT_MULTI_RXD 4096 139#define IGB_MAX_RXD 4096 140 141/* 142 * EM_TIDV - Transmit Interrupt Delay Value 143 * Valid Range: 0-65535 (0=off) 144 * Default Value: 64 145 * This value delays the generation of transmit interrupts in units of 146 * 1.024 microseconds. Transmit interrupt reduction can improve CPU 147 * efficiency if properly tuned for specific network traffic. If the 148 * system is reporting dropped transmits, this value may be set too high 149 * causing the driver to run out of available transmit descriptors. 150 */ 151#define EM_TIDV 64 152 153/* 154 * EM_TADV - Transmit Absolute Interrupt Delay Value 155 * (Not valid for 82542/82543/82544) 156 * Valid Range: 0-65535 (0=off) 157 * Default Value: 64 158 * This value, in units of 1.024 microseconds, limits the delay in which a 159 * transmit interrupt is generated. Useful only if EM_TIDV is non-zero, 160 * this value ensures that an interrupt is generated after the initial 161 * packet is sent on the wire within the set amount of time. Proper tuning, 162 * along with EM_TIDV, may improve traffic throughput in specific 163 * network conditions. 164 */ 165#define EM_TADV 64 166 167/* 168 * EM_RDTR - Receive Interrupt Delay Timer (Packet Timer) 169 * Valid Range: 0-65535 (0=off) 170 * Default Value: 0 171 * This value delays the generation of receive interrupts in units of 1.024 172 * microseconds. Receive interrupt reduction can improve CPU efficiency if 173 * properly tuned for specific network traffic. Increasing this value adds 174 * extra latency to frame reception and can end up decreasing the throughput 175 * of TCP traffic. If the system is reporting dropped receives, this value 176 * may be set too high, causing the driver to run out of available receive 177 * descriptors. 178 * 179 * CAUTION: When setting EM_RDTR to a value other than 0, adapters 180 * may hang (stop transmitting) under certain network conditions. 181 * If this occurs a WATCHDOG message is logged in the system 182 * event log. In addition, the controller is automatically reset, 183 * restoring the network connection. To eliminate the potential 184 * for the hang ensure that EM_RDTR is set to 0. 185 */ 186#define EM_RDTR 0 187 188/* 189 * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544) 190 * Valid Range: 0-65535 (0=off) 191 * Default Value: 64 192 * This value, in units of 1.024 microseconds, limits the delay in which a 193 * receive interrupt is generated. Useful only if EM_RDTR is non-zero, 194 * this value ensures that an interrupt is generated after the initial 195 * packet is received within the set amount of time. Proper tuning, 196 * along with EM_RDTR, may improve traffic throughput in specific network 197 * conditions. 198 */ 199#define EM_RADV 64 200 201/* 202 * This parameter controls whether or not autonegotation is enabled. 203 * 0 - Disable autonegotiation 204 * 1 - Enable autonegotiation 205 */ 206#define DO_AUTO_NEG 1 207 208/* 209 * This parameter control whether or not the driver will wait for 210 * autonegotiation to complete. 211 * 1 - Wait for autonegotiation to complete 212 * 0 - Don't wait for autonegotiation to complete 213 */ 214#define WAIT_FOR_AUTO_NEG_DEFAULT 0 215 216/* Tunables -- End */ 217 218#define AUTONEG_ADV_DEFAULT (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 219 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 220 ADVERTISE_1000_FULL) 221 222#define AUTO_ALL_MODES 0 223 224/* PHY master/slave setting */ 225#define EM_MASTER_SLAVE e1000_ms_hw_default 226 227/* 228 * Miscellaneous constants 229 */ 230#define EM_VENDOR_ID 0x8086 231#define EM_FLASH 0x0014 232 233#define EM_JUMBO_PBA 0x00000028 234#define EM_DEFAULT_PBA 0x00000030 235#define EM_SMARTSPEED_DOWNSHIFT 3 236#define EM_SMARTSPEED_MAX 15 237#define EM_MAX_LOOP 10 238 239#define MAX_NUM_MULTICAST_ADDRESSES 128 240#define PCI_ANY_ID (~0U) 241#define ETHER_ALIGN 2 242#define EM_FC_PAUSE_TIME 0x0680 243#define EM_EEPROM_APME 0x400; 244#define EM_82544_APME 0x0004; 245 246/* Support AutoMediaDetect for Marvell M88 PHY in i354 */ 247#define IGB_MEDIA_RESET (1 << 0) 248 249/* Define the starting Interrupt rate per Queue */ 250#define IGB_INTS_PER_SEC 8000 251#define IGB_DEFAULT_ITR ((1000000/IGB_INTS_PER_SEC) << 2) 252 253#define IGB_LINK_ITR 2000 254#define I210_LINK_DELAY 1000 255 256#define IGB_TXPBSIZE 20408 257#define IGB_HDR_BUF 128 258#define IGB_PKTTYPE_MASK 0x0000FFF0 259#define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coalesce Flush */ 260 261/* 262 * Driver state logic for the detection of a hung state 263 * in hardware. Set TX_HUNG whenever a TX packet is used 264 * (data is sent) and clear it when txeof() is invoked if 265 * any descriptors from the ring are cleaned/reclaimed. 266 * Increment internal counter if no descriptors are cleaned 267 * and compare to TX_MAXTRIES. When counter > TX_MAXTRIES, 268 * reset adapter. 269 */ 270#define EM_TX_IDLE 0x00000000 271#define EM_TX_BUSY 0x00000001 272#define EM_TX_HUNG 0x80000000 273#define EM_TX_MAXTRIES 10 274 275#define PCICFG_DESC_RING_STATUS 0xe4 276#define FLUSH_DESC_REQUIRED 0x100 277 278 279#define IGB_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : \ 280 ((hw->mac.type <= e1000_82576) ? 16 : 8)) 281#define IGB_RX_HTHRESH 8 282#define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \ 283 (sc->intr_type == IFLIB_INTR_MSIX)) ? 1 : 4) 284 285#define IGB_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8) 286#define IGB_TX_HTHRESH 1 287#define IGB_TX_WTHRESH ((hw->mac.type != e1000_82575 && \ 288 sc->intr_type == IFLIB_INTR_MSIX) ? 1 : 16) 289 290/* 291 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be 292 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will 293 * also optimize cache line size effect. H/W supports up to cache line size 128. 294 */ 295#define EM_DBA_ALIGN 128 296 297/* 298 * See Intel 82574 Driver Programming Interface Manual, Section 10.2.6.9 299 */ 300#define TARC_COMPENSATION_MODE (1 << 7) /* Compensation Mode */ 301#define TARC_SPEED_MODE_BIT (1 << 21) /* On PCI-E MACs only */ 302#define TARC_MQ_FIX (1 << 23) | \ 303 (1 << 24) | \ 304 (1 << 25) /* Handle errata in MQ mode */ 305#define TARC_ERRATA_BIT (1 << 26) /* Note from errata on 82574 */ 306 307/* PCI Config defines */ 308#define EM_BAR_TYPE(v) ((v) & EM_BAR_TYPE_MASK) 309#define EM_BAR_TYPE_MASK 0x00000001 310#define EM_BAR_TYPE_MMEM 0x00000000 311#define EM_BAR_TYPE_IO 0x00000001 312#define EM_BAR_TYPE_FLASH 0x0014 313#define EM_BAR_MEM_TYPE(v) ((v) & EM_BAR_MEM_TYPE_MASK) 314#define EM_BAR_MEM_TYPE_MASK 0x00000006 315#define EM_BAR_MEM_TYPE_32BIT 0x00000000 316#define EM_BAR_MEM_TYPE_64BIT 0x00000004 317 318/* Defines for printing debug information */ 319#define DEBUG_INIT 0 320#define DEBUG_IOCTL 0 321#define DEBUG_HW 0 322 323#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 324#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 325#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 326#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 327#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 328#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 329#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 330#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 331#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 332 333#define EM_MAX_SCATTER 40 334#define EM_VFTA_SIZE 128 335#define EM_TSO_SIZE 65535 336#define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */ 337#define ETH_ZLEN 60 338#define EM_CSUM_OFFLOAD (CSUM_IP | CSUM_IP_UDP | CSUM_IP_TCP) /* Offload bits in mbuf flag */ 339#define IGB_CSUM_OFFLOAD (CSUM_IP | CSUM_IP_UDP | CSUM_IP_TCP | \ 340 CSUM_IP_SCTP | CSUM_IP6_UDP | CSUM_IP6_TCP | \ 341 CSUM_IP6_SCTP) /* Offload bits in mbuf flag */ 342 343#define IGB_PKTTYPE_MASK 0x0000FFF0 344#define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coalesce Flush */ 345 346/* 347 * 82574 has a nonstandard address for EIAC 348 * and since its only used in MSI-X, and in 349 * the em driver only 82574 uses MSI-X we can 350 * solve it just using this define. 351 */ 352#define EM_EIAC 0x000DC 353/* 354 * 82574 only reports 3 MSI-X vectors by default; 355 * defines assisting with making it report 5 are 356 * located here. 357 */ 358#define EM_NVM_PCIE_CTRL 0x1B 359#define EM_NVM_MSIX_N_MASK (0x7 << EM_NVM_MSIX_N_SHIFT) 360#define EM_NVM_MSIX_N_SHIFT 7 361 362struct e1000_softc; 363 364struct em_int_delay_info { 365 struct e1000_softc *sc; /* Back-pointer to the sc struct */ 366 int offset; /* Register offset to read/write */ 367 int value; /* Current value in usecs */ 368}; 369 370/* 371 * The transmit ring, one per tx queue 372 */ 373struct tx_ring { 374 struct e1000_softc *sc; 375 struct e1000_tx_desc *tx_base; 376 uint64_t tx_paddr; 377 qidx_t *tx_rsq; 378 bool tx_tso; /* last tx was tso */ 379 uint8_t me; 380 qidx_t tx_rs_cidx; 381 qidx_t tx_rs_pidx; 382 qidx_t tx_cidx_processed; 383 /* Interrupt resources */ 384 void *tag; 385 struct resource *res; 386 unsigned long tx_irq; 387 388 /* Saved csum offloading context information */ 389 int csum_flags; 390 int csum_lhlen; 391 int csum_iphlen; 392 393 int csum_thlen; 394 int csum_mss; 395 int csum_pktlen; 396 397 uint32_t csum_txd_upper; 398 uint32_t csum_txd_lower; /* last field */ 399}; 400 401/* 402 * The Receive ring, one per rx queue 403 */ 404struct rx_ring { 405 struct e1000_softc *sc; 406 struct em_rx_queue *que; 407 u32 me; 408 u32 payload; 409 union e1000_rx_desc_extended *rx_base; 410 uint64_t rx_paddr; 411 412 /* Interrupt resources */ 413 void *tag; 414 struct resource *res; 415 bool discard; 416 417 /* Soft stats */ 418 unsigned long rx_irq; 419 unsigned long rx_discarded; 420 unsigned long rx_packets; 421 unsigned long rx_bytes; 422}; 423 424struct em_tx_queue { 425 struct e1000_softc *sc; 426 u32 msix; 427 u32 eims; /* This queue's EIMS bit */ 428 u32 me; 429 struct tx_ring txr; 430}; 431 432struct em_rx_queue { 433 struct e1000_softc *sc; 434 u32 me; 435 u32 msix; 436 u32 eims; 437 struct rx_ring rxr; 438 u64 irqs; 439 struct if_irq que_irq; 440}; 441 442/* Our softc structure */ 443struct e1000_softc { 444 struct e1000_hw hw; 445 446 if_softc_ctx_t shared; 447 if_ctx_t ctx; 448#define tx_num_queues shared->isc_ntxqsets 449#define rx_num_queues shared->isc_nrxqsets 450#define intr_type shared->isc_intr 451 /* FreeBSD operating-system-specific structures. */ 452 struct e1000_osdep osdep; 453 device_t dev; 454 struct cdev *led_dev; 455 456 struct em_tx_queue *tx_queues; 457 struct em_rx_queue *rx_queues; 458 struct if_irq irq; 459 460 struct resource *memory; 461 struct resource *flash; 462 struct resource *ioport; 463 464 struct resource *res; 465 void *tag; 466 u32 linkvec; 467 u32 ivars; 468 469 struct ifmedia *media; 470 int msix; 471 int if_flags; 472 int em_insert_vlan_header; 473 u32 ims; 474 bool in_detach; 475 476 u32 flags; 477 /* Task for FAST handling */ 478 struct grouptask link_task; 479 480 u16 num_vlans; 481 u32 txd_cmd; 482 483 u32 tx_process_limit; 484 u32 rx_process_limit; 485 u32 rx_mbuf_sz; 486 487 /* Management and WOL features */ 488 u32 wol; 489 bool has_manage; 490 bool has_amt; 491 492 /* Multicast array memory */ 493 u8 *mta; 494 495 /* 496 ** Shadow VFTA table, this is needed because 497 ** the real vlan filter table gets cleared during 498 ** a soft reset and the driver needs to be able 499 ** to repopulate it. 500 */ 501 u32 shadow_vfta[EM_VFTA_SIZE]; 502 503 /* Info about the interface */ 504 u16 link_active; 505 u16 fc; 506 u16 link_speed; 507 u16 link_duplex; 508 u32 smartspeed; 509 u32 dmac; 510 int link_mask; 511 512 u64 que_mask; 513 514 /* We need to store this at attach due to e1000 hw/sw locking model */ 515 struct e1000_fw_version fw_ver; 516 517 struct em_int_delay_info tx_int_delay; 518 struct em_int_delay_info tx_abs_int_delay; 519 struct em_int_delay_info rx_int_delay; 520 struct em_int_delay_info rx_abs_int_delay; 521 struct em_int_delay_info tx_itr; 522 523 /* Misc stats maintained by the driver */ 524 unsigned long dropped_pkts; 525 unsigned long link_irq; 526 unsigned long rx_overruns; 527 unsigned long watchdog_events; 528 529 struct e1000_hw_stats stats; 530 u16 vf_ifp; 531}; 532 533/******************************************************************************** 534 * vendor_info_array 535 * 536 * This array contains the list of Subvendor/Subdevice IDs on which the driver 537 * should load. 538 * 539 ********************************************************************************/ 540typedef struct _em_vendor_info_t { 541 unsigned int vendor_id; 542 unsigned int device_id; 543 unsigned int subvendor_id; 544 unsigned int subdevice_id; 545 unsigned int index; 546} em_vendor_info_t; 547 548void em_dump_rs(struct e1000_softc *); 549 550#define EM_RSSRK_SIZE 4 551#define EM_RSSRK_VAL(key, i) (key[(i) * EM_RSSRK_SIZE] | \ 552 key[(i) * EM_RSSRK_SIZE + 1] << 8 | \ 553 key[(i) * EM_RSSRK_SIZE + 2] << 16 | \ 554 key[(i) * EM_RSSRK_SIZE + 3] << 24) 555#endif /* _EM_H_DEFINED_ */ 556