1/*-
2 * Copyright 2021 Intel Corp
3 * Copyright 2021 Rubicon Communications, LLC (Netgate)
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 * $FreeBSD$
7 */
8
9#ifndef _IGC_PHY_H_
10#define _IGC_PHY_H_
11
12void igc_init_phy_ops_generic(struct igc_hw *hw);
13s32  igc_null_read_reg(struct igc_hw *hw, u32 offset, u16 *data);
14void igc_null_phy_generic(struct igc_hw *hw);
15s32  igc_null_lplu_state(struct igc_hw *hw, bool active);
16s32  igc_null_write_reg(struct igc_hw *hw, u32 offset, u16 data);
17s32  igc_null_set_page(struct igc_hw *hw, u16 data);
18s32  igc_check_downshift_generic(struct igc_hw *hw);
19s32  igc_check_reset_block_generic(struct igc_hw *hw);
20s32  igc_get_phy_id(struct igc_hw *hw);
21void igc_phy_force_speed_duplex_setup(struct igc_hw *hw, u16 *phy_ctrl);
22s32  igc_phy_hw_reset_generic(struct igc_hw *hw);
23s32  igc_phy_reset_dsp_generic(struct igc_hw *hw);
24s32  igc_set_d3_lplu_state_generic(struct igc_hw *hw, bool active);
25s32  igc_setup_copper_link_generic(struct igc_hw *hw);
26s32  igc_phy_has_link_generic(struct igc_hw *hw, u32 iterations,
27				u32 usec_interval, bool *success);
28enum igc_phy_type igc_get_phy_type_from_id(u32 phy_id);
29s32  igc_determine_phy_address(struct igc_hw *hw);
30s32  igc_enable_phy_wakeup_reg_access_bm(struct igc_hw *hw, u16 *phy_reg);
31s32  igc_disable_phy_wakeup_reg_access_bm(struct igc_hw *hw, u16 *phy_reg);
32void igc_power_up_phy_copper(struct igc_hw *hw);
33void igc_power_down_phy_copper(struct igc_hw *hw);
34s32  igc_read_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 *data);
35s32  igc_write_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 data);
36
37s32 igc_read_xmdio_reg(struct igc_hw *hw, u16 addr, u8 dev_addr,
38			 u16 *data);
39s32 igc_write_xmdio_reg(struct igc_hw *hw, u16 addr, u8 dev_addr,
40			  u16 data);
41s32  igc_write_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 data);
42s32  igc_read_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 *data);
43
44#define IGC_MAX_PHY_ADDR		8
45
46/* IGP01IGC Specific Registers */
47#define IGP01IGC_PHY_PORT_CONFIG	0x10 /* Port Config */
48#define IGP01IGC_PHY_PORT_STATUS	0x11 /* Status */
49#define IGP01IGC_PHY_PORT_CTRL	0x12 /* Control */
50#define IGP01IGC_PHY_LINK_HEALTH	0x13 /* PHY Link Health */
51#define IGP02IGC_PHY_POWER_MGMT	0x19 /* Power Management */
52#define IGP01IGC_PHY_PAGE_SELECT	0x1F /* Page Select */
53#define BM_PHY_PAGE_SELECT		22   /* Page Select for BM */
54#define IGP_PAGE_SHIFT			5
55#define PHY_REG_MASK			0x1F
56#define IGC_I225_PHPM			0x0E14 /* I225 PHY Power Management */
57#define IGC_I225_PHPM_DIS_1000_D3	0x0008 /* Disable 1G in D3 */
58#define IGC_I225_PHPM_LINK_ENERGY	0x0010 /* Link Energy Detect */
59#define IGC_I225_PHPM_GO_LINKD	0x0020 /* Go Link Disconnect */
60#define IGC_I225_PHPM_DIS_1000	0x0040 /* Disable 1G globally */
61#define IGC_I225_PHPM_SPD_B2B_EN	0x0080 /* Smart Power Down Back2Back */
62#define IGC_I225_PHPM_RST_COMPL	0x0100 /* PHY Reset Completed */
63#define IGC_I225_PHPM_DIS_100_D3	0x0200 /* Disable 100M in D3 */
64#define IGC_I225_PHPM_ULP		0x0400 /* Ultra Low-Power Mode */
65#define IGC_I225_PHPM_DIS_2500	0x0800 /* Disable 2.5G globally */
66#define IGC_I225_PHPM_DIS_2500_D3	0x1000 /* Disable 2.5G in D3 */
67/* GPY211 - I225 defines */
68#define GPY_MMD_MASK			0xFFFF0000
69#define GPY_MMD_SHIFT			16
70#define GPY_REG_MASK			0x0000FFFF
71#define IGP01IGC_PHY_PCS_INIT_REG	0x00B4
72#define IGP01IGC_PHY_POLARITY_MASK	0x0078
73
74#define IGP01IGC_PSCR_AUTO_MDIX	0x1000
75#define IGP01IGC_PSCR_FORCE_MDI_MDIX	0x2000 /* 0=MDI, 1=MDIX */
76
77#define IGP01IGC_PSCFR_SMART_SPEED	0x0080
78
79#define IGP02IGC_PM_SPD		0x0001 /* Smart Power Down */
80#define IGP02IGC_PM_D0_LPLU		0x0002 /* For D0a states */
81#define IGP02IGC_PM_D3_LPLU		0x0004 /* For all other states */
82
83#define IGP01IGC_PLHR_SS_DOWNGRADE	0x8000
84
85#define IGP01IGC_PSSR_POLARITY_REVERSED	0x0002
86#define IGP01IGC_PSSR_MDIX		0x0800
87#define IGP01IGC_PSSR_SPEED_MASK	0xC000
88#define IGP01IGC_PSSR_SPEED_1000MBPS	0xC000
89
90#define IGP02IGC_PHY_CHANNEL_NUM	4
91#define IGP02IGC_PHY_AGC_A		0x11B1
92#define IGP02IGC_PHY_AGC_B		0x12B1
93#define IGP02IGC_PHY_AGC_C		0x14B1
94#define IGP02IGC_PHY_AGC_D		0x18B1
95
96#define IGP02IGC_AGC_LENGTH_SHIFT	9   /* Course=15:13, Fine=12:9 */
97#define IGP02IGC_AGC_LENGTH_MASK	0x7F
98#define IGP02IGC_AGC_RANGE		15
99
100#define IGC_CABLE_LENGTH_UNDEFINED	0xFF
101
102#define IGC_KMRNCTRLSTA_OFFSET	0x001F0000
103#define IGC_KMRNCTRLSTA_OFFSET_SHIFT	16
104#define IGC_KMRNCTRLSTA_REN		0x00200000
105#define IGC_KMRNCTRLSTA_DIAG_OFFSET	0x3    /* Kumeran Diagnostic */
106#define IGC_KMRNCTRLSTA_TIMEOUTS	0x4    /* Kumeran Timeouts */
107#define IGC_KMRNCTRLSTA_INBAND_PARAM	0x9    /* Kumeran InBand Parameters */
108#define IGC_KMRNCTRLSTA_IBIST_DISABLE	0x0200 /* Kumeran IBIST Disable */
109#define IGC_KMRNCTRLSTA_DIAG_NELPBK	0x1000 /* Nearend Loopback mode */
110
111#define IFE_PHY_EXTENDED_STATUS_CONTROL	0x10
112#define IFE_PHY_SPECIAL_CONTROL		0x11 /* 100BaseTx PHY Special Ctrl */
113#define IFE_PHY_SPECIAL_CONTROL_LED	0x1B /* PHY Special and LED Ctrl */
114#define IFE_PHY_MDIX_CONTROL		0x1C /* MDI/MDI-X Control */
115
116/* IFE PHY Extended Status Control */
117#define IFE_PESC_POLARITY_REVERSED	0x0100
118
119/* IFE PHY Special Control */
120#define IFE_PSC_AUTO_POLARITY_DISABLE	0x0010
121#define IFE_PSC_FORCE_POLARITY		0x0020
122
123/* IFE PHY Special Control and LED Control */
124#define IFE_PSCL_PROBE_MODE		0x0020
125#define IFE_PSCL_PROBE_LEDS_OFF		0x0006 /* Force LEDs 0 and 2 off */
126#define IFE_PSCL_PROBE_LEDS_ON		0x0007 /* Force LEDs 0 and 2 on */
127
128/* IFE PHY MDIX Control */
129#define IFE_PMC_MDIX_STATUS		0x0020 /* 1=MDI-X, 0=MDI */
130#define IFE_PMC_FORCE_MDIX		0x0040 /* 1=force MDI-X, 0=force MDI */
131#define IFE_PMC_AUTO_MDIX		0x0080 /* 1=enable auto, 0=disable */
132
133#endif
134